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Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
93.75 75.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.44 96.47 89.29 100.00 100.00 71.43 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 75.00 50.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
91.44 96.47 89.29 100.00 100.00 71.43 u_rv_core_ibex


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.64 94.64 93.18 94.74 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.64 94.64 93.18 94.74 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00 100.00 100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
95.64 94.64 93.18 94.74 100.00 u_socket


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
reqfifo 100.00 100.00 100.00
rspfifo 100.00 100.00 100.00

Go back
Module Instances:
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T18,T19 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T18,T19
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T17,T18,T19
0 Covered T1,T2,T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T18,T19 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT1,T2,T3
1CoveredT17,T18,T19
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T17,T18,T19
0 Covered T1,T2,T3

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT29,T30,T31 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT29,T30,T31
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T29,T30,T31
0 Covered T32,T33,T34

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT29,T30,T31 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT29,T30,T31
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T29,T30,T31
0 Covered T32,T33,T34

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d
TotalCoveredPercent
Conditions44100.00
Logical44100.00
Non-Logical00
Event00

 LINE       66
 SUB-EXPRESSION ((tl_d_i.d_opcode == AccessAckData) ? tl_d_i.d_data : ({top_pkg::TL_DW {1'b0}}))
                 -----------------1----------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT30,T31,T17 

 LINE       66
 SUB-EXPRESSION (tl_d_i.d_opcode == AccessAckData)
                -----------------1----------------
-1-StatusTests
0CoveredT32,T33,T34
1CoveredT30,T31,T17
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d
Line No.TotalCoveredPercent
Branches 2 2 100.00
TERNARY 66 2 2 100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv' or '../src/lowrisc_tlul_common_0.1/rtl/tlul_fifo_sync.sv was not found/opened, so annotated branch coverage report could not be generated.


	LineNo.	Expression
-1-:	66	((tl_d_i.d_opcode == AccessAckData)) ?

Branches:
-1-StatusTests
1 Covered T30,T31,T17
0 Covered T32,T33,T34

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