Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	339410793	41913867	0	0
DepthKnown_A	339410793	339312107	0	0
RvalidKnown_A	339410793	339312107	0	0
WreadyKnown_A	339410793	339312107	0	0
gen_passthru_fifo.paramCheckPass	948	948	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	41913867	0	0
T17	76680	8024	0	0
T18	154838	22520	0	0
T19	89980	10380	0	0
T20	237755	30797	0	0
T21	233791	30210	0	0
T41	739788	64790	0	0
T72	460206	11822	0	0
T73	153066	18448	0	0
T74	222948	28839	0	0
T75	114152	15341	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	339410793	31319661	0	0
DepthKnown_A	339410793	339312107	0	0
RvalidKnown_A	339410793	339312107	0	0
WreadyKnown_A	339410793	339312107	0	0
gen_passthru_fifo.paramCheckPass	948	948	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	31319661	0	0
T17	76680	6226	0	0
T18	154838	16535	0	0
T19	89980	8188	0	0
T20	237755	21375	0	0
T21	233791	20770	0	0
T41	739788	45681	0	0
T72	460206	8928	0	0
T73	153066	13158	0	0
T74	222948	19375	0	0
T75	114152	11894	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	339410793	30594999	0	0
DepthKnown_A	339410793	339312107	0	0
RvalidKnown_A	339410793	339312107	0	0
WreadyKnown_A	339410793	339312107	0	0
gen_passthru_fifo.paramCheckPass	948	948	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	30594999	0	0
T1	116944	3784	0	0
T2	172552	3964	0	0
T3	192566	3799	0	0
T7	130065	3812	0	0
T60	151506	2997	0	0
T61	172382	3526	0	0
T62	176444	5814	0	0
T63	140367	2404	0	0
T64	131483	2254	0	0
T65	146240	6112	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	339410793	25034617	0	0
DepthKnown_A	339410793	339312107	0	0
RvalidKnown_A	339410793	339312107	0	0
WreadyKnown_A	339410793	339312107	0	0
gen_passthru_fifo.paramCheckPass	948	948	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	25034617	0	0
T1	116944	1906	0	0
T2	172552	14044	0	0
T3	192566	15271	0	0
T7	130065	2362	0	0
T60	151506	10561	0	0
T61	172382	13204	0	0
T62	176444	4132	0	0
T63	140367	9048	0	0
T64	131483	8040	0	0
T65	146240	3022	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	339410793	339312107	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0
T63	140367	140196	0	0
T64	131483	131308	0	0
T65	146240	146083	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	948	948	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T60	1	1	0	0
T61	1	1	0	0
T62	1	1	0	0
T63	1	1	0	0
T64	1	1	0	0
T65	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416219523	89394	0	0
DepthKnown_A	416219523	416105270	0	0
RvalidKnown_A	416219523	416105270	0	0
WreadyKnown_A	416219523	416105270	0	0
gen_passthru_fifo.paramCheckPass	2857	2857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	89394	0	0
T17	76680	13	0	0
T18	154838	26	0	0
T19	89980	23	0	0
T20	237755	149	0	0
T21	233791	149	0	0
T29	189229	76	0	0
T30	325038	97	0	0
T31	264820	542	0	0
T41	739788	1588	0	0
T72	460206	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2857	2857	0	0
T29	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T104	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T301	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416219523	92338	0	0
DepthKnown_A	416219523	416105270	0	0
RvalidKnown_A	416219523	416105270	0	0
WreadyKnown_A	416219523	416105270	0	0
gen_passthru_fifo.paramCheckPass	2857	2857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	92338	0	0
T17	76680	13	0	0
T18	154838	26	0	0
T19	89980	23	0	0
T20	237755	149	0	0
T21	233791	149	0	0
T29	189229	76	0	0
T30	325038	97	0	0
T31	264820	542	0	0
T41	739788	1588	0	0
T72	460206	12	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2857	2857	0	0
T29	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T104	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T301	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416219523	48677	0	0
DepthKnown_A	416219523	416105270	0	0
RvalidKnown_A	416219523	416105270	0	0
WreadyKnown_A	416219523	416105270	0	0
gen_passthru_fifo.paramCheckPass	2857	2857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	48677	0	0
T17	76680	12	0	0
T18	154838	23	0	0
T19	89980	22	0	0
T20	237755	95	0	0
T21	233791	95	0	0
T41	739788	1572	0	0
T72	460206	11	0	0
T73	153066	24	0	0
T74	222948	95	0	0
T75	114152	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2857	2857	0	0
T29	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T104	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T301	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416219523	48677	0	0
DepthKnown_A	416219523	416105270	0	0
RvalidKnown_A	416219523	416105270	0	0
WreadyKnown_A	416219523	416105270	0	0
gen_passthru_fifo.paramCheckPass	2857	2857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	48677	0	0
T17	76680	12	0	0
T18	154838	23	0	0
T19	89980	22	0	0
T20	237755	95	0	0
T21	233791	95	0	0
T41	739788	1572	0	0
T72	460206	11	0	0
T73	153066	24	0	0
T74	222948	95	0	0
T75	114152	18	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2857	2857	0	0
T29	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T104	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T301	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416219523	40717	0	0
DepthKnown_A	416219523	416105270	0	0
RvalidKnown_A	416219523	416105270	0	0
WreadyKnown_A	416219523	416105270	0	0
gen_passthru_fifo.paramCheckPass	2857	2857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	40717	0	0
T17	76680	1	0	0
T18	154838	3	0	0
T19	89980	1	0	0
T20	237755	54	0	0
T21	233791	54	0	0
T29	189229	76	0	0
T30	325038	97	0	0
T31	264820	542	0	0
T41	739788	16	0	0
T72	460206	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2857	2857	0	0
T29	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T104	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T301	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	416219523	43661	0	0
DepthKnown_A	416219523	416105270	0	0
RvalidKnown_A	416219523	416105270	0	0
WreadyKnown_A	416219523	416105270	0	0
gen_passthru_fifo.paramCheckPass	2857	2857	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	43661	0	0
T17	76680	1	0	0
T18	154838	3	0	0
T19	89980	1	0	0
T20	237755	54	0	0
T21	233791	54	0	0
T29	189229	76	0	0
T30	325038	97	0	0
T31	264820	542	0	0
T41	739788	16	0	0
T72	460206	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	416219523	416105270	0	0
T1	116944	116791	0	0
T2	172552	172388	0	0
T3	192566	192392	0	0
T7	130065	129883	0	0
T29	189229	189105	0	0
T30	325038	324925	0	0
T31	264820	264804	0	0
T60	151506	151327	0	0
T61	172382	172211	0	0
T62	176444	176280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2857	2857	0	0
T29	1	1	0	0
T32	1	1	0	0
T33	1	1	0	0
T34	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T104	1	1	0	0
T186	1	1	0	0
T187	1	1	0	0
T301	1	1	0	0