Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	129226608	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	20934	20934	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	129226608	0	0
T1	233888	5690	0	0
T2	345104	18008	0	0
T3	385132	19070	0	0
T7	260130	6174	0	0
T17	230040	14263	0	0
T18	464514	39081	0	0
T19	269940	18591	0	0
T20	713265	52321	0	0
T21	701373	51129	0	0
T29	189229	76	0	0
T41	2219364	112059	0	0
T60	303012	13558	0	0
T61	344764	16730	0	0
T62	352888	9946	0	0
T63	280734	11452	0	0
T64	262966	10294	0	0
T65	292480	9134	0	0
T72	1380618	20762	0	0
T73	306132	31606	0	0
T74	445896	48214	0	0
T75	228304	27235	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1169440	1167910	0	0
T2	1725520	1723880	0	0
T3	1925660	1923920	0	0
T7	1300650	1298830	0	0
T29	1135374	1134630	0	0
T30	1950228	1949550	0	0
T31	1588920	1588824	0	0
T60	1515060	1513270	0	0
T61	1723820	1722110	0	0
T62	1764440	1762800	0	0
T63	561468	560784	0	0
T64	525932	525232	0	0
T65	584960	584332	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1169440	1167910	0	0
T2	1725520	1723880	0	0
T3	1925660	1923920	0	0
T7	1300650	1298830	0	0
T29	1135374	1134630	0	0
T30	1950228	1949550	0	0
T31	1588920	1588824	0	0
T60	1515060	1513270	0	0
T61	1723820	1722110	0	0
T62	1764440	1762800	0	0
T63	561468	560784	0	0
T64	525932	525232	0	0
T65	584960	584332	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1169440	1167910	0	0
T2	1725520	1723880	0	0
T3	1925660	1923920	0	0
T7	1300650	1298830	0	0
T29	1135374	1134630	0	0
T30	1950228	1949550	0	0
T31	1588920	1588824	0	0
T60	1515060	1513270	0	0
T61	1723820	1722110	0	0
T62	1764440	1762800	0	0
T63	561468	560784	0	0
T64	525932	525232	0	0
T65	584960	584332	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	20934	20934	0	0
T1	4	4	0	0
T2	4	4	0	0
T3	4	4	0	0
T7	4	4	0	0
T29	6	6	0	0
T32	6	6	0	0
T33	6	6	0	0
T34	6	6	0	0
T55	6	6	0	0
T56	6	6	0	0
T60	4	4	0	0
T61	4	4	0	0
T62	4	4	0	0
T63	4	4	0	0
T64	4	4	0	0
T65	4	4	0	0
T104	6	6	0	0
T186	6	6	0	0
T187	6	6	0	0
T301	6	6	0	0