Unified Coverage Report :: Group :: tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

Group : tl_agent_pkg::max_outstanding_cg::SHAPE{max_outstanding=64}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

3 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	64	0	64	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_max_outstanding_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_num_of_outstanding	64	0	64	100.00	100	1	1	0

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	3777090	1			T35	553		T36	534		T37	2076
values[2]	751852	1			T35	81		T36	169		T37	517
values[3]	104244	1			T35	7		T36	10		T37	1
values[4]	54059	1			T259	129		T258	2		T170	31
values[5]	35633	1			T259	146		T170	39		T423	6
values[6]	26563	1			T259	123		T170	19		T423	6
values[7]	21809	1			T259	136		T170	28		T423	6
values[8]	18696	1			T259	132		T170	34		T423	6
values[9]	16146	1			T259	137		T170	31		T423	6
values[10]	14655	1			T259	164		T170	12		T423	7
values[11]	13586	1			T259	127		T170	6		T423	6
values[12]	13096	1			T259	150		T170	17		T423	6
values[13]	12647	1			T259	122		T170	14		T423	6
values[14]	11919	1			T259	90		T170	13		T423	6
values[15]	11284	1			T259	113		T170	33		T423	6
values[16]	10762	1			T259	96		T170	13		T423	7
values[17]	10488	1			T259	99		T170	15		T423	6
values[18]	9986	1			T259	96		T170	13		T423	7
values[19]	9910	1			T259	121		T170	19		T423	6
values[20]	9275	1			T259	129		T170	17		T423	6
values[21]	9121	1			T259	128		T170	14		T423	6
values[22]	8881	1			T259	125		T170	29		T423	6
values[23]	8623	1			T259	112		T170	44		T423	6
values[24]	8216	1			T259	84		T170	51		T423	6
values[25]	8088	1			T259	87		T170	26		T423	6
values[26]	7929	1			T259	74		T170	8		T423	6
values[27]	7483	1			T259	80		T170	8		T423	6
values[28]	6927	1			T259	79		T170	7		T423	6
values[29]	6491	1			T259	84		T170	10		T423	7
values[30]	6130	1			T259	68		T170	7		T423	6
values[31]	5657	1			T259	41		T170	11		T423	6
values[32]	5033	1			T259	23		T170	11		T423	6
values[33]	4805	1			T259	26		T170	5		T423	6
values[34]	4445	1			T259	27		T170	2		T423	6
values[35]	4207	1			T259	17		T170	9		T423	6
values[36]	4018	1			T259	16		T170	2		T423	7
values[37]	3822	1			T259	16		T170	1		T423	6
values[38]	3621	1			T259	15		T170	2		T423	6
values[39]	3437	1			T259	10		T170	2		T423	6
values[40]	3235	1			T259	7		T170	2		T423	6
values[41]	3231	1			T259	7		T170	4		T423	6
values[42]	3189	1			T259	14		T170	1		T423	6
values[43]	3181	1			T259	9		T170	4		T423	6
values[44]	3063	1			T259	3		T170	1		T423	6
values[45]	3036	1			T259	3		T170	1		T423	6
values[46]	3050	1			T259	7		T170	1		T423	6
values[47]	2926	1			T259	9		T423	6		T114	5
values[48]	2793	1			T259	2		T423	6		T114	7
values[49]	2817	1			T259	2		T423	6		T114	6
values[50]	2620	1			T259	5		T423	6		T114	9
values[51]	2745	1			T259	6		T423	7		T114	12
values[52]	2742	1			T259	2		T423	6		T114	7
values[53]	2695	1			T259	2		T423	7		T114	8
values[54]	2570	1			T259	2		T423	6		T114	7
values[55]	2551	1			T259	3		T423	6		T114	6
values[56]	2575	1			T259	4		T423	6		T114	9
values[57]	2622	1			T259	1		T423	6		T114	9
values[58]	2543	1			T259	1		T423	6		T114	6
values[59]	2437	1			T259	1		T423	6		T114	5
values[60]	2404	1			T259	1		T423	7		T114	10
values[61]	2648	1			T259	1		T423	6		T114	13
values[62]	4149	1			T259	2		T423	6		T114	27
values[63]	15727	1			T259	13		T423	7		T114	87
values[64]	228294	1			T259	120		T423	1195		T114	330

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	4835701	1			T35	1665		T36	603		T37	1989
values[2]	795967	1			T35	249		T36	171		T37	521
values[3]	73497	1			T35	19		T36	31		T37	15
values[4]	13746	1			T35	2		T36	6		T50	2
values[5]	5208	1			T36	1		T259	5		T258	22
values[6]	3005	1			T259	5		T258	9		T423	2
values[7]	2227	1			T259	6		T258	3		T424	19
values[8]	1945	1			T259	2		T424	24		T387	4
values[9]	1653	1			T259	3		T424	13		T387	4
values[10]	1486	1			T259	4		T424	10		T387	4
values[11]	1434	1			T259	8		T424	8		T387	4
values[12]	1357	1			T259	4		T424	16		T387	4
values[13]	1331	1			T259	2		T424	13		T387	4
values[14]	1130	1			T259	5		T424	10		T387	4
values[15]	1087	1			T259	3		T424	8		T387	4
values[16]	1157	1			T259	2		T424	6		T387	4
values[17]	1052	1			T259	5		T424	2		T387	4
values[18]	902	1			T259	3		T424	4		T387	4
values[19]	816	1			T259	2		T424	4		T387	4
values[20]	749	1			T259	2		T424	5		T387	4
values[21]	737	1			T259	2		T424	7		T387	4
values[22]	660	1			T259	4		T424	2		T387	4
values[23]	702	1			T259	6		T424	5		T387	4
values[24]	638	1			T259	8		T424	2		T387	4
values[25]	578	1			T259	4		T424	2		T387	4
values[26]	596	1			T259	4		T424	4		T387	4
values[27]	628	1			T259	3		T424	3		T387	4
values[28]	665	1			T259	3		T424	2		T387	4
values[29]	610	1			T259	2		T424	2		T387	4
values[30]	547	1			T259	11		T424	6		T387	4
values[31]	510	1			T259	6		T424	3		T387	4
values[32]	519	1			T259	3		T424	4		T387	4
values[33]	544	1			T259	5		T424	7		T387	4
values[34]	530	1			T259	3		T424	6		T387	4
values[35]	491	1			T259	3		T424	6		T387	4
values[36]	460	1			T259	4		T424	4		T387	4
values[37]	505	1			T259	3		T424	9		T387	4
values[38]	468	1			T259	3		T424	4		T387	4
values[39]	448	1			T259	3		T424	4		T387	4
values[40]	433	1			T259	7		T424	2		T387	4
values[41]	444	1			T259	5		T424	3		T387	4
values[42]	470	1			T259	11		T424	4		T387	5
values[43]	441	1			T259	7		T424	7		T387	4
values[44]	421	1			T259	3		T424	10		T387	4
values[45]	443	1			T259	2		T424	3		T387	4
values[46]	435	1			T259	12		T424	2		T387	4
values[47]	456	1			T259	2		T424	5		T387	4
values[48]	418	1			T259	2		T424	5		T387	4
values[49]	419	1			T259	5		T424	3		T387	4
values[50]	412	1			T259	4		T424	2		T387	5
values[51]	409	1			T259	6		T424	4		T387	4
values[52]	404	1			T259	4		T424	3		T387	4
values[53]	376	1			T259	4		T424	2		T387	4
values[54]	380	1			T259	3		T424	3		T387	4
values[55]	354	1			T259	4		T424	2		T387	4
values[56]	386	1			T259	3		T424	2		T387	4
values[57]	378	1			T259	3		T424	5		T387	4
values[58]	371	1			T259	2		T424	4		T387	4
values[59]	377	1			T259	6		T424	5		T387	4
values[60]	379	1			T259	3		T424	3		T387	4
values[61]	412	1			T259	2		T424	2		T387	4
values[62]	662	1			T259	3		T424	17		T387	4
values[63]	3375	1			T259	16		T424	61		T387	4
values[64]	27591	1			T259	178		T424	180		T387	722

Summary for Variable cp_num_of_outstanding

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	64	0	64	100.00

User Defined Bins for cp_num_of_outstanding

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[1]	607443	1			T35	51		T36	10		T37	19
values[2]	2755431	1			T35	294		T36	228		T37	2113
values[3]	1112457	1			T35	362		T36	587		T37	576
values[4]	138853	1			T35	20		T36	37		T37	2
values[5]	71411	1			T35	2		T36	1		T259	178
values[6]	47050	1			T259	180		T170	34		T423	6
values[7]	34270	1			T259	149		T170	37		T423	6
values[8]	27007	1			T259	103		T170	25		T423	6
values[9]	22501	1			T259	149		T170	16		T423	6
values[10]	20141	1			T259	117		T170	12		T423	6
values[11]	17727	1			T259	126		T170	30		T423	6
values[12]	15694	1			T259	155		T170	28		T423	6
values[13]	14623	1			T259	153		T170	20		T423	7
values[14]	13886	1			T259	169		T170	50		T423	6
values[15]	13416	1			T259	175		T170	39		T423	6
values[16]	12844	1			T259	171		T170	21		T423	6
values[17]	12522	1			T259	168		T170	22		T423	6
values[18]	12125	1			T259	158		T170	14		T423	6
values[19]	12068	1			T259	138		T170	17		T423	6
values[20]	11521	1			T259	129		T170	25		T423	6
values[21]	10769	1			T259	143		T170	15		T423	6
values[22]	10216	1			T259	121		T170	17		T423	6
values[23]	9711	1			T259	103		T170	26		T423	6
values[24]	9363	1			T259	84		T170	8		T423	6
values[25]	8662	1			T259	103		T170	7		T423	6
values[26]	8227	1			T259	93		T170	18		T423	6
values[27]	8009	1			T259	109		T170	17		T423	6
values[28]	7705	1			T259	67		T170	21		T423	6
values[29]	7507	1			T259	86		T170	11		T423	6
values[30]	7050	1			T259	84		T170	3		T423	6
values[31]	6084	1			T259	60		T170	4		T423	6
values[32]	5774	1			T259	48		T170	10		T423	6
values[33]	5449	1			T259	37		T170	14		T423	6
values[34]	5030	1			T259	20		T170	7		T423	6
values[35]	4675	1			T259	29		T170	3		T423	6
values[36]	4398	1			T259	27		T423	7		T114	21
values[37]	4124	1			T259	17		T423	6		T114	6
values[38]	3842	1			T259	25		T423	6		T114	13
values[39]	3714	1			T259	21		T423	6		T114	13
values[40]	3520	1			T259	12		T423	6		T114	9
values[41]	3499	1			T259	22		T423	6		T114	10
values[42]	3452	1			T259	11		T423	6		T114	13
values[43]	3412	1			T259	20		T423	6		T114	9
values[44]	3344	1			T259	10		T423	6		T114	10
values[45]	3211	1			T259	6		T423	6		T114	6
values[46]	3223	1			T259	5		T423	7		T114	16
values[47]	3163	1			T259	4		T423	6		T114	14
values[48]	3180	1			T259	5		T423	6		T114	13
values[49]	3117	1			T259	6		T423	6		T114	16
values[50]	3000	1			T259	5		T423	6		T114	6
values[51]	2932	1			T259	5		T423	6		T114	19
values[52]	2928	1			T259	4		T423	6		T114	19
values[53]	2934	1			T259	4		T423	7		T114	18
values[54]	2758	1			T259	5		T423	6		T114	9
values[55]	2706	1			T259	6		T423	6		T114	9
values[56]	2652	1			T259	6		T423	6		T114	14
values[57]	2660	1			T259	12		T423	6		T114	12
values[58]	2640	1			T259	6		T423	6		T114	6
values[59]	2633	1			T259	3		T423	6		T114	9
values[60]	2484	1			T259	5		T423	6		T114	22
values[61]	2631	1			T259	4		T423	6		T114	24
values[62]	3714	1			T259	7		T423	6		T114	41
values[63]	17461	1			T259	3		T423	6		T114	123
values[64]	220562	1			T259	244		T423	1025		T114	180