Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/cover_reg_top/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

4 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64
tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__cored_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_core_ibex__corei_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

---

Group Instance : tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.rv_dm__sba_agent.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2196725	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

27654973

1

T33

48856

T34

2365

T1

1008

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	19646077	1			T33	24262		T34	4642		T23	135
values[0x0]	8450652	1			T33	12179		T34	39		T1	900
values[0x1]	1754969	1			T33	12415		T34	40		T1	980

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	578695	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

29273003

1

T33

48856

T34

3158

T1

1346

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	13849487	1			T33	686		T34	69		T2	63
valid_sources[0x01]	13848309	1			T33	788		T34	68		T2	63
valid_sources[0x02]	35031	1			T33	727		T34	77		T2	63
valid_sources[0x03]	34075	1			T33	821		T34	55		T2	65
valid_sources[0x04]	35641	1			T33	936		T34	92		T1	16
valid_sources[0x05]	34198	1			T33	707		T34	84		T2	44
valid_sources[0x06]	35417	1			T33	704		T34	91		T2	76
valid_sources[0x07]	35417	1			T33	669		T34	79		T1	16
valid_sources[0x08]	35951	1			T33	903		T34	42		T2	73
valid_sources[0x09]	34752	1			T33	692		T34	96		T2	57
valid_sources[0x0a]	34980	1			T33	657		T34	68		T2	54
valid_sources[0x0b]	34561	1			T33	677		T34	114		T2	58
valid_sources[0x0c]	33783	1			T33	807		T34	71		T1	16
valid_sources[0x0d]	33935	1			T33	800		T34	92		T2	48
valid_sources[0x0e]	34852	1			T33	657		T34	48		T1	16
valid_sources[0x0f]	35115	1			T33	654		T34	81		T2	61
valid_sources[0x10]	34787	1			T33	826		T34	71		T2	60
valid_sources[0x11]	34718	1			T33	918		T34	114		T2	59
valid_sources[0x12]	35784	1			T33	758		T34	73		T2	47
valid_sources[0x13]	34934	1			T33	705		T34	67		T2	61
valid_sources[0x14]	34224	1			T33	704		T34	91		T2	56
valid_sources[0x15]	35346	1			T33	787		T34	68		T2	62
valid_sources[0x16]	35645	1			T33	988		T34	41		T1	337
valid_sources[0x17]	35259	1			T33	805		T34	83		T2	67
valid_sources[0x18]	34127	1			T33	626		T34	49		T2	72
valid_sources[0x19]	33971	1			T33	799		T34	64		T2	41
valid_sources[0x1a]	37616	1			T33	621		T34	71		T2	62
valid_sources[0x1b]	34303	1			T33	758		T34	81		T2	57
valid_sources[0x1c]	34238	1			T33	729		T34	63		T2	58
valid_sources[0x1d]	35257	1			T33	896		T34	80		T2	77
valid_sources[0x1e]	34287	1			T33	892		T34	65		T2	62
valid_sources[0x1f]	34606	1			T33	715		T34	83		T2	63
valid_sources[0x20]	34012	1			T33	770		T34	82		T2	60

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

19011095

1

T33

24262

T34

2293

T23

135

values[0x0]

all_enables

biggest_size

8405139

1

T33

12179

T34

38

T1

631

values[0x1]

all_enables

biggest_size

238739

1

T33

12415

T34

34

T1

377

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2918002	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

462012

1

T35

8

T36

97

T37

364

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1143053	1			T35	18		T36	222		T37	818
values[0x0]	1093239	1			T35	3		T36	233		T37	911
values[0x1]	1143722	1			T35	14		T36	258		T37	865

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2261080	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1118934

1

T35

12

T36

213

T37

877

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52272	1			T35	1		T36	6		T37	39
valid_sources[0x01]	52957	1			T37	44		T50	27		T105	3
valid_sources[0x02]	53319	1			T36	27		T37	9		T50	13
valid_sources[0x03]	53296	1			T35	1		T36	20		T37	31
valid_sources[0x04]	52001	1			T35	2		T36	23		T37	45
valid_sources[0x05]	53580	1			T36	2		T37	32		T50	18
valid_sources[0x06]	51645	1			T36	26		T37	20		T50	25
valid_sources[0x07]	52542	1			T36	4		T37	24		T50	67
valid_sources[0x08]	52868	1			T35	1		T36	11		T37	52
valid_sources[0x09]	52919	1			T36	7		T37	40		T50	100
valid_sources[0x0a]	52768	1			T35	2		T36	20		T37	42
valid_sources[0x0b]	53012	1			T37	58		T50	17		T105	2
valid_sources[0x0c]	51560	1			T36	13		T37	33		T50	12
valid_sources[0x0d]	52472	1			T35	1		T36	16		T37	47
valid_sources[0x0e]	53914	1			T36	16		T37	52		T50	37
valid_sources[0x0f]	53887	1			T35	1		T36	17		T37	22
valid_sources[0x10]	52831	1			T36	12		T37	34		T50	38
valid_sources[0x11]	52987	1			T35	1		T36	18		T37	35
valid_sources[0x12]	53595	1			T36	4		T37	64		T50	25
valid_sources[0x13]	53463	1			T36	25		T37	46		T50	24
valid_sources[0x14]	53160	1			T36	18		T37	33		T50	42
valid_sources[0x15]	52900	1			T36	11		T37	48		T50	26
valid_sources[0x16]	52040	1			T35	1		T36	5		T37	44
valid_sources[0x17]	51655	1			T36	2		T37	64		T50	22
valid_sources[0x18]	52706	1			T35	1		T37	27		T50	17
valid_sources[0x19]	52726	1			T36	12		T37	84		T50	22
valid_sources[0x1a]	52600	1			T35	3		T36	12		T37	41
valid_sources[0x1b]	53324	1			T36	18		T37	65		T50	27
valid_sources[0x1c]	53702	1			T36	6		T37	16		T50	20
valid_sources[0x1d]	53047	1			T35	1		T36	11		T37	41
valid_sources[0x1e]	53073	1			T36	12		T37	66		T50	49
valid_sources[0x1f]	50759	1			T36	5		T37	24		T50	37
valid_sources[0x20]	52258	1			T36	5		T37	28		T50	21

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

48301

1

T35

4

T36

12

T37

27

values[0x0]

all_enables

biggest_size

365306

1

T36

71

T37

300

T50

202

values[0x1]

all_enables

biggest_size

48405

1

T35

4

T36

14

T37

37

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	3107743	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

505844

1

T35

8

T36

119

T37

340

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1235560	1			T35	42		T36	282		T37	822
values[0x0]	1141589	1			T35	5		T36	256		T37	824
values[0x1]	1236438	1			T35	38		T36	274		T37	879

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2385957	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1227630

1

T35

27

T36

264

T37

851

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	56755	1			T36	4		T37	21		T50	28
valid_sources[0x01]	56178	1			T35	1		T36	6		T37	68
valid_sources[0x02]	56821	1			T35	5		T36	2		T37	99
valid_sources[0x03]	56643	1			T36	5		T37	33		T50	51
valid_sources[0x04]	56301	1			T35	4		T36	7		T37	65
valid_sources[0x05]	56644	1			T35	2		T36	16		T37	29
valid_sources[0x06]	56655	1			T35	2		T36	34		T37	38
valid_sources[0x07]	56571	1			T36	22		T37	11		T50	19
valid_sources[0x08]	57165	1			T35	1		T36	11		T37	64
valid_sources[0x09]	55797	1			T35	1		T36	5		T37	53
valid_sources[0x0a]	55988	1			T35	6		T36	23		T37	33
valid_sources[0x0b]	56684	1			T36	1		T37	22		T50	28
valid_sources[0x0c]	56421	1			T35	1		T36	6		T37	22
valid_sources[0x0d]	56071	1			T36	5		T37	9		T50	2
valid_sources[0x0e]	57513	1			T37	34		T50	18		T257	5
valid_sources[0x0f]	56076	1			T35	2		T36	12		T37	23
valid_sources[0x10]	56416	1			T35	5		T36	4		T37	39
valid_sources[0x11]	55270	1			T35	3		T36	15		T37	37
valid_sources[0x12]	57878	1			T35	1		T36	5		T37	51
valid_sources[0x13]	56678	1			T36	29		T37	20		T50	16
valid_sources[0x14]	57336	1			T36	2		T37	31		T50	9
valid_sources[0x15]	56139	1			T35	1		T36	4		T37	20
valid_sources[0x16]	55765	1			T36	44		T37	66		T50	43
valid_sources[0x17]	56140	1			T36	16		T37	12		T50	6
valid_sources[0x18]	56053	1			T35	1		T36	3		T37	48
valid_sources[0x19]	56522	1			T36	6		T37	41		T50	47
valid_sources[0x1a]	56893	1			T36	5		T37	4		T50	44
valid_sources[0x1b]	56280	1			T35	1		T36	5		T37	59
valid_sources[0x1c]	57252	1			T36	12		T37	23		T50	32
valid_sources[0x1d]	56908	1			T35	1		T36	14		T37	52
valid_sources[0x1e]	57098	1			T35	1		T36	12		T37	21
valid_sources[0x1f]	55754	1			T36	16		T37	59		T50	10
valid_sources[0x20]	56711	1			T36	9		T37	26		T50	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

52711

1

T35

6

T36

10

T37

30

values[0x0]

all_enables

biggest_size

400184

1

T35

2

T36

93

T37

273

values[0x1]

all_enables

biggest_size

52949

1

T36

16

T37

37

T50

22

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2945561	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

465391

1

T35

5

T36

132

T37

391

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	1154761	1			T35	18		T36	272		T37	915
values[0x0]	1102519	1			T35	2		T36	282		T37	888
values[0x1]	1153672	1			T35	14		T36	309		T37	907

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	2281425	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

1129527

1

T35

17

T36

291

T37

906

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	52810	1			T36	15		T37	46		T50	20
valid_sources[0x01]	52515	1			T36	9		T37	38		T50	27
valid_sources[0x02]	53185	1			T36	16		T37	47		T50	23
valid_sources[0x03]	54335	1			T35	1		T36	6		T37	40
valid_sources[0x04]	53210	1			T36	11		T37	43		T50	25
valid_sources[0x05]	53169	1			T36	10		T37	32		T50	22
valid_sources[0x06]	52541	1			T36	16		T37	34		T50	41
valid_sources[0x07]	53082	1			T36	13		T37	38		T50	21
valid_sources[0x08]	54902	1			T35	2		T36	17		T37	35
valid_sources[0x09]	53517	1			T35	3		T36	12		T37	44
valid_sources[0x0a]	53555	1			T36	7		T37	53		T50	17
valid_sources[0x0b]	53182	1			T35	1		T36	11		T37	40
valid_sources[0x0c]	53182	1			T35	2		T36	20		T37	34
valid_sources[0x0d]	52804	1			T36	23		T37	38		T50	16
valid_sources[0x0e]	53842	1			T35	1		T36	2		T37	51
valid_sources[0x0f]	52729	1			T36	11		T37	40		T50	19
valid_sources[0x10]	53561	1			T36	18		T37	39		T50	25
valid_sources[0x11]	52215	1			T36	7		T37	43		T50	22
valid_sources[0x12]	53194	1			T36	16		T37	56		T50	25
valid_sources[0x13]	52928	1			T36	8		T37	40		T50	19
valid_sources[0x14]	53625	1			T35	1		T36	24		T37	51
valid_sources[0x15]	53252	1			T35	2		T36	14		T37	56
valid_sources[0x16]	52685	1			T35	1		T36	8		T37	49
valid_sources[0x17]	52514	1			T36	14		T37	41		T50	38
valid_sources[0x18]	53687	1			T35	1		T36	17		T37	48
valid_sources[0x19]	52293	1			T35	1		T36	19		T37	40
valid_sources[0x1a]	53987	1			T36	27		T37	54		T50	23
valid_sources[0x1b]	53443	1			T36	22		T37	36		T50	30
valid_sources[0x1c]	53463	1			T36	16		T37	38		T50	23
valid_sources[0x1d]	53653	1			T35	1		T36	11		T37	37
valid_sources[0x1e]	53357	1			T36	4		T37	56		T50	32
valid_sources[0x1f]	52877	1			T36	13		T37	45		T50	28
valid_sources[0x20]	53185	1			T36	11		T37	47		T50	19

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

49121

1

T35

3

T36

9

T37

37

values[0x0]

all_enables

biggest_size

367383

1

T35

1

T36

103

T37

315

values[0x1]

all_enables

biggest_size

48887

1

T35

1

T36

20

T37

39