Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T163,T12,T13
0	1	Covered	T163,T166,T301
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T163,T166,T301
1	Covered	T163,T12,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T163,T166,T301
1	Covered	T163,T12,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T166,T301
1	1	Covered	T163,T166,T301

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T163,T12,T13
1	0	Covered	T163,T166,T301
1	1	Covered	T163,T166,T301

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T163,T166,T301

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T163,T12,T13
0	Covered	T163,T166,T301

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T163,T12,T13
0	Covered	T163,T166,T301

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	782961264	764111684	0	0
CheckNGreaterZero_A	1930	1930	0	0
GntImpliesReady_A	782961264	5438	0	0
GntImpliesValid_A	782961264	5438	0	0
GrantKnown_A	782961264	764111684	0	0
IdxKnown_A	782961264	764111684	0	0
IndexIsCorrect_A	782961264	5438	0	0
NoReadyValidNoGrant_A	782961264	0	0	0
Priority_A	782961264	5438	0	0
ReadyAndValidImplyGrant_A	782961264	5438	0	0
ReqAndReadyImplyGrant_A	782961264	5438	0	0
ReqImpliesValid_A	782961264	5438	0	0
ValidKnown_A	782961264	764111684	0	0
gen_data_port_assertion.DataFlow_A	782961264	5438	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	764111684	0	0
T23	561038	560914	0	0
T24	183208	183106	0	0
T25	709258	709156	0	0
T26	473734	473516	0	0
T41	526636	526432	0	0
T47	589342	589332	0	0
T85	979552	979428	0	0
T91	113052	112942	0	0
T158	415426	415316	0	0
T181	734188	734072	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1930	1930	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T7	2	2	0	0
T55	2	2	0	0
T56	2	2	0	0
T57	2	2	0	0
T58	2	2	0	0
T59	2	2	0	0
T60	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	764111684	0	0
T23	561038	560914	0	0
T24	183208	183106	0	0
T25	709258	709156	0	0
T26	473734	473516	0	0
T41	526636	526432	0	0
T47	589342	589332	0	0
T85	979552	979428	0	0
T91	113052	112942	0	0
T158	415426	415316	0	0
T181	734188	734072	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	764111684	0	0
T23	561038	560914	0	0
T24	183208	183106	0	0
T25	709258	709156	0	0
T26	473734	473516	0	0
T41	526636	526432	0	0
T47	589342	589332	0	0
T85	979552	979428	0	0
T91	113052	112942	0	0
T158	415426	415316	0	0
T181	734188	734072	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	764111684	0	0
T23	561038	560914	0	0
T24	183208	183106	0	0
T25	709258	709156	0	0
T26	473734	473516	0	0
T41	526636	526432	0	0
T47	589342	589332	0	0
T85	979552	979428	0	0
T91	113052	112942	0	0
T158	415426	415316	0	0
T181	734188	734072	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	782961264	5438	0	0
T14	384426	0	0	0
T163	156972	1812	0	0
T166	0	1809	0	0
T286	445706	0	0	0
T301	0	1817	0	0
T303	1609302	0	0	0
T304	1084954	0	0	0
T305	1341528	0	0	0
T306	589518	0	0	0
T307	509680	0	0	0
T308	1013680	0	0	0
T309	523326	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T163,T12,T13
0	1	Covered	T163,T166,T301
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T163,T166,T301
1	Covered	T163,T12,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T163,T166,T301
1	Covered	T163,T12,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T166,T301
1	1	Covered	T163,T166,T301

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T163,T12,T13
1	0	Covered	T163,T166,T301
1	1	Covered	T163,T166,T301

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T163,T166,T301

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T163,T12,T13
0	Covered	T163,T166,T301

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T163,T12,T13
0	Covered	T163,T166,T301

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391480632	382055842	0	0
CheckNGreaterZero_A	965	965	0	0
GntImpliesReady_A	391480632	4406	0	0
GntImpliesValid_A	391480632	4406	0	0
GrantKnown_A	391480632	382055842	0	0
IdxKnown_A	391480632	382055842	0	0
IndexIsCorrect_A	391480632	4406	0	0
NoReadyValidNoGrant_A	391480632	0	0	0
Priority_A	391480632	4406	0	0
ReadyAndValidImplyGrant_A	391480632	4406	0	0
ReqAndReadyImplyGrant_A	391480632	4406	0	0
ReqImpliesValid_A	391480632	4406	0	0
ValidKnown_A	391480632	382055842	0	0
gen_data_port_assertion.DataFlow_A	391480632	4406	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	4406	0	0
T14	192213	0	0	0
T163	78486	1468	0	0
T166	0	1465	0	0
T286	222853	0	0	0
T301	0	1473	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T163,T12,T13
0	1	Covered	T163,T166,T301
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T163,T166,T301
1	Covered	T163,T12,T13

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T163,T166,T301
1	Covered	T163,T12,T13

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T163,T166,T301
1	1	Covered	T163,T166,T301

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T163,T12,T13
1	0	Covered	T163,T166,T301
1	1	Covered	T163,T166,T301

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T163,T166,T301

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T163,T12,T13
0	Covered	T163,T166,T301

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T163,T12,T13
0	Covered	T163,T166,T301

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	391480632	382055842	0	0
CheckNGreaterZero_A	965	965	0	0
GntImpliesReady_A	391480632	1032	0	0
GntImpliesValid_A	391480632	1032	0	0
GrantKnown_A	391480632	382055842	0	0
IdxKnown_A	391480632	382055842	0	0
IndexIsCorrect_A	391480632	1032	0	0
NoReadyValidNoGrant_A	391480632	0	0	0
Priority_A	391480632	1032	0	0
ReadyAndValidImplyGrant_A	391480632	1032	0	0
ReqAndReadyImplyGrant_A	391480632	1032	0	0
ReqImpliesValid_A	391480632	1032	0	0
ValidKnown_A	391480632	382055842	0	0
gen_data_port_assertion.DataFlow_A	391480632	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	965	965	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T7	1	1	0	0
T55	1	1	0	0
T56	1	1	0	0
T57	1	1	0	0
T58	1	1	0	0
T59	1	1	0	0
T60	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	382055842	0	0
T23	280519	280457	0	0
T24	91604	91553	0	0
T25	354629	354578	0	0
T26	236867	236758	0	0
T41	263318	263216	0	0
T47	294671	294666	0	0
T85	489776	489714	0	0
T91	56526	56471	0	0
T158	207713	207658	0	0
T181	367094	367036	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	391480632	1032	0	0
T14	192213	0	0	0
T163	78486	344	0	0
T166	0	344	0	0
T286	222853	0	0	0
T301	0	344	0	0
T303	804651	0	0	0
T304	542477	0	0	0
T305	670764	0	0	0
T306	294759	0	0	0
T307	254840	0	0	0
T308	506840	0	0	0
T309	261663	0	0	0