Unified Coverage Report :: Module :: edn

Module : edn

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.59			99.59

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_edn_0.1/rtl/edn.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_edn0	99.50			99.50
tb.dut.top_earlgrey.u_edn1	99.58			99.58

---

Module Instance : tb.dut.top_earlgrey.u_edn0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.50			99.50

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.50			99.50

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_edn1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58			99.58

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.58			99.58

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : edn

	Total	Covered	Percent
Totals	78	74	94.87
Total Bits	1206	1201	99.59
Total Bits 0->1	603	602	99.83
Total Bits 1->0	603	599	99.34

Ports	78	74	94.87
Port Bits	1206	1201	99.59
Port Bits 0->1	603	602	99.83
Port Bits 1->0	603	599	99.34

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
rst_ni	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
tl_i.d_ready	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:16]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_valid	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_o.a_ready	Yes	Yes	T35,T36,T50	Yes	T35,T36,T37	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_sink	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
edn_i[0].edn_req	Yes	Yes	T146,T150,T183	Yes	T146,T150,T183	INPUT
edn_i[1].edn_req	Yes	Yes	T24,T25,T85	Yes	T24,T25,T85	INPUT
edn_i[2].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[3].edn_req	Yes	Yes	T403,T197,T198	Yes	T403,T197,T198	INPUT
edn_i[4].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[5].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[6].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[7].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T146,T150,T183	Yes	T146,T150,T183	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T109,T110,T267	Yes	T67,T131,T109	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T146,T150,T183	Yes	T146,T150,T183	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T24,T25,T85	Yes	T24,T25,T85	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T67,T131,T132	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T24,T25,T85	Yes	T24,T25,T85	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T25,T26,T41	Yes	T25,T85,T26	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T86,T87,T88	Yes	T67,T89,T90	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T403,T197,T198	Yes	T403,T197,T198	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T197,T198,T404	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T403,T197,T198	Yes	T403,T197,T198	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T85,T41,T47	Yes	T23,T24,T85	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T89,T647,T648	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T267,T649,T650	Yes	T267,T197,T198	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T109,T110,T267	Yes	T67,T131,T109	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T85,T42,T38	Yes	T24,T85,T47	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T109,T110,T267	Yes	T79,T109,T268	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T26,T41,T42	Yes	T23,T24,T25	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T109,T110,T651	Yes	T79,T67,T131	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
csrng_cmd_i.csrng_rsp_sts	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T267,T652,T653	Yes	T267,T652,T653	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T51,T53	Yes	T33,T51,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T51,T53,T54	Yes	T51,T53,T54	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T51,T53,T54	Yes	T51,T53,T54	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T33,T51,T70	Yes	T33,T51,T70	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T51,T276,T53	Yes	T51,T276,T53	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T51,T276,T53	Yes	T51,T276,T53	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T51,T53	Yes	T33,T51,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T33,T51,T70	Yes	T33,T51,T70	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T202,T71,T111	Yes	T202,T71,T111	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T202,T71,T204	Yes	T202,T71,T204	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn0

	Total	Covered	Percent
Totals	78	73	93.59
Total Bits	1204	1198	99.50
Total Bits 0->1	602	601	99.83
Total Bits 1->0	602	597	99.17

Ports	78	73	93.59
Port Bits	1204	1198	99.50
Port Bits 0->1	602	601	99.83
Port Bits 1->0	602	597	99.17

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
rst_ni	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
tl_i.d_ready	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:16]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_valid	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_o.a_ready	Yes	Yes	T35,T36,T50	Yes	T35,T36,T37	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_sink	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
edn_i[0].edn_req	Yes	Yes	T146,T150,T183	Yes	T146,T150,T183	INPUT
edn_i[1].edn_req	Yes	Yes	T24,T25,T85	Yes	T24,T25,T85	INPUT
edn_i[2].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[3].edn_req	Yes	Yes	T403,T197,T198	Yes	T403,T197,T198	INPUT
edn_i[4].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[5].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[6].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_i[7].edn_req	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
edn_o[0].edn_bus[31:0]	Yes	Yes	T146,T150,T183	Yes	T146,T150,T183	OUTPUT
edn_o[0].edn_fips	No	No		Yes	T186,T197,T198	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T146,T150,T183	Yes	T146,T150,T183	OUTPUT
edn_o[1].edn_bus[31:0]	Yes	Yes	T24,T25,T85	Yes	T24,T25,T85	OUTPUT
edn_o[1].edn_fips	No	No		Yes	T67,T131,T132	OUTPUT
edn_o[1].edn_ack	Yes	Yes	T24,T25,T85	Yes	T24,T25,T85	OUTPUT
edn_o[2].edn_bus[31:0]	Yes	Yes	T25,T26,T41	Yes	T25,T85,T26	OUTPUT
edn_o[2].edn_fips	Yes	Yes	T86,T87,T88	Yes	T67,T89,T90	OUTPUT
edn_o[2].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[3].edn_bus[31:0]	Yes	Yes	T403,T197,T198	Yes	T403,T197,T198	OUTPUT
edn_o[3].edn_fips	No	No		Yes	T197,T198,T404	OUTPUT
edn_o[3].edn_ack	Yes	Yes	T403,T197,T198	Yes	T403,T197,T198	OUTPUT
edn_o[4].edn_bus[31:0]	Yes	Yes	T85,T41,T47	Yes	T23,T24,T85	OUTPUT
edn_o[4].edn_fips	No	No		Yes	T89,T647,T648	OUTPUT
edn_o[4].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[5].edn_bus[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[5].edn_fips	Yes	Yes	T267,T649,T650	Yes	T267,T197,T198	OUTPUT
edn_o[5].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[6].edn_bus[31:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[6].edn_fips	Yes	Yes	T109,T110,T267	Yes	T67,T131,T109	OUTPUT
edn_o[6].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
edn_o[7].edn_bus[31:0]	Yes	Yes	T85,T42,T38	Yes	T24,T85,T47	OUTPUT
edn_o[7].edn_fips	Yes	Yes	T109,T110,T267	Yes	T79,T109,T268	OUTPUT
edn_o[7].edn_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
csrng_cmd_o.genbits_ready	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T26,T41,T42	Yes	T23,T24,T25	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
csrng_cmd_i.genbits_fips	Yes	Yes	T109,T110,T651	Yes	T79,T67,T131	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
csrng_cmd_i.csrng_rsp_sts	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T23,T24,T25	Yes	T23,T24,T25	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T267,T652,T653	Yes	T267,T652,T653	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T51,T53	Yes	T33,T51,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T51,T53,T54	Yes	T51,T53,T54	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T51,T53,T54	Yes	T51,T53,T54	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T33,T51,T654	Yes	T33,T51,T654	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T51,T276,T53	Yes	T51,T276,T53	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T51,T276,T53	Yes	T51,T276,T53	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T51,T53	Yes	T33,T51,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T33,T51,T654	Yes	T33,T51,T654	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T202,T71,T111	Yes	T202,T71,T111	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T202,T71,T204	Yes	T202,T71,T204	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_edn1

	Total	Covered	Percent
Totals	50	48	96.00
Total Bits	710	707	99.58
Total Bits 0->1	355	354	99.72
Total Bits 1->0	355	353	99.44

Ports	50	48	96.00
Port Bits	710	707	99.58
Port Bits 0->1	355	354	99.72
Port Bits 1->0	355	353	99.44

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
rst_ni	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
tl_i.d_ready	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20:19]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T35,*T36,*T37	Yes	T35,T36,T37	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_i.a_valid	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	INPUT
tl_o.a_ready	Yes	Yes	T35,T36,T50	Yes	T35,T36,T37	OUTPUT
tl_o.d_error	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_sink	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T35,*T36,*T37	Yes	T36,T37,T50	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T35,T36,T37	Yes	T35,T36,T37	OUTPUT
edn_i[0].edn_req	Yes	Yes	T67,T131,T109	Yes	T67,T131,T109	INPUT
edn_i[1].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[2].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[3].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[4].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[5].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[6].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_i[7].edn_req[0:0]	Excluded	Excluded		Excluded		INPUT	[UNR] Tied off and unused.
edn_o[0].edn_bus[31:0]	Yes	Yes	T67,T131,T109	Yes	T67,T131,T109	OUTPUT
edn_o[0].edn_fips	Yes	Yes	T109,T110,T267	Yes	T67,T131,T109	OUTPUT
edn_o[0].edn_ack	Yes	Yes	T67,T131,T109	Yes	T67,T131,T109	OUTPUT
edn_o[1].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[1].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[2].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[3].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[4].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[5].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[6].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_bus[31:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_fips[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
edn_o[7].edn_ack[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tied off and unused.
csrng_cmd_o.genbits_ready	Yes	Yes	T79,T67,T131	Yes	T79,T67,T131	OUTPUT
csrng_cmd_o.csrng_req_bus[31:0]	Yes	Yes	T67,T131,T109	Yes	T79,T67,T131	OUTPUT
csrng_cmd_o.csrng_req_valid	Yes	Yes	T79,T67,T131	Yes	T79,T67,T131	OUTPUT
csrng_cmd_i.genbits_bus[127:0]	Yes	Yes	T67,T131,T109	Yes	T67,T131,T109	INPUT
csrng_cmd_i.genbits_fips	No	No		Yes	T109,T110,T651	INPUT
csrng_cmd_i.genbits_valid	Yes	Yes	T79,T67,T131	Yes	T79,T67,T131	INPUT
csrng_cmd_i.csrng_rsp_sts	No	No		No		INPUT
csrng_cmd_i.csrng_rsp_ack	Yes	Yes	T79,T67,T131	Yes	T79,T67,T131	INPUT
csrng_cmd_i.csrng_req_ready	Yes	Yes	T267,T653,T649	Yes	T267,T653,T649	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T33,T51,T53	Yes	T33,T51,T53	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T51,T53,T137	Yes	T53,T137,T138	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T53,T137,T138	Yes	T51,T53,T137	INPUT
alert_rx_i[1].ack_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	INPUT
alert_rx_i[1].ack_p	Yes	Yes	T33,T51,T70	Yes	T33,T51,T70	INPUT
alert_rx_i[1].ping_n	Yes	Yes	T51,T53,T137	Yes	T53,T137,T138	INPUT
alert_rx_i[1].ping_p	Yes	Yes	T53,T137,T138	Yes	T51,T53,T137	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T33,T51,T53	Yes	T33,T51,T53	OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T33,T34,T1	Yes	T33,T34,T1	OUTPUT
alert_tx_o[1].alert_p	Yes	Yes	T33,T51,T70	Yes	T33,T51,T70	OUTPUT
intr_edn_cmd_req_done_o	Yes	Yes	T202,T71,T111	Yes	T202,T71,T111	OUTPUT
intr_edn_fatal_err_o	Yes	Yes	T202,T71,T204	Yes	T202,T71,T204	OUTPUT

*Tests covering at least one bit in the range