Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.08	100.00	92.31			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.22	100.00	96.88			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.88	90.91	84.62			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.38	94.00	87.50			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	93.79	93.33	81.82			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T169,T33,T16

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T16,T12
1	1	Covered	T33,T16,T12

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T16,T12
1	-	Covered	T16,T17,T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T16,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T16,T12
1	1	Covered	T33,T16,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T16,T12
0	0	1	Covered	T33,T16,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T16,T12
0	0	1	Covered	T33,T16,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	131992	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	329	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	131992	0	0
T12	0	381	0	0
T13	0	438	0	0
T16	26625	752	0	0
T17	0	624	0	0
T18	0	906	0	0
T33	631007	1706	0	0
T52	39294	0	0	0
T126	0	895	0	0
T127	0	4553	0	0
T128	0	6009	0	0
T152	26490	0	0	0
T313	0	435	0	0
T360	40529	0	0	0
T361	20984	0	0	0
T362	53986	0	0	0
T363	38658	0	0	0
T364	53664	0	0	0
T365	92814	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	329	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	26625	2	0	0
T17	0	2	0	0
T18	0	2	0	0
T33	631007	4	0	0
T52	39294	0	0	0
T126	0	2	0	0
T127	0	11	0	0
T128	0	14	0	0
T152	26490	0	0	0
T313	0	1	0	0
T360	40529	0	0	0
T361	20984	0	0	0
T362	53986	0	0	0
T363	38658	0	0	0
T364	53664	0	0	0
T365	92814	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T259,T33,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T19,T12
1	1	Covered	T33,T19,T12

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T19,T12
1	-	Covered	T19

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T19,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T19,T12
1	1	Covered	T33,T19,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T19,T12
0	0	1	Covered	T33,T19,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T19,T12
0	0	1	Covered	T33,T19,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	129793	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	322	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	129793	0	0
T12	0	385	0	0
T13	0	438	0	0
T19	32082	1020	0	0
T32	29582	0	0	0
T33	631007	4799	0	0
T120	44545	0	0	0
T126	0	855	0	0
T127	0	3724	0	0
T128	0	5145	0	0
T313	0	420	0	0
T353	0	8241	0	0
T354	0	242	0	0
T366	58039	0	0	0
T367	32112	0	0	0
T368	266635	0	0	0
T369	24839	0	0	0
T370	54666	0	0	0
T371	99569	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	322	0	0
T12	0	1	0	0
T13	0	1	0	0
T19	32082	2	0	0
T32	29582	0	0	0
T33	631007	11	0	0
T120	44545	0	0	0
T126	0	2	0	0
T127	0	9	0	0
T128	0	12	0	0
T313	0	1	0	0
T353	0	20	0	0
T354	0	1	0	0
T366	58039	0	0	0
T367	32112	0	0	0
T368	266635	0	0	0
T369	24839	0	0	0
T370	54666	0	0	0
T371	99569	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T372,T33,T115

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T14,T12
1	1	Covered	T33,T14,T12

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T14,T12
1	-	Covered	T14

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T14,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T14,T12
1	1	Covered	T33,T14,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T14,T12
0	0	1	Covered	T33,T14,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T14,T12
0	0	1	Covered	T33,T14,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	148258	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	367	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	148258	0	0
T12	0	465	0	0
T13	0	387	0	0
T14	48771	989	0	0
T33	631007	7913	0	0
T126	0	789	0	0
T127	0	1735	0	0
T128	0	5590	0	0
T153	14745	0	0	0
T174	52477	0	0	0
T286	54884	0	0	0
T309	63854	0	0	0
T313	0	398	0	0
T352	26258	0	0	0
T353	0	5466	0	0
T354	0	5032	0	0
T373	271416	0	0	0
T374	54461	0	0	0
T375	38737	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	367	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	48771	2	0	0
T33	631007	18	0	0
T126	0	2	0	0
T127	0	4	0	0
T128	0	13	0	0
T153	14745	0	0	0
T174	52477	0	0	0
T286	54884	0	0	0
T309	63854	0	0	0
T313	0	1	0	0
T352	26258	0	0	0
T353	0	13	0	0
T354	0	13	0	0
T373	271416	0	0	0
T374	54461	0	0	0
T375	38737	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T37,T376,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T12,T13
1	-	Covered	T20

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	119323	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	298	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	119323	0	0
T12	431394	373	0	0
T13	432023	387	0	0
T20	0	808	0	0
T33	631007	4985	0	0
T126	0	744	0	0
T127	0	1307	0	0
T128	0	3746	0	0
T313	0	447	0	0
T353	0	2815	0	0
T354	0	1847	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	298	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T20	0	2	0	0
T33	631007	11	0	0
T126	0	2	0	0
T127	0	3	0	0
T128	0	9	0	0
T313	0	1	0	0
T353	0	7	0	0
T354	0	5	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T359,T384

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	127242	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	317	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	127242	0	0
T12	431394	402	0	0
T13	432023	427	0	0
T33	631007	1794	0	0
T126	0	877	0	0
T127	0	4572	0	0
T128	0	4658	0	0
T313	0	425	0	0
T353	0	7088	0	0
T354	0	2552	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	343	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	317	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	4	0	0
T126	0	2	0	0
T127	0	11	0	0
T128	0	11	0	0
T313	0	1	0	0
T353	0	17	0	0
T354	0	7	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Covered	Percent
Conditions	13	12	92.31
Logical	13	12	92.31
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T259,T33,T8

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T8,T9
1	1	Covered	T33,T8,T9

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T8,T9
1	-	Covered	T8,T9,T10

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T8,T9
1	1	Covered	T33,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T8,T9
0	0	1	Covered	T33,T8,T9
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T8,T9
0	0	1	Covered	T33,T8,T9
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	140463	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	353	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	140463	0	0
T8	135887	878	0	0
T9	140412	758	0	0
T10	0	744	0	0
T15	0	1397	0	0
T21	0	1284	0	0
T22	0	1513	0	0
T33	631007	5292	0	0
T73	0	779	0	0
T74	0	735	0	0
T75	0	744	0	0
T76	39418	0	0	0
T77	167688	0	0	0
T78	42400	0	0	0
T79	84523	0	0	0
T80	42874	0	0	0
T81	56549	0	0	0
T82	66663	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	353	0	0
T8	135887	2	0	0
T9	140412	2	0	0
T10	0	2	0	0
T15	0	4	0	0
T21	0	4	0	0
T22	0	4	0	0
T33	631007	12	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	39418	0	0	0
T77	167688	0	0	0
T78	42400	0	0	0
T79	84523	0	0	0
T80	42874	0	0	0
T81	56549	0	0	0
T82	66663	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	144898	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	356	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	144898	0	0
T12	431394	433	0	0
T13	432023	374	0	0
T33	631007	7815	0	0
T126	0	874	0	0
T127	0	3029	0	0
T128	0	4440	0	0
T313	0	434	0	0
T353	0	6361	0	0
T354	0	5939	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	337	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	356	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	18	0	0
T126	0	2	0	0
T127	0	7	0	0
T128	0	10	0	0
T313	0	1	0	0
T353	0	15	0	0
T354	0	15	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	20	90.91
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	0	0.00
CONT_ASSIGN	145	1	0	0.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	0	1
145	0	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Covered	Percent
Conditions	13	11	84.62
Logical	13	11	84.62
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T386,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       112
 EXPRESSION (src_wd_i & BitMask)
             ----1---   ---2---

-1-	-2-	Status	Tests
0	-	Covered	T33,T12,T13
1	-	Not Covered

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	129137	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	322	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	129137	0	0
T12	431394	372	0	0
T13	432023	471	0	0
T33	631007	5721	0	0
T126	0	888	0	0
T127	0	3009	0	0
T128	0	5090	0	0
T313	0	437	0	0
T353	0	2532	0	0
T354	0	2667	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	349	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	322	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	13	0	0
T126	0	2	0	0
T127	0	7	0	0
T128	0	12	0	0
T313	0	1	0	0
T353	0	6	0	0
T354	0	7	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T259,T387,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T16,T12
1	1	Covered	T33,T16,T12

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T16,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T16,T12
1	1	Covered	T33,T16,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T16,T12
0	0	1	Covered	T33,T16,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T16,T12
0	0	1	Covered	T33,T16,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	136587	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	340	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	136587	0	0
T12	0	396	0	0
T13	0	371	0	0
T16	26625	378	0	0
T17	0	250	0	0
T18	0	412	0	0
T33	631007	4004	0	0
T52	39294	0	0	0
T126	0	804	0	0
T128	0	4441	0	0
T152	26490	0	0	0
T313	0	399	0	0
T353	0	6556	0	0
T360	40529	0	0	0
T361	20984	0	0	0
T362	53986	0	0	0
T363	38658	0	0	0
T364	53664	0	0	0
T365	92814	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	340	0	0
T12	0	1	0	0
T13	0	1	0	0
T16	26625	1	0	0
T17	0	1	0	0
T18	0	1	0	0
T33	631007	9	0	0
T52	39294	0	0	0
T126	0	2	0	0
T128	0	10	0	0
T152	26490	0	0	0
T313	0	1	0	0
T353	0	16	0	0
T360	40529	0	0	0
T361	20984	0	0	0
T362	53986	0	0	0
T363	38658	0	0	0
T364	53664	0	0	0
T365	92814	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T384,T19

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T19,T12
1	1	Covered	T33,T19,T12

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T19,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T19,T12
1	1	Covered	T33,T19,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T19,T12
0	0	1	Covered	T33,T19,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T19,T12
0	0	1	Covered	T33,T19,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	130378	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	322	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	130378	0	0
T12	0	464	0	0
T13	0	395	0	0
T19	32082	480	0	0
T32	29582	0	0	0
T33	631007	1771	0	0
T120	44545	0	0	0
T126	0	865	0	0
T127	0	1254	0	0
T128	0	6505	0	0
T313	0	434	0	0
T353	0	4223	0	0
T354	0	2269	0	0
T366	58039	0	0	0
T367	32112	0	0	0
T368	266635	0	0	0
T369	24839	0	0	0
T370	54666	0	0	0
T371	99569	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	322	0	0
T12	0	1	0	0
T13	0	1	0	0
T19	32082	1	0	0
T32	29582	0	0	0
T33	631007	4	0	0
T120	44545	0	0	0
T126	0	2	0	0
T127	0	3	0	0
T128	0	15	0	0
T313	0	1	0	0
T353	0	10	0	0
T354	0	6	0	0
T366	58039	0	0	0
T367	32112	0	0	0
T368	266635	0	0	0
T369	24839	0	0	0
T370	54666	0	0	0
T371	99569	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T388,T14

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T14,T12
1	1	Covered	T33,T14,T12

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T14,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T14,T12
1	1	Covered	T33,T14,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T14,T12
0	0	1	Covered	T33,T14,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T14,T12
0	0	1	Covered	T33,T14,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	127658	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	318	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	127658	0	0
T12	0	367	0	0
T13	0	380	0	0
T14	48771	450	0	0
T33	631007	4842	0	0
T126	0	868	0	0
T127	0	2145	0	0
T128	0	8481	0	0
T153	14745	0	0	0
T174	52477	0	0	0
T286	54884	0	0	0
T309	63854	0	0	0
T313	0	404	0	0
T352	26258	0	0	0
T353	0	2486	0	0
T354	0	2156	0	0
T373	271416	0	0	0
T374	54461	0	0	0
T375	38737	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	318	0	0
T12	0	1	0	0
T13	0	1	0	0
T14	48771	1	0	0
T33	631007	11	0	0
T126	0	2	0	0
T127	0	5	0	0
T128	0	20	0	0
T153	14745	0	0	0
T174	52477	0	0	0
T286	54884	0	0	0
T309	63854	0	0	0
T313	0	1	0	0
T352	26258	0	0	0
T353	0	6	0	0
T354	0	6	0	0
T373	271416	0	0	0
T374	54461	0	0	0
T375	38737	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T389,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	119595	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	299	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	119595	0	0
T12	431394	364	0	0
T13	432023	373	0	0
T20	0	265	0	0
T33	631007	7280	0	0
T126	0	778	0	0
T127	0	3039	0	0
T128	0	3034	0	0
T313	0	448	0	0
T353	0	3569	0	0
T354	0	4285	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	299	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T20	0	1	0	0
T33	631007	17	0	0
T126	0	2	0	0
T127	0	7	0	0
T128	0	7	0	0
T313	0	1	0	0
T353	0	9	0	0
T354	0	11	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T390,T391

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	132531	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	328	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	132531	0	0
T12	431394	466	0	0
T13	432023	381	0	0
T33	631007	3147	0	0
T126	0	882	0	0
T127	0	2612	0	0
T128	0	6542	0	0
T313	0	408	0	0
T353	0	2215	0	0
T354	0	4382	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	346	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	328	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	7	0	0
T126	0	2	0	0
T127	0	6	0	0
T128	0	15	0	0
T313	0	1	0	0
T353	0	5	0	0
T354	0	11	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T259,T258,T33

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T8,T9
1	1	Covered	T33,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T8,T9
1	1	Covered	T33,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T8,T9
0	0	1	Covered	T33,T8,T9
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T8,T9
0	0	1	Covered	T33,T8,T9
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	137832	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	346	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	137832	0	0
T8	135887	384	0	0
T9	140412	263	0	0
T10	0	250	0	0
T15	0	648	0	0
T21	0	535	0	0
T22	0	887	0	0
T33	631007	4484	0	0
T73	0	285	0	0
T74	0	361	0	0
T75	0	250	0	0
T76	39418	0	0	0
T77	167688	0	0	0
T78	42400	0	0	0
T79	84523	0	0	0
T80	42874	0	0	0
T81	56549	0	0	0
T82	66663	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	346	0	0
T8	135887	1	0	0
T9	140412	1	0	0
T10	0	1	0	0
T15	0	2	0	0
T21	0	2	0	0
T22	0	2	0	0
T33	631007	10	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	39418	0	0	0
T77	167688	0	0	0
T78	42400	0	0	0
T79	84523	0	0	0
T80	42874	0	0	0
T81	56549	0	0	0
T82	66663	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T389,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	127907	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	320	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	127907	0	0
T12	431394	400	0	0
T13	432023	397	0	0
T33	631007	6019	0	0
T126	0	771	0	0
T127	0	731	0	0
T128	0	8057	0	0
T313	0	368	0	0
T353	0	5796	0	0
T354	0	1321	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	277	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	320	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	14	0	0
T126	0	2	0	0
T127	0	2	0	0
T128	0	19	0	0
T313	0	1	0	0
T353	0	14	0	0
T354	0	4	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T359,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	146490	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	365	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	146490	0	0
T12	431394	433	0	0
T13	432023	370	0	0
T33	631007	5199	0	0
T126	0	848	0	0
T127	0	829	0	0
T128	0	5080	0	0
T313	0	383	0	0
T353	0	8304	0	0
T354	0	3451	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	267	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	365	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	12	0	0
T126	0	2	0	0
T127	0	2	0	0
T128	0	12	0	0
T313	0	1	0	0
T353	0	20	0	0
T354	0	9	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0