Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.27	99.82	97.24			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T359,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	130953	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	326	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	130953	0	0
T12	431394	384	0	0
T13	432023	443	0	0
T33	631007	4942	0	0
T126	0	779	0	0
T127	0	3358	0	0
T128	0	6904	0	0
T313	0	418	0	0
T353	0	5496	0	0
T354	0	3809	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	309	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	326	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	11	0	0
T126	0	2	0	0
T127	0	8	0	0
T128	0	16	0	0
T313	0	1	0	0
T353	0	13	0	0
T354	0	10	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T11,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T11,T12
1	1	Covered	T33,T11,T12

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T11,T12

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T11,T12
1	1	Covered	T33,T11,T12

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T11,T12
0	0	1	Covered	T33,T11,T12
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T11,T12
0	0	1	Covered	T33,T11,T12
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	140976	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	347	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	140976	0	0
T11	38507	261	0	0
T12	0	466	0	0
T13	0	456	0	0
T33	631007	2250	0	0
T126	0	865	0	0
T127	0	3800	0	0
T128	0	6604	0	0
T203	63428	0	0	0
T313	0	462	0	0
T392	0	273	0	0
T393	0	353	0	0
T394	115674	0	0	0
T395	209381	0	0	0
T396	42069	0	0	0
T397	23711	0	0	0
T398	117326	0	0	0
T399	242362	0	0	0
T400	21938	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	347	0	0
T11	38507	1	0	0
T12	0	1	0	0
T13	0	1	0	0
T33	631007	5	0	0
T126	0	2	0	0
T127	0	9	0	0
T128	0	15	0	0
T203	63428	0	0	0
T313	0	1	0	0
T353	0	5	0	0
T392	0	1	0	0
T394	115674	0	0	0
T395	209381	0	0	0
T396	42069	0	0	0
T397	23711	0	0	0
T398	117326	0	0	0
T399	242362	0	0	0
T400	21938	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T388,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	115819	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	289	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	115819	0	0
T12	431394	443	0	0
T13	432023	450	0	0
T33	631007	3110	0	0
T126	0	886	0	0
T127	0	4185	0	0
T128	0	1243	0	0
T313	0	475	0	0
T353	0	3663	0	0
T354	0	7106	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	281	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	289	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	7	0	0
T126	0	2	0	0
T127	0	10	0	0
T128	0	3	0	0
T313	0	1	0	0
T353	0	9	0	0
T354	0	18	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T259,T33,T359

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	121547	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	305	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	121547	0	0
T12	431394	419	0	0
T13	432023	363	0	0
T33	631007	4414	0	0
T126	0	812	0	0
T127	0	1676	0	0
T128	0	2558	0	0
T313	0	398	0	0
T353	0	1741	0	0
T354	0	3998	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	249	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	305	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	10	0	0
T126	0	2	0	0
T127	0	4	0	0
T128	0	6	0	0
T313	0	1	0	0
T353	0	4	0	0
T354	0	10	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T259,T33,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	130413	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	324	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	130413	0	0
T12	431394	394	0	0
T13	432023	440	0	0
T33	631007	3638	0	0
T126	0	900	0	0
T127	0	2260	0	0
T128	0	5300	0	0
T313	0	433	0	0
T353	0	3285	0	0
T354	0	1701	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	291	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	324	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	8	0	0
T126	0	2	0	0
T127	0	5	0	0
T128	0	12	0	0
T313	0	1	0	0
T353	0	8	0	0
T354	0	5	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	135439	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	340	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	135439	0	0
T12	431394	370	0	0
T13	432023	388	0	0
T33	631007	5216	0	0
T126	0	834	0	0
T127	0	3340	0	0
T128	0	2190	0	0
T313	0	476	0	0
T353	0	3652	0	0
T354	0	3857	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	315	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	340	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	12	0	0
T126	0	2	0	0
T127	0	8	0	0
T128	0	5	0	0
T313	0	1	0	0
T353	0	9	0	0
T354	0	10	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	143930	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	356	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	143930	0	0
T12	431394	432	0	0
T13	432023	441	0	0
T33	631007	5747	0	0
T126	0	898	0	0
T127	0	3710	0	0
T128	0	6583	0	0
T313	0	384	0	0
T353	0	3597	0	0
T354	0	2742	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	253	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	356	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	13	0	0
T126	0	2	0	0
T127	0	9	0	0
T128	0	15	0	0
T313	0	1	0	0
T353	0	9	0	0
T354	0	7	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T387,T33,T12

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Unreachable
1	0	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T12,T13
1	1	Covered	T33,T12,T13

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T12,T13
0	0	1	Covered	T33,T12,T13
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	131710	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	327	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	131710	0	0
T12	431394	459	0	0
T13	432023	380	0	0
T33	631007	2367	0	0
T126	0	802	0	0
T127	0	3794	0	0
T128	0	3778	0	0
T313	0	427	0	0
T353	0	3199	0	0
T354	0	3781	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	348	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	327	0	0
T12	431394	1	0	0
T13	432023	1	0	0
T33	631007	5	0	0
T126	0	2	0	0
T127	0	9	0	0
T128	0	9	0	0
T313	0	1	0	0
T353	0	8	0	0
T354	0	10	0	0
T377	19436	0	0	0
T378	45762	0	0	0
T379	29293	0	0	0
T380	268676	0	0	0
T381	50801	0	0	0
T382	28921	0	0	0
T383	21656	0	0	0
T385	0	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T37
0	1	Unreachable
1	0	Covered	T33,T359,T115

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T37
1	0	Covered	T33,T8,T9
1	1	Covered	T33,T8,T9

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T34,T1
0	1	Covered	T8,T9,T10
1	0	Covered	T33,T8,T9

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T33,T8,T9
1	1	Covered	T33,T8,T9

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T33,T34,T1
1	0	Not Covered
1	1	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T8,T9
0	0	1	Covered	T33,T8,T9
0	0	0	Covered	T33,T34,T1

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T33,T34,T1
0	1	-	Covered	T33,T8,T9
0	0	1	Covered	T33,T8,T9
0	0	0	Covered	T33,T34,T1

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	121002806	190872	0	0
DstReqKnown_A	1567889	1359995	0	0
SrcAckBusyChk_A	121002806	393	0	0
SrcBusyKnown_A	121002806	120203466	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	190872	0	0
T8	135887	921	0	0
T9	140412	720	0	0
T10	0	781	0	0
T15	0	1366	0	0
T16	0	1050	0	0
T21	0	1279	0	0
T33	631007	5330	0	0
T73	0	768	0	0
T74	0	782	0	0
T75	0	779	0	0
T76	39418	0	0	0
T77	167688	0	0	0
T78	42400	0	0	0
T79	84523	0	0	0
T80	42874	0	0	0
T81	56549	0	0	0
T82	66663	0	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1567889	1359995	0	0
T1	292	69	0	0
T2	342	119	0	0
T3	366	145	0	0
T7	378	153	0	0
T33	5559	5333	0	0
T34	1447	1000	0	0
T55	309	85	0	0
T56	301	77	0	0
T57	330	107	0	0
T58	305	79	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	393	0	0
T8	135887	2	0	0
T9	140412	2	0	0
T10	0	2	0	0
T15	0	4	0	0
T16	0	3	0	0
T21	0	4	0	0
T33	631007	10	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	39418	0	0	0
T77	167688	0	0	0
T78	42400	0	0	0
T79	84523	0	0	0
T80	42874	0	0	0
T81	56549	0	0	0
T82	66663	0	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121002806	120203466	0	0
T1	10713	9225	0	0
T2	9918	9097	0	0
T3	10053	9385	0	0
T7	9760	9087	0	0
T33	631007	630296	0	0
T34	46705	45269	0	0
T55	10554	9312	0	0
T56	10916	9486	0	0
T57	10313	9253	0	0
T58	10518	9130	0	0