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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.29 95.43 94.62 95.05 95.30 97.75 99.59


Total test records in report: 2846
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T1050 /workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1286680541 Feb 18 04:05:27 PM PST 24 Feb 18 04:10:43 PM PST 24 2988066590 ps
T1051 /workspace/coverage/default/2.chip_tap_straps_dev.1724054014 Feb 18 04:14:18 PM PST 24 Feb 18 04:17:46 PM PST 24 3030058474 ps
T1052 /workspace/coverage/default/1.chip_sw_hmac_enc_idle.3503986563 Feb 18 04:02:01 PM PST 24 Feb 18 04:06:19 PM PST 24 3022559304 ps
T133 /workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.2309687372 Feb 18 03:53:29 PM PST 24 Feb 18 03:55:38 PM PST 24 3003324136 ps
T1053 /workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.1263332924 Feb 18 04:16:28 PM PST 24 Feb 18 04:23:50 PM PST 24 3857073752 ps
T1054 /workspace/coverage/default/0.chip_sw_otbn_randomness.81593373 Feb 18 03:57:12 PM PST 24 Feb 18 04:13:09 PM PST 24 6429351604 ps
T1055 /workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1788221847 Feb 18 04:15:14 PM PST 24 Feb 18 04:22:11 PM PST 24 3289912968 ps
T100 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1715424884 Feb 18 03:58:09 PM PST 24 Feb 18 04:07:04 PM PST 24 7586512156 ps
T774 /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.4209662747 Feb 18 04:23:12 PM PST 24 Feb 18 04:29:15 PM PST 24 3947899720 ps
T1056 /workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.3041616629 Feb 18 04:16:31 PM PST 24 Feb 18 04:23:42 PM PST 24 4788073210 ps
T1057 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.4029551129 Feb 18 04:01:04 PM PST 24 Feb 18 04:34:02 PM PST 24 8546407490 ps
T243 /workspace/coverage/default/95.chip_sw_all_escalation_resets.2326338756 Feb 18 04:25:56 PM PST 24 Feb 18 04:36:30 PM PST 24 6157487240 ps
T1058 /workspace/coverage/default/0.chip_sw_kmac_smoketest.3774308313 Feb 18 03:56:40 PM PST 24 Feb 18 04:02:03 PM PST 24 3079020040 ps
T670 /workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.2757391819 Feb 18 04:05:36 PM PST 24 Feb 18 04:15:39 PM PST 24 4849706773 ps
T270 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.799167257 Feb 18 04:19:45 PM PST 24 Feb 18 04:27:46 PM PST 24 4311455395 ps
T1059 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3595264526 Feb 18 04:01:46 PM PST 24 Feb 18 04:42:41 PM PST 24 8207104440 ps
T353 /workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2614121667 Feb 18 03:55:17 PM PST 24 Feb 18 03:59:13 PM PST 24 2863103041 ps
T355 /workspace/coverage/default/2.chip_sw_all_escalation_resets.2857406690 Feb 18 04:09:13 PM PST 24 Feb 18 04:21:23 PM PST 24 4955269558 ps
T378 /workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.1564620606 Feb 18 03:56:28 PM PST 24 Feb 18 04:19:42 PM PST 24 18543041290 ps
T1060 /workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.1881793702 Feb 18 04:10:35 PM PST 24 Feb 18 04:29:31 PM PST 24 8601557900 ps
T237 /workspace/coverage/default/0.chip_sw_plic_sw_irq.3708301093 Feb 18 03:53:43 PM PST 24 Feb 18 03:56:59 PM PST 24 2949298760 ps
T24 /workspace/coverage/default/0.chip_sw_usbdev_config_host.1943551589 Feb 18 03:52:41 PM PST 24 Feb 18 04:25:55 PM PST 24 7985821988 ps
T763 /workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.677475351 Feb 18 04:22:24 PM PST 24 Feb 18 04:28:46 PM PST 24 3414447396 ps
T808 /workspace/coverage/default/73.chip_sw_all_escalation_resets.1614964724 Feb 18 04:23:17 PM PST 24 Feb 18 04:34:33 PM PST 24 5400388904 ps
T220 /workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.4115193390 Feb 18 03:53:24 PM PST 24 Feb 18 05:16:26 PM PST 24 46689191568 ps
T787 /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3333449066 Feb 18 04:25:23 PM PST 24 Feb 18 04:33:21 PM PST 24 3495961400 ps
T725 /workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4087867024 Feb 18 04:19:13 PM PST 24 Feb 18 04:25:28 PM PST 24 3583229882 ps
T1061 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3436151536 Feb 18 04:07:10 PM PST 24 Feb 18 04:13:44 PM PST 24 3278446184 ps
T713 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1044650785 Feb 18 04:11:13 PM PST 24 Feb 18 04:41:55 PM PST 24 22379653152 ps
T1062 /workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1230484507 Feb 18 03:56:54 PM PST 24 Feb 18 04:14:06 PM PST 24 10377299511 ps
T337 /workspace/coverage/default/2.chip_sw_hmac_enc.1988086638 Feb 18 04:12:53 PM PST 24 Feb 18 04:17:52 PM PST 24 2894879524 ps
T159 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2576958924 Feb 18 04:03:14 PM PST 24 Feb 18 04:11:33 PM PST 24 5188962836 ps
T1063 /workspace/coverage/default/2.chip_sw_uart_tx_rx.4262639 Feb 18 04:08:53 PM PST 24 Feb 18 04:24:41 PM PST 24 5102340296 ps
T1064 /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.3522111088 Feb 18 03:55:20 PM PST 24 Feb 18 04:00:54 PM PST 24 3352562744 ps
T1065 /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1016807560 Feb 18 03:55:27 PM PST 24 Feb 18 03:58:15 PM PST 24 2530855535 ps
T74 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.10695388 Feb 18 03:52:29 PM PST 24 Feb 18 04:01:09 PM PST 24 3605454620 ps
T330 /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.2791909286 Feb 18 03:54:11 PM PST 24 Feb 18 04:01:43 PM PST 24 3806516818 ps
T1066 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.642482637 Feb 18 03:59:09 PM PST 24 Feb 18 04:47:25 PM PST 24 28356445831 ps
T1067 /workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2302252724 Feb 18 04:15:53 PM PST 24 Feb 18 04:22:07 PM PST 24 5081552406 ps
T799 /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1056209418 Feb 18 04:21:26 PM PST 24 Feb 18 04:27:49 PM PST 24 3812848580 ps
T1068 /workspace/coverage/default/0.chip_sw_edn_sw_mode.2218365773 Feb 18 03:53:08 PM PST 24 Feb 18 04:14:56 PM PST 24 7030158928 ps
T1069 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.1006022350 Feb 18 04:14:29 PM PST 24 Feb 18 04:26:40 PM PST 24 5914114908 ps
T721 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.3652905880 Feb 18 04:12:10 PM PST 24 Feb 18 05:01:47 PM PST 24 20193821332 ps
T1070 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.2804565123 Feb 18 03:57:56 PM PST 24 Feb 18 04:01:14 PM PST 24 2691560032 ps
T819 /workspace/coverage/default/82.chip_sw_all_escalation_resets.1522171382 Feb 18 04:24:51 PM PST 24 Feb 18 04:34:32 PM PST 24 5863886136 ps
T800 /workspace/coverage/default/9.chip_sw_all_escalation_resets.2269935319 Feb 18 04:19:36 PM PST 24 Feb 18 04:30:39 PM PST 24 4601746024 ps
T1071 /workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.890181769 Feb 18 03:59:00 PM PST 24 Feb 18 04:05:31 PM PST 24 3191466160 ps
T1072 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3407528464 Feb 18 04:15:27 PM PST 24 Feb 18 04:21:56 PM PST 24 4139700600 ps
T332 /workspace/coverage/default/0.chip_sival_flash_info_access.397365582 Feb 18 03:52:38 PM PST 24 Feb 18 04:00:17 PM PST 24 3930088904 ps
T1073 /workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.3686101317 Feb 18 04:00:25 PM PST 24 Feb 18 04:06:54 PM PST 24 2963667995 ps
T1074 /workspace/coverage/default/2.chip_sw_clkmgr_off_peri.2098370198 Feb 18 04:19:37 PM PST 24 Feb 18 04:37:23 PM PST 24 10389389076 ps
T352 /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.2709517084 Feb 18 04:18:30 PM PST 24 Feb 18 04:27:51 PM PST 24 4528721544 ps
T1075 /workspace/coverage/default/58.chip_sw_all_escalation_resets.4135315336 Feb 18 04:21:39 PM PST 24 Feb 18 04:31:25 PM PST 24 4497444834 ps
T365 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.2166102041 Feb 18 04:02:06 PM PST 24 Feb 18 05:01:05 PM PST 24 12106572224 ps
T696 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.1722134712 Feb 18 03:54:11 PM PST 24 Feb 18 03:58:00 PM PST 24 3121459964 ps
T1076 /workspace/coverage/default/1.chip_sw_edn_kat.248958267 Feb 18 04:02:35 PM PST 24 Feb 18 04:14:27 PM PST 24 3571489516 ps
T145 /workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1684030878 Feb 18 04:15:48 PM PST 24 Feb 18 05:30:07 PM PST 24 30071918275 ps
T1077 /workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1731742419 Feb 18 03:54:03 PM PST 24 Feb 18 04:09:53 PM PST 24 5220554740 ps
T271 /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3537704776 Feb 18 04:12:20 PM PST 24 Feb 18 04:21:10 PM PST 24 4389172482 ps
T1078 /workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.4129391959 Feb 18 03:55:30 PM PST 24 Feb 18 04:26:14 PM PST 24 20474597396 ps
T40 /workspace/coverage/default/1.chip_sw_spi_device_tpm.181347097 Feb 18 03:59:56 PM PST 24 Feb 18 04:07:54 PM PST 24 2785538329 ps
T1079 /workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.2126568902 Feb 18 03:57:08 PM PST 24 Feb 18 04:12:54 PM PST 24 5780059302 ps
T1080 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1554094914 Feb 18 04:20:07 PM PST 24 Feb 18 04:23:53 PM PST 24 3106919780 ps
T221 /workspace/coverage/default/2.chip_sw_flash_init.1476034394 Feb 18 04:10:07 PM PST 24 Feb 18 04:36:51 PM PST 24 21951652796 ps
T1081 /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.175223028 Feb 18 03:54:29 PM PST 24 Feb 18 04:01:12 PM PST 24 4744178014 ps
T215 /workspace/coverage/default/0.chip_sw_flash_init.3098343557 Feb 18 03:53:20 PM PST 24 Feb 18 04:25:49 PM PST 24 20387587824 ps
T1082 /workspace/coverage/default/2.chip_sw_example_flash.1700561705 Feb 18 04:08:07 PM PST 24 Feb 18 04:13:21 PM PST 24 2705091936 ps
T1083 /workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.2365822151 Feb 18 04:09:34 PM PST 24 Feb 18 04:27:10 PM PST 24 6062120750 ps
T1084 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.315566826 Feb 18 04:16:45 PM PST 24 Feb 18 04:30:00 PM PST 24 5063750328 ps
T775 /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.720055669 Feb 18 04:23:36 PM PST 24 Feb 18 04:30:57 PM PST 24 3975399720 ps
T812 /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1508370245 Feb 18 04:21:54 PM PST 24 Feb 18 04:28:53 PM PST 24 3837729792 ps
T1085 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2775173162 Feb 18 04:19:07 PM PST 24 Feb 18 04:28:56 PM PST 24 6042144000 ps
T1086 /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.4184105615 Feb 18 03:53:07 PM PST 24 Feb 18 04:10:03 PM PST 24 6078221040 ps
T134 /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.477852265 Feb 18 03:53:13 PM PST 24 Feb 18 03:58:29 PM PST 24 2867040569 ps
T1087 /workspace/coverage/default/2.chip_sw_hmac_smoketest.1309427950 Feb 18 04:16:08 PM PST 24 Feb 18 04:23:32 PM PST 24 3060824496 ps
T826 /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3351577925 Feb 18 04:24:02 PM PST 24 Feb 18 04:29:40 PM PST 24 3833407186 ps
T1088 /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1172070789 Feb 18 04:19:39 PM PST 24 Feb 18 05:01:24 PM PST 24 12646499144 ps
T1089 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1927292178 Feb 18 04:11:50 PM PST 24 Feb 18 07:38:16 PM PST 24 254541355298 ps
T57 /workspace/coverage/default/1.chip_sw_alert_test.1254826135 Feb 18 04:02:56 PM PST 24 Feb 18 04:08:02 PM PST 24 3011665386 ps
T708 /workspace/coverage/default/1.chip_sw_power_idle_load.2688554771 Feb 18 04:07:19 PM PST 24 Feb 18 04:21:51 PM PST 24 4206902510 ps
T1090 /workspace/coverage/default/0.chip_tap_straps_testunlock0.2901343822 Feb 18 03:55:39 PM PST 24 Feb 18 04:03:03 PM PST 24 5422290215 ps
T224 /workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.943392568 Feb 18 04:14:18 PM PST 24 Feb 18 04:52:34 PM PST 24 20862103471 ps
T1091 /workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3850324649 Feb 18 04:06:25 PM PST 24 Feb 18 04:26:42 PM PST 24 7669377333 ps
T1092 /workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1914055181 Feb 18 04:14:56 PM PST 24 Feb 18 04:21:38 PM PST 24 2809559981 ps
T312 /workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2823514889 Feb 18 04:00:04 PM PST 24 Feb 18 04:16:25 PM PST 24 5439521684 ps
T1093 /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.2749152140 Feb 18 04:16:11 PM PST 24 Feb 18 04:30:37 PM PST 24 4964189542 ps
T1094 /workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2075408466 Feb 18 04:02:49 PM PST 24 Feb 18 04:06:28 PM PST 24 2629556536 ps
T191 /workspace/coverage/default/1.chip_sw_alert_handler_entropy.3397276300 Feb 18 04:02:32 PM PST 24 Feb 18 04:10:11 PM PST 24 4115888509 ps
T1095 /workspace/coverage/default/0.rom_e2e_asm_init_prod.1569626603 Feb 18 04:03:47 PM PST 24 Feb 18 04:38:13 PM PST 24 8558368820 ps
T1096 /workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.874231543 Feb 18 04:01:55 PM PST 24 Feb 18 04:11:34 PM PST 24 5549066552 ps
T1097 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.4252765584 Feb 18 04:02:35 PM PST 24 Feb 18 04:09:29 PM PST 24 5077845268 ps
T672 /workspace/coverage/default/3.chip_tap_straps_dev.2601569099 Feb 18 04:16:35 PM PST 24 Feb 18 04:38:00 PM PST 24 11035969345 ps
T1098 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3460158273 Feb 18 03:54:14 PM PST 24 Feb 18 04:04:14 PM PST 24 6081033636 ps
T1099 /workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.3197417999 Feb 18 04:13:18 PM PST 24 Feb 18 04:25:08 PM PST 24 9777298045 ps
T1100 /workspace/coverage/default/0.chip_sw_aes_enc.438672032 Feb 18 03:57:55 PM PST 24 Feb 18 04:03:40 PM PST 24 3031594600 ps
T764 /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2370810613 Feb 18 04:19:47 PM PST 24 Feb 18 04:24:59 PM PST 24 3883599606 ps
T402 /workspace/coverage/default/0.chip_jtag_mem_access.3186582104 Feb 18 03:47:26 PM PST 24 Feb 18 04:14:34 PM PST 24 13010939770 ps
T809 /workspace/coverage/default/84.chip_sw_all_escalation_resets.3851254879 Feb 18 04:25:27 PM PST 24 Feb 18 04:36:58 PM PST 24 5758565540 ps
T349 /workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3851316258 Feb 18 04:13:41 PM PST 24 Feb 18 04:19:17 PM PST 24 4830642394 ps
T225 /workspace/coverage/default/1.chip_sw_flash_init.4083442860 Feb 18 03:57:38 PM PST 24 Feb 18 04:35:00 PM PST 24 23487307236 ps
T664 /workspace/coverage/default/2.chip_sw_edn_auto_mode.1086252670 Feb 18 04:12:02 PM PST 24 Feb 18 04:30:03 PM PST 24 4539067942 ps
T794 /workspace/coverage/default/90.chip_sw_all_escalation_resets.3347383484 Feb 18 04:24:31 PM PST 24 Feb 18 04:34:24 PM PST 24 5694355760 ps
T1101 /workspace/coverage/default/2.rom_e2e_asm_init_dev.745906762 Feb 18 04:19:47 PM PST 24 Feb 18 04:43:16 PM PST 24 8409330447 ps
T1102 /workspace/coverage/default/1.chip_tap_straps_rma.3484867892 Feb 18 04:04:54 PM PST 24 Feb 18 04:12:09 PM PST 24 3966541109 ps
T781 /workspace/coverage/default/64.chip_sw_all_escalation_resets.3479205584 Feb 18 04:22:14 PM PST 24 Feb 18 04:32:23 PM PST 24 4707656300 ps
T714 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.626126227 Feb 18 03:52:26 PM PST 24 Feb 18 04:25:14 PM PST 24 22972408632 ps
T272 /workspace/coverage/default/5.chip_sw_data_integrity_escalation.2456504834 Feb 18 04:17:34 PM PST 24 Feb 18 04:27:19 PM PST 24 4333161430 ps
T415 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.1079567490 Feb 18 03:53:27 PM PST 24 Feb 18 04:07:15 PM PST 24 5327471520 ps
T709 /workspace/coverage/default/2.rom_raw_unlock.2151883688 Feb 18 04:16:21 PM PST 24 Feb 18 04:43:35 PM PST 24 16304183006 ps
T1103 /workspace/coverage/default/1.chip_sw_example_concurrency.439346684 Feb 18 04:01:37 PM PST 24 Feb 18 04:06:05 PM PST 24 3296522192 ps
T1104 /workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3100883217 Feb 18 04:01:13 PM PST 24 Feb 18 04:10:29 PM PST 24 4575097446 ps
T1105 /workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1284646691 Feb 18 04:16:34 PM PST 24 Feb 18 04:24:46 PM PST 24 4298869600 ps
T1106 /workspace/coverage/default/3.chip_sw_uart_tx_rx.960259518 Feb 18 04:16:09 PM PST 24 Feb 18 04:29:30 PM PST 24 5300117604 ps
T51 /workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.3610563496 Feb 18 04:13:43 PM PST 24 Feb 18 04:21:51 PM PST 24 4417428492 ps
T1107 /workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4161401462 Feb 18 04:09:25 PM PST 24 Feb 18 04:26:50 PM PST 24 5655486497 ps
T1108 /workspace/coverage/default/0.chip_sw_edn_kat.2148316396 Feb 18 03:54:49 PM PST 24 Feb 18 04:05:03 PM PST 24 3176218272 ps
T797 /workspace/coverage/default/76.chip_sw_all_escalation_resets.2612849365 Feb 18 04:23:00 PM PST 24 Feb 18 04:31:52 PM PST 24 6084243064 ps
T1109 /workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.2565891051 Feb 18 04:01:26 PM PST 24 Feb 18 04:52:59 PM PST 24 12665757336 ps
T356 /workspace/coverage/default/71.chip_sw_all_escalation_resets.178625579 Feb 18 04:22:51 PM PST 24 Feb 18 04:31:24 PM PST 24 4400744560 ps
T75 /workspace/coverage/default/0.chip_sw_usbdev_pullup.4200688637 Feb 18 03:52:56 PM PST 24 Feb 18 03:57:27 PM PST 24 3086204964 ps
T495 /workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.318812095 Feb 18 04:00:44 PM PST 24 Feb 18 04:27:37 PM PST 24 9542761926 ps
T126 /workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.1463772475 Feb 18 03:53:52 PM PST 24 Feb 18 04:02:58 PM PST 24 4908137088 ps
T665 /workspace/coverage/default/1.chip_sw_edn_auto_mode.2924563662 Feb 18 04:02:58 PM PST 24 Feb 18 04:24:52 PM PST 24 5737683210 ps
T1110 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3610282240 Feb 18 04:03:54 PM PST 24 Feb 18 04:14:00 PM PST 24 4328289462 ps
T676 /workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1586550140 Feb 18 04:09:27 PM PST 24 Feb 18 04:11:11 PM PST 24 2625437285 ps
T1111 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2012205345 Feb 18 04:00:02 PM PST 24 Feb 18 06:54:38 PM PST 24 59154375220 ps
T1112 /workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.2924698877 Feb 18 03:53:35 PM PST 24 Feb 18 03:56:11 PM PST 24 3601448513 ps
T1113 /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.3087604668 Feb 18 04:17:15 PM PST 24 Feb 18 04:23:37 PM PST 24 7293957840 ps
T1114 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.1689047419 Feb 18 04:02:41 PM PST 24 Feb 18 04:25:21 PM PST 24 10596876080 ps
T723 /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.583130112 Feb 18 04:22:52 PM PST 24 Feb 18 04:29:35 PM PST 24 4335803686 ps
T789 /workspace/coverage/default/54.chip_sw_all_escalation_resets.306565405 Feb 18 04:21:14 PM PST 24 Feb 18 04:28:42 PM PST 24 5088737320 ps
T1115 /workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2929170689 Feb 18 04:13:27 PM PST 24 Feb 18 04:19:21 PM PST 24 3748747163 ps
T1116 /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3156318248 Feb 18 03:52:59 PM PST 24 Feb 18 07:08:53 PM PST 24 254921627376 ps
T1117 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.593969859 Feb 18 04:16:48 PM PST 24 Feb 18 04:19:39 PM PST 24 2545244392 ps
T1118 /workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3825579378 Feb 18 04:21:58 PM PST 24 Feb 18 04:29:50 PM PST 24 3930012368 ps
T795 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.3161379398 Feb 18 04:23:44 PM PST 24 Feb 18 04:30:07 PM PST 24 3674930128 ps
T379 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.857286270 Feb 18 03:54:58 PM PST 24 Feb 18 04:20:27 PM PST 24 17860399750 ps
T1119 /workspace/coverage/default/0.chip_sw_alert_handler_escalation.3578498519 Feb 18 03:54:53 PM PST 24 Feb 18 04:05:06 PM PST 24 5982082258 ps
T1120 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1456288086 Feb 18 04:11:13 PM PST 24 Feb 18 04:50:39 PM PST 24 28821564794 ps
T767 /workspace/coverage/default/61.chip_sw_all_escalation_resets.868210276 Feb 18 04:21:50 PM PST 24 Feb 18 04:31:05 PM PST 24 4674800300 ps
T1121 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.3202422811 Feb 18 04:00:39 PM PST 24 Feb 18 04:09:12 PM PST 24 5748164048 ps
T1122 /workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.723211866 Feb 18 04:03:10 PM PST 24 Feb 18 04:38:25 PM PST 24 25498457368 ps
T688 /workspace/coverage/default/86.chip_sw_all_escalation_resets.174776323 Feb 18 04:24:03 PM PST 24 Feb 18 04:32:31 PM PST 24 5563559700 ps
T1123 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.1452798186 Feb 18 04:16:44 PM PST 24 Feb 18 04:28:29 PM PST 24 5471514160 ps
T492 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.1288508958 Feb 18 03:55:08 PM PST 24 Feb 18 04:11:22 PM PST 24 4520466040 ps
T124 /workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.304529474 Feb 18 03:52:59 PM PST 24 Feb 18 03:54:31 PM PST 24 2173525675 ps
T1124 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.1487681724 Feb 18 03:57:22 PM PST 24 Feb 18 04:00:28 PM PST 24 2101875284 ps
T36 /workspace/coverage/default/0.chip_sw_spi_host_tx_rx.3680574519 Feb 18 03:52:57 PM PST 24 Feb 18 03:59:02 PM PST 24 3296194200 ps
T177 /workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.3236512707 Feb 18 04:09:04 PM PST 24 Feb 18 04:20:20 PM PST 24 4066095351 ps
T1125 /workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.2864845566 Feb 18 04:19:15 PM PST 24 Feb 18 04:24:36 PM PST 24 4033701592 ps
T324 /workspace/coverage/default/2.chip_sw_pattgen_ios.3653492327 Feb 18 04:10:04 PM PST 24 Feb 18 04:14:00 PM PST 24 2396608152 ps
T297 /workspace/coverage/default/0.chip_sw_rstmgr_alert_info.4294156423 Feb 18 03:55:31 PM PST 24 Feb 18 04:29:51 PM PST 24 13790376636 ps
T1126 /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2710493690 Feb 18 03:55:41 PM PST 24 Feb 18 04:06:03 PM PST 24 4381527850 ps
T1127 /workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3960398616 Feb 18 03:51:42 PM PST 24 Feb 18 03:59:52 PM PST 24 5871459063 ps
T1128 /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3149009863 Feb 18 03:54:41 PM PST 24 Feb 18 03:56:45 PM PST 24 1945934296 ps
T1129 /workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2494474609 Feb 18 04:16:12 PM PST 24 Feb 18 04:22:28 PM PST 24 3396326200 ps
T244 /workspace/coverage/default/43.chip_sw_all_escalation_resets.1463720282 Feb 18 04:22:09 PM PST 24 Feb 18 04:30:18 PM PST 24 4573106800 ps
T1130 /workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2180274832 Feb 18 03:58:26 PM PST 24 Feb 18 04:24:43 PM PST 24 11255653051 ps
T1131 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2511536409 Feb 18 04:19:19 PM PST 24 Feb 18 04:25:32 PM PST 24 3450761382 ps
T1132 /workspace/coverage/default/1.chip_sw_rv_timer_irq.488629700 Feb 18 04:01:12 PM PST 24 Feb 18 04:04:58 PM PST 24 2575203600 ps
T777 /workspace/coverage/default/87.chip_sw_all_escalation_resets.1398784745 Feb 18 04:24:13 PM PST 24 Feb 18 04:34:37 PM PST 24 5227922744 ps
T305 /workspace/coverage/default/1.chip_sw_entropy_src_csrng.2829120006 Feb 18 04:04:29 PM PST 24 Feb 18 04:39:05 PM PST 24 8365597376 ps
T141 /workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.133204842 Feb 18 04:05:25 PM PST 24 Feb 18 04:09:12 PM PST 24 2927437845 ps
T1133 /workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3534681442 Feb 18 03:52:04 PM PST 24 Feb 18 04:05:50 PM PST 24 5218066792 ps
T302 /workspace/coverage/default/0.chip_plic_all_irqs_20.1217640964 Feb 18 03:55:24 PM PST 24 Feb 18 04:11:38 PM PST 24 4578657316 ps
T1134 /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4036719439 Feb 18 03:58:22 PM PST 24 Feb 18 04:20:34 PM PST 24 7952042910 ps
T1135 /workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.850148982 Feb 18 04:11:05 PM PST 24 Feb 18 04:27:43 PM PST 24 5232882080 ps
T160 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.31140188 Feb 18 04:13:22 PM PST 24 Feb 18 04:23:31 PM PST 24 5212436472 ps
T1136 /workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2772994912 Feb 18 04:05:53 PM PST 24 Feb 18 05:06:29 PM PST 24 24356153290 ps
T1137 /workspace/coverage/default/1.chip_sw_aes_enc.959435295 Feb 18 04:00:58 PM PST 24 Feb 18 04:05:35 PM PST 24 2853697018 ps
T1138 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1284681758 Feb 18 04:14:34 PM PST 24 Feb 18 04:24:28 PM PST 24 4239250140 ps
T1139 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1848183651 Feb 18 03:54:21 PM PST 24 Feb 18 04:06:52 PM PST 24 10456604500 ps
T1140 /workspace/coverage/default/1.chip_sw_hmac_enc.499094414 Feb 18 04:02:54 PM PST 24 Feb 18 04:08:23 PM PST 24 3197477832 ps
T29 /workspace/coverage/default/0.chip_sw_gpio.4285796821 Feb 18 03:54:14 PM PST 24 Feb 18 04:00:55 PM PST 24 3484786584 ps
T222 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.262759850 Feb 18 04:01:12 PM PST 24 Feb 18 05:22:35 PM PST 24 46942490927 ps
T496 /workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.410205903 Feb 18 03:58:17 PM PST 24 Feb 18 04:29:07 PM PST 24 12593355863 ps
T284 /workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.2191190581 Feb 18 03:55:37 PM PST 24 Feb 18 03:59:15 PM PST 24 2642619019 ps
T1141 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3449003052 Feb 18 04:13:35 PM PST 24 Feb 18 04:24:54 PM PST 24 4625280828 ps
T1142 /workspace/coverage/default/0.chip_sw_kmac_app_rom.3062735352 Feb 18 03:54:55 PM PST 24 Feb 18 03:58:09 PM PST 24 2390679548 ps
T273 /workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1310910664 Feb 18 03:55:12 PM PST 24 Feb 18 04:05:59 PM PST 24 5662122150 ps
T762 /workspace/coverage/default/26.chip_sw_all_escalation_resets.3147248728 Feb 18 04:19:29 PM PST 24 Feb 18 04:28:21 PM PST 24 4662323544 ps
T731 /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.2854192982 Feb 18 04:23:45 PM PST 24 Feb 18 04:30:34 PM PST 24 3962037492 ps
T30 /workspace/coverage/default/2.chip_sw_gpio.535123030 Feb 18 04:10:42 PM PST 24 Feb 18 04:17:37 PM PST 24 4012515708 ps
T1143 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2459252414 Feb 18 03:56:24 PM PST 24 Feb 18 04:06:11 PM PST 24 4884368856 ps
T1144 /workspace/coverage/default/2.chip_sw_aes_idle.4237319352 Feb 18 04:12:08 PM PST 24 Feb 18 04:16:22 PM PST 24 2433313580 ps
T1145 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.992153667 Feb 18 04:18:47 PM PST 24 Feb 18 04:34:00 PM PST 24 5674351526 ps
T1146 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1618673408 Feb 18 04:11:02 PM PST 24 Feb 18 04:14:48 PM PST 24 2731253551 ps
T1147 /workspace/coverage/default/0.rom_e2e_asm_init_rma.3060380105 Feb 18 04:02:09 PM PST 24 Feb 18 04:33:58 PM PST 24 8116827196 ps
T1148 /workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2504755507 Feb 18 03:54:42 PM PST 24 Feb 18 04:01:43 PM PST 24 3184245750 ps
T796 /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3320172071 Feb 18 04:23:13 PM PST 24 Feb 18 04:30:06 PM PST 24 3483136176 ps
T1149 /workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3114366641 Feb 18 03:53:39 PM PST 24 Feb 18 04:41:40 PM PST 24 14400255484 ps
T1150 /workspace/coverage/default/1.chip_sw_flash_crash_alert.1017120181 Feb 18 04:05:28 PM PST 24 Feb 18 04:19:17 PM PST 24 5562202490 ps
T1151 /workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3905072664 Feb 18 04:09:16 PM PST 24 Feb 18 04:28:01 PM PST 24 6621368428 ps
T311 /workspace/coverage/default/0.chip_plic_all_irqs_0.542555351 Feb 18 03:58:21 PM PST 24 Feb 18 04:21:01 PM PST 24 6176272880 ps
T218 /workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.63628436 Feb 18 04:09:54 PM PST 24 Feb 18 05:42:32 PM PST 24 49275355535 ps
T146 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.144824781 Feb 18 03:55:37 PM PST 24 Feb 18 04:31:53 PM PST 24 11172549208 ps
T163 /workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.3940430218 Feb 18 03:54:56 PM PST 24 Feb 18 04:03:37 PM PST 24 5249702266 ps
T1152 /workspace/coverage/default/8.chip_sw_all_escalation_resets.510458525 Feb 18 04:19:08 PM PST 24 Feb 18 04:29:20 PM PST 24 5093080194 ps
T1153 /workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3447534488 Feb 18 04:00:12 PM PST 24 Feb 18 04:05:22 PM PST 24 2731599250 ps
T1154 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.2084952981 Feb 18 03:57:39 PM PST 24 Feb 18 04:05:39 PM PST 24 4628804200 ps
T216 /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.1088376458 Feb 18 03:54:51 PM PST 24 Feb 18 04:27:48 PM PST 24 26283650728 ps
T813 /workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.339909389 Feb 18 04:21:03 PM PST 24 Feb 18 04:27:08 PM PST 24 4101824798 ps
T1155 /workspace/coverage/default/0.chip_sw_uart_tx_rx.931551649 Feb 18 03:56:37 PM PST 24 Feb 18 04:12:40 PM PST 24 5401555122 ps
T493 /workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3439851101 Feb 18 04:11:22 PM PST 24 Feb 18 04:27:55 PM PST 24 4763453400 ps
T1156 /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.3506279743 Feb 18 03:56:26 PM PST 24 Feb 18 04:04:44 PM PST 24 4758757624 ps
T1157 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2828919774 Feb 18 04:14:14 PM PST 24 Feb 18 04:21:06 PM PST 24 5238842299 ps
T1158 /workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3255841096 Feb 18 04:00:26 PM PST 24 Feb 18 04:19:58 PM PST 24 8273217644 ps
T1159 /workspace/coverage/default/2.chip_sw_clkmgr_jitter.2230892214 Feb 18 04:14:23 PM PST 24 Feb 18 04:17:40 PM PST 24 3107317011 ps
T1160 /workspace/coverage/default/2.chip_sw_uart_smoketest_signed.2889868356 Feb 18 04:19:41 PM PST 24 Feb 18 04:49:35 PM PST 24 8736192568 ps
T1161 /workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3601753911 Feb 18 03:54:53 PM PST 24 Feb 18 04:03:06 PM PST 24 4216075420 ps
T783 /workspace/coverage/default/21.chip_sw_all_escalation_resets.1157644173 Feb 18 04:19:19 PM PST 24 Feb 18 04:29:27 PM PST 24 5629586826 ps
T1162 /workspace/coverage/default/2.chip_sw_kmac_app_rom.1346714386 Feb 18 04:13:03 PM PST 24 Feb 18 04:16:13 PM PST 24 2215500738 ps
T199 /workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1772020306 Feb 18 03:53:58 PM PST 24 Feb 18 04:04:51 PM PST 24 4679270651 ps
T1163 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.556885352 Feb 18 03:57:47 PM PST 24 Feb 18 04:08:04 PM PST 24 4249572666 ps
T209 /workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2833027275 Feb 18 04:03:30 PM PST 24 Feb 18 04:12:12 PM PST 24 4615557496 ps
T1164 /workspace/coverage/default/2.chip_sw_csrng_smoketest.2160214086 Feb 18 04:16:57 PM PST 24 Feb 18 04:20:42 PM PST 24 3257148808 ps
T1165 /workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1463305254 Feb 18 04:07:59 PM PST 24 Feb 18 04:13:05 PM PST 24 4287072924 ps
T729 /workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2199763837 Feb 18 04:22:20 PM PST 24 Feb 18 04:27:07 PM PST 24 3684230796 ps
T1166 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.3202574115 Feb 18 03:58:11 PM PST 24 Feb 18 04:06:37 PM PST 24 6421525520 ps
T1167 /workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.414028385 Feb 18 04:12:47 PM PST 24 Feb 18 04:21:47 PM PST 24 5101525380 ps
T786 /workspace/coverage/default/44.chip_sw_all_escalation_resets.1113277891 Feb 18 04:20:14 PM PST 24 Feb 18 04:35:54 PM PST 24 6465511786 ps
T1168 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.3316713119 Feb 18 03:55:04 PM PST 24 Feb 18 04:11:27 PM PST 24 7241564000 ps
T1169 /workspace/coverage/default/1.chip_sw_csrng_kat_test.2195540221 Feb 18 04:04:10 PM PST 24 Feb 18 04:07:52 PM PST 24 2043790280 ps
T279 /workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2097614343 Feb 18 04:21:18 PM PST 24 Feb 18 04:27:05 PM PST 24 3531972414 ps
T217 /workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.2045929132 Feb 18 04:10:47 PM PST 24 Feb 18 05:26:20 PM PST 24 47332638149 ps
T1170 /workspace/coverage/default/0.chip_sw_flash_ctrl_access.966672896 Feb 18 03:52:55 PM PST 24 Feb 18 04:11:51 PM PST 24 5815500100 ps
T1171 /workspace/coverage/default/2.chip_sw_otbn_smoketest.837341858 Feb 18 04:16:29 PM PST 24 Feb 18 04:49:41 PM PST 24 9756545776 ps
T1172 /workspace/coverage/default/65.chip_sw_all_escalation_resets.234093689 Feb 18 04:23:44 PM PST 24 Feb 18 04:36:23 PM PST 24 5762182456 ps
T1173 /workspace/coverage/default/15.chip_sw_uart_rand_baudrate.3025606971 Feb 18 04:18:01 PM PST 24 Feb 18 04:30:51 PM PST 24 4966997448 ps
T1174 /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.3143299612 Feb 18 04:18:24 PM PST 24 Feb 18 05:33:13 PM PST 24 22973308694 ps
T498 /workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.2847360827 Feb 18 04:02:26 PM PST 24 Feb 18 04:09:34 PM PST 24 3922283424 ps
T1175 /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.788584016 Feb 18 03:55:10 PM PST 24 Feb 18 04:11:18 PM PST 24 4542777694 ps
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T1176 /workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.629902017 Feb 18 04:10:00 PM PST 24 Feb 18 04:32:45 PM PST 24 13303017570 ps
T303 /workspace/coverage/default/1.chip_plic_all_irqs_20.2399293520 Feb 18 04:04:11 PM PST 24 Feb 18 04:15:06 PM PST 24 5007518908 ps
T706 /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3374971563 Feb 18 03:53:32 PM PST 24 Feb 18 04:07:35 PM PST 24 5069979808 ps
T1177 /workspace/coverage/default/2.chip_sw_power_idle_load.500382525 Feb 18 04:20:09 PM PST 24 Feb 18 04:29:52 PM PST 24 4862512616 ps
T1178 /workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.1784716827 Feb 18 04:05:49 PM PST 24 Feb 18 04:36:44 PM PST 24 27070645850 ps
T666 /workspace/coverage/default/0.chip_sw_edn_auto_mode.3555595227 Feb 18 03:56:26 PM PST 24 Feb 18 04:14:13 PM PST 24 4580448920 ps
T1179 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.2075445431 Feb 18 04:18:35 PM PST 24 Feb 18 04:34:48 PM PST 24 5044154176 ps
T403 /workspace/coverage/default/2.chip_jtag_mem_access.1451480910 Feb 18 04:06:49 PM PST 24 Feb 18 04:31:06 PM PST 24 13232837880 ps
T1180 /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.402585923 Feb 18 04:16:54 PM PST 24 Feb 18 04:51:15 PM PST 24 22908259356 ps
T1181 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2753556945 Feb 18 04:18:15 PM PST 24 Feb 18 04:25:48 PM PST 24 6022545131 ps
T1182 /workspace/coverage/default/1.rom_e2e_asm_init_rma.1657113369 Feb 18 04:13:42 PM PST 24 Feb 18 04:42:20 PM PST 24 8554917011 ps
T333 /workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3170691557 Feb 18 04:20:22 PM PST 24 Feb 18 04:33:02 PM PST 24 6020362406 ps
T1183 /workspace/coverage/default/89.chip_sw_all_escalation_resets.1633779007 Feb 18 04:25:42 PM PST 24 Feb 18 04:34:09 PM PST 24 3958877990 ps
T259 /workspace/coverage/default/3.chip_sw_data_integrity_escalation.1757870300 Feb 18 04:16:44 PM PST 24 Feb 18 04:27:08 PM PST 24 4451856808 ps
T1184 /workspace/coverage/default/2.rom_e2e_shutdown_output.1150441967 Feb 18 04:21:06 PM PST 24 Feb 18 05:05:35 PM PST 24 22596072006 ps
T1185 /workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.4192759211 Feb 18 04:11:11 PM PST 24 Feb 18 05:24:38 PM PST 24 18686937488 ps
T1186 /workspace/coverage/default/0.chip_sw_inject_scramble_seed.755814479 Feb 18 03:53:30 PM PST 24 Feb 18 07:10:32 PM PST 24 66310956036 ps
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