| T1187 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.3272125799 |
|
|
Feb 18 04:16:58 PM PST 24 |
Feb 18 04:22:27 PM PST 24 |
2486861016 ps |
| T1188 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2535617174 |
|
|
Feb 18 04:00:02 PM PST 24 |
Feb 18 04:31:45 PM PST 24 |
15133464554 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.114244871 |
|
|
Feb 18 04:16:19 PM PST 24 |
Feb 18 04:19:47 PM PST 24 |
2556518674 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.1952082637 |
|
|
Feb 18 04:00:48 PM PST 24 |
Feb 18 04:05:17 PM PST 24 |
2536729612 ps |
| T1191 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3089392944 |
|
|
Feb 18 04:17:30 PM PST 24 |
Feb 18 04:27:00 PM PST 24 |
7001930208 ps |
| T1192 |
/workspace/coverage/default/0.chip_sw_example_rom.1387122398 |
|
|
Feb 18 03:51:54 PM PST 24 |
Feb 18 03:53:57 PM PST 24 |
2859745672 ps |
| T285 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2934720499 |
|
|
Feb 18 03:56:46 PM PST 24 |
Feb 18 03:59:55 PM PST 24 |
2685527700 ps |
| T814 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2920059810 |
|
|
Feb 18 04:25:19 PM PST 24 |
Feb 18 04:34:36 PM PST 24 |
5900759790 ps |
| T1193 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2028425757 |
|
|
Feb 18 03:57:57 PM PST 24 |
Feb 18 04:03:16 PM PST 24 |
3318957260 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.1922286041 |
|
|
Feb 18 03:52:51 PM PST 24 |
Feb 18 04:39:50 PM PST 24 |
11567425216 ps |
| T52 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3618185025 |
|
|
Feb 18 03:57:40 PM PST 24 |
Feb 18 04:04:24 PM PST 24 |
3541398612 ps |
| T803 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.2211552262 |
|
|
Feb 18 04:21:18 PM PST 24 |
Feb 18 04:27:56 PM PST 24 |
3734210960 ps |
| T214 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.512575327 |
|
|
Feb 18 04:13:42 PM PST 24 |
Feb 18 05:00:13 PM PST 24 |
12142355790 ps |
| T1194 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1234848445 |
|
|
Feb 18 04:10:55 PM PST 24 |
Feb 18 04:24:58 PM PST 24 |
6492875600 ps |
| T1195 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1481282599 |
|
|
Feb 18 04:02:31 PM PST 24 |
Feb 18 04:07:27 PM PST 24 |
3189285004 ps |
| T1196 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1385765672 |
|
|
Feb 18 04:10:23 PM PST 24 |
Feb 18 04:16:16 PM PST 24 |
3131038536 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2308950134 |
|
|
Feb 18 04:14:08 PM PST 24 |
Feb 18 04:21:40 PM PST 24 |
3261988642 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2941164934 |
|
|
Feb 18 03:55:34 PM PST 24 |
Feb 18 03:57:43 PM PST 24 |
3077541248 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.3042980446 |
|
|
Feb 18 04:03:45 PM PST 24 |
Feb 18 04:32:04 PM PST 24 |
7989803080 ps |
| T1199 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2390231711 |
|
|
Feb 18 04:20:47 PM PST 24 |
Feb 18 04:31:58 PM PST 24 |
5133588640 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.120399891 |
|
|
Feb 18 04:13:32 PM PST 24 |
Feb 18 04:30:19 PM PST 24 |
6246148576 ps |
| T1201 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1214427235 |
|
|
Feb 18 04:02:10 PM PST 24 |
Feb 18 04:06:59 PM PST 24 |
2573611320 ps |
| T1202 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.2034952973 |
|
|
Feb 18 04:07:43 PM PST 24 |
Feb 18 04:12:12 PM PST 24 |
3076912714 ps |
| T1203 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.2949696349 |
|
|
Feb 18 03:53:02 PM PST 24 |
Feb 18 04:13:40 PM PST 24 |
8044631424 ps |
| T823 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.2245276835 |
|
|
Feb 18 04:20:10 PM PST 24 |
Feb 18 04:29:21 PM PST 24 |
4752556660 ps |
| T1204 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2258005794 |
|
|
Feb 18 04:09:26 PM PST 24 |
Feb 18 04:51:50 PM PST 24 |
14316093667 ps |
| T1205 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2886482479 |
|
|
Feb 18 04:01:34 PM PST 24 |
Feb 18 04:16:44 PM PST 24 |
5028375414 ps |
| T1206 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.4064088189 |
|
|
Feb 18 04:14:49 PM PST 24 |
Feb 18 04:24:30 PM PST 24 |
4206875186 ps |
| T1207 |
/workspace/coverage/default/2.chip_sw_aes_entropy.2359119281 |
|
|
Feb 18 04:12:39 PM PST 24 |
Feb 18 04:16:21 PM PST 24 |
2857391692 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3532185389 |
|
|
Feb 18 04:08:12 PM PST 24 |
Feb 18 04:19:01 PM PST 24 |
4290273608 ps |
| T791 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.1939675649 |
|
|
Feb 18 04:21:31 PM PST 24 |
Feb 18 04:29:23 PM PST 24 |
4997990928 ps |
| T1209 |
/workspace/coverage/default/0.chip_tap_straps_dev.4064105647 |
|
|
Feb 18 03:55:43 PM PST 24 |
Feb 18 04:22:57 PM PST 24 |
14187221920 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2585311044 |
|
|
Feb 18 03:59:55 PM PST 24 |
Feb 18 04:08:18 PM PST 24 |
4547015378 ps |
| T804 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2789277184 |
|
|
Feb 18 04:19:43 PM PST 24 |
Feb 18 04:32:56 PM PST 24 |
5388386740 ps |
| T778 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.2362091145 |
|
|
Feb 18 04:19:24 PM PST 24 |
Feb 18 04:29:50 PM PST 24 |
5847180616 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3339283759 |
|
|
Feb 18 04:05:24 PM PST 24 |
Feb 18 04:13:25 PM PST 24 |
5407246418 ps |
| T1212 |
/workspace/coverage/default/0.rom_e2e_static_critical.1549466914 |
|
|
Feb 18 04:00:31 PM PST 24 |
Feb 18 04:41:49 PM PST 24 |
10375680572 ps |
| T1213 |
/workspace/coverage/default/2.rom_e2e_static_critical.1245489349 |
|
|
Feb 18 04:19:45 PM PST 24 |
Feb 18 05:05:24 PM PST 24 |
10663748500 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1595590532 |
|
|
Feb 18 03:53:49 PM PST 24 |
Feb 18 04:03:07 PM PST 24 |
3671147225 ps |
| T792 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2754803640 |
|
|
Feb 18 04:23:43 PM PST 24 |
Feb 18 04:32:43 PM PST 24 |
4104904696 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.11691493 |
|
|
Feb 18 03:54:08 PM PST 24 |
Feb 18 04:04:55 PM PST 24 |
4468676520 ps |
| T76 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1598867163 |
|
|
Feb 18 03:52:43 PM PST 24 |
Feb 18 05:51:08 PM PST 24 |
31195522574 ps |
| T1216 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.441303178 |
|
|
Feb 18 03:59:41 PM PST 24 |
Feb 18 07:38:04 PM PST 24 |
78593375155 ps |
| T1217 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2954605262 |
|
|
Feb 18 03:56:55 PM PST 24 |
Feb 18 04:13:26 PM PST 24 |
5682780056 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3498466025 |
|
|
Feb 18 03:59:14 PM PST 24 |
Feb 18 04:12:24 PM PST 24 |
6166496754 ps |
| T1219 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.305780708 |
|
|
Feb 18 04:11:19 PM PST 24 |
Feb 18 04:43:40 PM PST 24 |
8887895480 ps |
| T1220 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.3587527103 |
|
|
Feb 18 04:20:50 PM PST 24 |
Feb 18 04:31:33 PM PST 24 |
8941796640 ps |
| T280 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2935426173 |
|
|
Feb 18 04:22:29 PM PST 24 |
Feb 18 04:28:45 PM PST 24 |
3963251128 ps |
| T1221 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.496572464 |
|
|
Feb 18 03:56:23 PM PST 24 |
Feb 18 04:08:03 PM PST 24 |
6338269900 ps |
| T1222 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2248324390 |
|
|
Feb 18 04:01:51 PM PST 24 |
Feb 18 04:31:15 PM PST 24 |
8975664386 ps |
| T1223 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.146035251 |
|
|
Feb 18 03:58:36 PM PST 24 |
Feb 18 04:18:03 PM PST 24 |
7734361702 ps |
| T116 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.1123142780 |
|
|
Feb 18 04:03:19 PM PST 24 |
Feb 18 04:12:19 PM PST 24 |
3831572686 ps |
| T1224 |
/workspace/coverage/default/1.chip_tap_straps_prod.1450855522 |
|
|
Feb 18 04:04:54 PM PST 24 |
Feb 18 04:07:31 PM PST 24 |
2523796470 ps |
| T245 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1124221213 |
|
|
Feb 18 03:54:49 PM PST 24 |
Feb 18 04:02:46 PM PST 24 |
4701646760 ps |
| T393 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.2238318716 |
|
|
Feb 18 04:14:13 PM PST 24 |
Feb 18 04:23:43 PM PST 24 |
7831591888 ps |
| T1225 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.233240362 |
|
|
Feb 18 03:52:08 PM PST 24 |
Feb 18 04:06:28 PM PST 24 |
5775005784 ps |
| T776 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.884266249 |
|
|
Feb 18 04:25:28 PM PST 24 |
Feb 18 04:33:18 PM PST 24 |
3363924164 ps |
| T1226 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2323929707 |
|
|
Feb 18 04:06:56 PM PST 24 |
Feb 18 04:12:20 PM PST 24 |
2696728957 ps |
| T1227 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.3660184450 |
|
|
Feb 18 04:08:53 PM PST 24 |
Feb 18 04:15:00 PM PST 24 |
3193234736 ps |
| T1228 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2738822322 |
|
|
Feb 18 04:04:26 PM PST 24 |
Feb 18 04:36:59 PM PST 24 |
8581508528 ps |
| T793 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.2541850782 |
|
|
Feb 18 04:23:27 PM PST 24 |
Feb 18 04:29:53 PM PST 24 |
3431602968 ps |
| T1229 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1938428324 |
|
|
Feb 18 04:00:37 PM PST 24 |
Feb 18 04:33:05 PM PST 24 |
7660379459 ps |
| T1230 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1423961328 |
|
|
Feb 18 03:59:28 PM PST 24 |
Feb 18 04:17:40 PM PST 24 |
12306137503 ps |
| T822 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.3255612765 |
|
|
Feb 18 04:22:37 PM PST 24 |
Feb 18 04:29:15 PM PST 24 |
3560845400 ps |
| T1231 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2699805688 |
|
|
Feb 18 03:53:06 PM PST 24 |
Feb 18 04:02:36 PM PST 24 |
5501370105 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.489063632 |
|
|
Feb 18 04:10:26 PM PST 24 |
Feb 18 04:27:55 PM PST 24 |
5182622016 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2447082192 |
|
|
Feb 18 03:53:04 PM PST 24 |
Feb 18 03:58:21 PM PST 24 |
2976732029 ps |
| T779 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.3743761065 |
|
|
Feb 18 04:21:58 PM PST 24 |
Feb 18 04:27:51 PM PST 24 |
3382412076 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3517501481 |
|
|
Feb 18 03:55:50 PM PST 24 |
Feb 18 04:02:55 PM PST 24 |
3011816072 ps |
| T210 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.212637090 |
|
|
Feb 18 04:13:30 PM PST 24 |
Feb 18 04:23:02 PM PST 24 |
4942033336 ps |
| T1234 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3379420164 |
|
|
Feb 18 03:56:53 PM PST 24 |
Feb 18 04:17:20 PM PST 24 |
6437912682 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1893655342 |
|
|
Feb 18 03:52:57 PM PST 24 |
Feb 18 03:55:25 PM PST 24 |
3291410967 ps |
| T817 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.3531905236 |
|
|
Feb 18 04:22:57 PM PST 24 |
Feb 18 04:34:40 PM PST 24 |
5738366576 ps |
| T1236 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.2643997745 |
|
|
Feb 18 04:01:39 PM PST 24 |
Feb 18 04:36:43 PM PST 24 |
8629824660 ps |
| T1237 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.3609884770 |
|
|
Feb 18 04:09:41 PM PST 24 |
Feb 18 04:27:05 PM PST 24 |
5030305919 ps |
| T801 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.803970503 |
|
|
Feb 18 04:23:49 PM PST 24 |
Feb 18 04:29:38 PM PST 24 |
3510705892 ps |
| T1238 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2764448296 |
|
|
Feb 18 03:57:29 PM PST 24 |
Feb 18 04:08:53 PM PST 24 |
6169136836 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.1917554778 |
|
|
Feb 18 04:09:52 PM PST 24 |
Feb 18 04:39:12 PM PST 24 |
10863415936 ps |
| T1240 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3324691018 |
|
|
Feb 18 04:10:00 PM PST 24 |
Feb 18 04:11:45 PM PST 24 |
2038222258 ps |
| T1241 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2326409981 |
|
|
Feb 18 03:57:06 PM PST 24 |
Feb 18 04:37:45 PM PST 24 |
11147062200 ps |
| T1242 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.3167178491 |
|
|
Feb 18 04:03:29 PM PST 24 |
Feb 18 04:08:16 PM PST 24 |
3677445781 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.395143806 |
|
|
Feb 18 04:00:09 PM PST 24 |
Feb 18 04:02:10 PM PST 24 |
2463056524 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3983633831 |
|
|
Feb 18 04:15:46 PM PST 24 |
Feb 18 04:19:34 PM PST 24 |
2351911160 ps |
| T58 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2205178700 |
|
|
Feb 18 04:09:37 PM PST 24 |
Feb 18 04:15:22 PM PST 24 |
5568898744 ps |
| T1243 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.438654663 |
|
|
Feb 18 04:13:43 PM PST 24 |
Feb 18 04:24:08 PM PST 24 |
5251198894 ps |
| T219 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.4016058941 |
|
|
Feb 18 03:59:01 PM PST 24 |
Feb 18 05:19:22 PM PST 24 |
44516081433 ps |
| T161 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1492016117 |
|
|
Feb 18 03:54:57 PM PST 24 |
Feb 18 04:03:43 PM PST 24 |
5202607152 ps |
| T1244 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.1178565005 |
|
|
Feb 18 03:54:25 PM PST 24 |
Feb 18 04:02:27 PM PST 24 |
4699412360 ps |
| T1245 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2369597791 |
|
|
Feb 18 04:19:54 PM PST 24 |
Feb 18 04:46:23 PM PST 24 |
8101449067 ps |
| T37 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.3765062301 |
|
|
Feb 18 03:59:10 PM PST 24 |
Feb 18 04:03:46 PM PST 24 |
2208766280 ps |
| T827 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.3522709377 |
|
|
Feb 18 04:20:20 PM PST 24 |
Feb 18 04:26:55 PM PST 24 |
3900889084 ps |
| T1246 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2837760115 |
|
|
Feb 18 04:00:10 PM PST 24 |
Feb 18 04:46:04 PM PST 24 |
9711820510 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.169863847 |
|
|
Feb 18 03:55:30 PM PST 24 |
Feb 18 04:07:37 PM PST 24 |
3699924680 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2229324334 |
|
|
Feb 18 04:00:50 PM PST 24 |
Feb 18 05:00:21 PM PST 24 |
20039793866 ps |
| T331 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2821260462 |
|
|
Feb 18 03:54:18 PM PST 24 |
Feb 18 04:02:46 PM PST 24 |
4476776168 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.770655294 |
|
|
Feb 18 03:59:41 PM PST 24 |
Feb 18 04:16:42 PM PST 24 |
5694337272 ps |
| T1249 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.2631528370 |
|
|
Feb 18 04:17:11 PM PST 24 |
Feb 18 04:28:52 PM PST 24 |
4723750072 ps |
| T1250 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.388353856 |
|
|
Feb 18 03:54:14 PM PST 24 |
Feb 18 04:58:47 PM PST 24 |
19260632472 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.878357993 |
|
|
Feb 18 04:15:42 PM PST 24 |
Feb 18 04:19:18 PM PST 24 |
2346093070 ps |
| T1252 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.826792952 |
|
|
Feb 18 03:53:35 PM PST 24 |
Feb 18 03:57:11 PM PST 24 |
3251222464 ps |
| T1253 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3477785003 |
|
|
Feb 18 04:09:52 PM PST 24 |
Feb 18 04:12:51 PM PST 24 |
3494367795 ps |
| T494 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2804269756 |
|
|
Feb 18 04:02:02 PM PST 24 |
Feb 18 04:17:43 PM PST 24 |
4904532480 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.357765612 |
|
|
Feb 18 04:00:30 PM PST 24 |
Feb 18 04:08:47 PM PST 24 |
5077659016 ps |
| T1255 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.2044405688 |
|
|
Feb 18 04:17:33 PM PST 24 |
Feb 18 04:29:05 PM PST 24 |
5878048740 ps |
| T1256 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.1801742359 |
|
|
Feb 18 04:09:04 PM PST 24 |
Feb 18 04:19:07 PM PST 24 |
4585200048 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.392231451 |
|
|
Feb 18 03:58:12 PM PST 24 |
Feb 18 04:19:03 PM PST 24 |
5497642359 ps |
| T1258 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.4157302137 |
|
|
Feb 18 04:18:00 PM PST 24 |
Feb 18 04:31:26 PM PST 24 |
4995659552 ps |
| T1259 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.2499726118 |
|
|
Feb 18 04:16:13 PM PST 24 |
Feb 18 04:20:44 PM PST 24 |
2741323096 ps |
| T761 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1739859516 |
|
|
Feb 18 04:24:55 PM PST 24 |
Feb 18 04:30:19 PM PST 24 |
3249293150 ps |
| T828 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.3004841171 |
|
|
Feb 18 04:25:50 PM PST 24 |
Feb 18 04:34:16 PM PST 24 |
4147778024 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1057416825 |
|
|
Feb 18 04:03:59 PM PST 24 |
Feb 18 04:15:54 PM PST 24 |
3997578696 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1266643678 |
|
|
Feb 18 03:56:16 PM PST 24 |
Feb 18 04:58:43 PM PST 24 |
15190572728 ps |
| T350 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1229759031 |
|
|
Feb 18 04:05:11 PM PST 24 |
Feb 18 04:14:00 PM PST 24 |
6552832390 ps |
| T820 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.3683115027 |
|
|
Feb 18 04:22:42 PM PST 24 |
Feb 18 04:28:46 PM PST 24 |
3766924044 ps |
| T89 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1048760066 |
|
|
Feb 18 04:22:20 PM PST 24 |
Feb 18 04:29:01 PM PST 24 |
4269803780 ps |
| T768 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2460371439 |
|
|
Feb 18 04:23:19 PM PST 24 |
Feb 18 04:32:00 PM PST 24 |
4247371216 ps |
| T1262 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.340107382 |
|
|
Feb 18 04:17:01 PM PST 24 |
Feb 18 04:24:43 PM PST 24 |
5975629737 ps |
| T1263 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.742124229 |
|
|
Feb 18 04:16:43 PM PST 24 |
Feb 18 04:22:41 PM PST 24 |
2618246556 ps |
| T1264 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2075286941 |
|
|
Feb 18 04:10:07 PM PST 24 |
Feb 18 04:59:14 PM PST 24 |
32985267920 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2516142332 |
|
|
Feb 18 03:58:16 PM PST 24 |
Feb 18 04:18:44 PM PST 24 |
8329386770 ps |
| T1266 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.4230876719 |
|
|
Feb 18 04:10:31 PM PST 24 |
Feb 18 04:22:30 PM PST 24 |
4894537363 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1476838793 |
|
|
Feb 18 04:16:21 PM PST 24 |
Feb 18 04:22:05 PM PST 24 |
2817516540 ps |
| T798 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2831693890 |
|
|
Feb 18 04:25:49 PM PST 24 |
Feb 18 04:32:01 PM PST 24 |
3971181728 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.2521058696 |
|
|
Feb 18 04:00:32 PM PST 24 |
Feb 18 04:04:25 PM PST 24 |
2855199080 ps |
| T1269 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1070853646 |
|
|
Feb 18 03:54:46 PM PST 24 |
Feb 18 04:00:59 PM PST 24 |
3369016896 ps |
| T1270 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.1140166636 |
|
|
Feb 18 04:12:38 PM PST 24 |
Feb 18 04:17:21 PM PST 24 |
2878764284 ps |
| T1271 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1947287469 |
|
|
Feb 18 04:12:52 PM PST 24 |
Feb 18 04:27:16 PM PST 24 |
7257024658 ps |
| T1272 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3036958857 |
|
|
Feb 18 04:18:58 PM PST 24 |
Feb 18 04:27:33 PM PST 24 |
5849260399 ps |
| T1273 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3792680875 |
|
|
Feb 18 04:00:50 PM PST 24 |
Feb 18 04:31:45 PM PST 24 |
8169893682 ps |
| T246 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2304767860 |
|
|
Feb 18 04:01:54 PM PST 24 |
Feb 18 04:09:15 PM PST 24 |
4334826022 ps |
| T247 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.4078190459 |
|
|
Feb 18 04:22:26 PM PST 24 |
Feb 18 04:33:18 PM PST 24 |
5812360056 ps |
| T1274 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1949608835 |
|
|
Feb 18 04:10:32 PM PST 24 |
Feb 18 04:15:56 PM PST 24 |
2911106368 ps |
| T1275 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3268066030 |
|
|
Feb 18 03:52:30 PM PST 24 |
Feb 18 03:57:21 PM PST 24 |
4386258348 ps |
| T1276 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2187425757 |
|
|
Feb 18 04:09:16 PM PST 24 |
Feb 18 04:13:03 PM PST 24 |
2151327342 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1266503404 |
|
|
Feb 18 03:58:09 PM PST 24 |
Feb 18 04:02:20 PM PST 24 |
3385474184 ps |
| T1278 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.33961765 |
|
|
Feb 18 04:05:21 PM PST 24 |
Feb 18 04:09:23 PM PST 24 |
3219924708 ps |
| T1279 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.813921160 |
|
|
Feb 18 04:23:31 PM PST 24 |
Feb 18 04:28:35 PM PST 24 |
3587203320 ps |
| T1280 |
/workspace/coverage/default/2.rom_e2e_smoke.142008650 |
|
|
Feb 18 04:17:07 PM PST 24 |
Feb 18 04:43:58 PM PST 24 |
8617549108 ps |
| T673 |
/workspace/coverage/default/4.chip_tap_straps_dev.979838581 |
|
|
Feb 18 04:17:40 PM PST 24 |
Feb 18 04:34:32 PM PST 24 |
12595162219 ps |
| T189 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.998422124 |
|
|
Feb 18 04:13:35 PM PST 24 |
Feb 18 04:21:38 PM PST 24 |
3605127140 ps |
| T1281 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3425244802 |
|
|
Feb 18 04:14:06 PM PST 24 |
Feb 18 04:24:11 PM PST 24 |
3810822750 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.3851261760 |
|
|
Feb 18 04:03:58 PM PST 24 |
Feb 18 04:15:01 PM PST 24 |
4642474216 ps |
| T1283 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3091139961 |
|
|
Feb 18 04:11:03 PM PST 24 |
Feb 18 04:18:04 PM PST 24 |
4686097138 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2445432144 |
|
|
Feb 18 04:14:14 PM PST 24 |
Feb 18 04:24:12 PM PST 24 |
4979372100 ps |
| T497 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.3867281984 |
|
|
Feb 18 03:57:24 PM PST 24 |
Feb 18 04:07:25 PM PST 24 |
4791134393 ps |
| T782 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.466550858 |
|
|
Feb 18 04:18:54 PM PST 24 |
Feb 18 04:24:44 PM PST 24 |
4039240810 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.771991967 |
|
|
Feb 18 03:57:21 PM PST 24 |
Feb 18 04:04:17 PM PST 24 |
4070438632 ps |
| T818 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.2949900496 |
|
|
Feb 18 04:22:08 PM PST 24 |
Feb 18 04:32:09 PM PST 24 |
5387894664 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.1859856912 |
|
|
Feb 18 03:53:26 PM PST 24 |
Feb 18 03:59:53 PM PST 24 |
3607747304 ps |
| T1287 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.613042156 |
|
|
Feb 18 04:01:34 PM PST 24 |
Feb 18 04:36:58 PM PST 24 |
8463165701 ps |
| T1288 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2474290874 |
|
|
Feb 18 03:54:29 PM PST 24 |
Feb 18 04:24:03 PM PST 24 |
7398986776 ps |
| T1289 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.144699507 |
|
|
Feb 18 04:03:19 PM PST 24 |
Feb 18 04:53:17 PM PST 24 |
12467413040 ps |
| T825 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.3588677987 |
|
|
Feb 18 04:23:02 PM PST 24 |
Feb 18 04:28:37 PM PST 24 |
3279342120 ps |
| T1290 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1143747117 |
|
|
Feb 18 04:11:46 PM PST 24 |
Feb 18 04:19:58 PM PST 24 |
4319400590 ps |
| T784 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1362711313 |
|
|
Feb 18 04:22:07 PM PST 24 |
Feb 18 04:32:35 PM PST 24 |
4687052084 ps |
| T1291 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.1548636699 |
|
|
Feb 18 04:19:39 PM PST 24 |
Feb 18 04:50:59 PM PST 24 |
8965066443 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.288710844 |
|
|
Feb 18 04:03:55 PM PST 24 |
Feb 18 04:24:23 PM PST 24 |
5341859600 ps |
| T357 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2558748324 |
|
|
Feb 18 04:19:11 PM PST 24 |
Feb 18 04:26:57 PM PST 24 |
5715029640 ps |
| T1293 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2867657365 |
|
|
Feb 18 03:54:46 PM PST 24 |
Feb 18 04:22:39 PM PST 24 |
12452064496 ps |
| T1294 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1040196715 |
|
|
Feb 18 04:03:21 PM PST 24 |
Feb 18 04:11:06 PM PST 24 |
3838863600 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_example_flash.3884131583 |
|
|
Feb 18 03:56:54 PM PST 24 |
Feb 18 04:00:43 PM PST 24 |
2235924784 ps |
| T1296 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.135838381 |
|
|
Feb 18 04:20:31 PM PST 24 |
Feb 18 05:25:12 PM PST 24 |
23046947690 ps |
| T1297 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2185381507 |
|
|
Feb 18 03:56:56 PM PST 24 |
Feb 18 04:01:33 PM PST 24 |
3113791744 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3294237896 |
|
|
Feb 18 04:19:35 PM PST 24 |
Feb 18 04:23:38 PM PST 24 |
2351781509 ps |
| T1299 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.2137250797 |
|
|
Feb 18 03:56:37 PM PST 24 |
Feb 18 04:01:24 PM PST 24 |
3555434856 ps |
| T726 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3237962087 |
|
|
Feb 18 04:24:36 PM PST 24 |
Feb 18 04:35:47 PM PST 24 |
5146809854 ps |
| T765 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1086585105 |
|
|
Feb 18 04:23:31 PM PST 24 |
Feb 18 04:30:03 PM PST 24 |
4107719604 ps |
| T1300 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.1287415166 |
|
|
Feb 18 04:01:57 PM PST 24 |
Feb 18 04:39:58 PM PST 24 |
8589022136 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2768972090 |
|
|
Feb 18 04:09:40 PM PST 24 |
Feb 18 04:13:31 PM PST 24 |
3157553576 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.2544756140 |
|
|
Feb 18 03:54:48 PM PST 24 |
Feb 18 03:58:50 PM PST 24 |
2970448146 ps |
| T703 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.3378972230 |
|
|
Feb 18 04:05:59 PM PST 24 |
Feb 18 04:11:24 PM PST 24 |
4688560664 ps |
| T1303 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1410482813 |
|
|
Feb 18 04:21:57 PM PST 24 |
Feb 18 04:28:33 PM PST 24 |
4362617680 ps |
| T1304 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2543541636 |
|
|
Feb 18 04:02:42 PM PST 24 |
Feb 18 04:08:04 PM PST 24 |
2721677828 ps |
| T1305 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1023637599 |
|
|
Feb 18 04:10:23 PM PST 24 |
Feb 18 04:14:17 PM PST 24 |
2921467832 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2011895121 |
|
|
Feb 18 03:58:50 PM PST 24 |
Feb 18 04:09:07 PM PST 24 |
7401341896 ps |
| T351 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.584394718 |
|
|
Feb 18 04:19:25 PM PST 24 |
Feb 18 04:31:20 PM PST 24 |
8954919208 ps |
| T1307 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.2862815699 |
|
|
Feb 18 03:52:44 PM PST 24 |
Feb 18 05:18:38 PM PST 24 |
47226097140 ps |
| T320 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.837394714 |
|
|
Feb 18 04:08:41 PM PST 24 |
Feb 18 04:22:10 PM PST 24 |
5020832290 ps |
| T1308 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.3544555188 |
|
|
Feb 18 04:08:21 PM PST 24 |
Feb 18 07:22:26 PM PST 24 |
64299131658 ps |
| T236 |
/workspace/coverage/default/1.chip_jtag_mem_access.2695674602 |
|
|
Feb 18 03:57:16 PM PST 24 |
Feb 18 04:20:04 PM PST 24 |
12968233160 ps |
| T1309 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3542609985 |
|
|
Feb 18 03:57:50 PM PST 24 |
Feb 18 04:03:13 PM PST 24 |
5084536592 ps |
| T281 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1966064747 |
|
|
Feb 18 04:20:39 PM PST 24 |
Feb 18 04:29:07 PM PST 24 |
5030841944 ps |
| T1310 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2262397638 |
|
|
Feb 18 04:13:53 PM PST 24 |
Feb 18 05:10:53 PM PST 24 |
14928808664 ps |
| T1311 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.1047944575 |
|
|
Feb 18 04:13:38 PM PST 24 |
Feb 18 04:18:27 PM PST 24 |
2446066802 ps |
| T1312 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.4091180114 |
|
|
Feb 18 04:00:13 PM PST 24 |
Feb 18 04:22:47 PM PST 24 |
8722268878 ps |
| T1313 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4085510469 |
|
|
Feb 18 04:01:21 PM PST 24 |
Feb 18 04:26:52 PM PST 24 |
12457249354 ps |
| T1314 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.844891427 |
|
|
Feb 18 03:53:54 PM PST 24 |
Feb 18 04:10:35 PM PST 24 |
5207154712 ps |
| T1315 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2230891764 |
|
|
Feb 18 04:09:34 PM PST 24 |
Feb 18 04:27:29 PM PST 24 |
13191932881 ps |
| T1316 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.1859543570 |
|
|
Feb 18 04:16:59 PM PST 24 |
Feb 18 04:33:27 PM PST 24 |
6058721572 ps |
| T1317 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.432309991 |
|
|
Feb 18 04:11:46 PM PST 24 |
Feb 18 04:38:46 PM PST 24 |
6863607570 ps |
| T1318 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.969858405 |
|
|
Feb 18 04:01:13 PM PST 24 |
Feb 18 04:13:57 PM PST 24 |
7532544945 ps |
| T707 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.4243054696 |
|
|
Feb 18 04:09:14 PM PST 24 |
Feb 18 04:28:06 PM PST 24 |
5667587680 ps |
| T334 |
/workspace/coverage/default/2.chip_sival_flash_info_access.3806281259 |
|
|
Feb 18 04:09:14 PM PST 24 |
Feb 18 04:16:58 PM PST 24 |
3593255196 ps |
| T1319 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2661657433 |
|
|
Feb 18 04:04:54 PM PST 24 |
Feb 18 04:24:29 PM PST 24 |
17623696152 ps |
| T785 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.2130458136 |
|
|
Feb 18 04:22:51 PM PST 24 |
Feb 18 04:28:34 PM PST 24 |
4043884176 ps |
| T260 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1049315703 |
|
|
Feb 18 04:17:05 PM PST 24 |
Feb 18 04:29:16 PM PST 24 |
5762331116 ps |
| T77 |
/workspace/coverage/cover_reg_top/85.xbar_error_random.3840723014 |
|
|
Feb 18 03:43:11 PM PST 24 |
Feb 18 03:43:37 PM PST 24 |
291418710 ps |
| T78 |
/workspace/coverage/cover_reg_top/88.xbar_smoke_slow_rsp.243045240 |
|
|
Feb 18 03:43:32 PM PST 24 |
Feb 18 03:45:09 PM PST 24 |
5516754840 ps |
| T79 |
/workspace/coverage/cover_reg_top/45.xbar_smoke.3535065145 |
|
|
Feb 18 03:36:14 PM PST 24 |
Feb 18 03:36:25 PM PST 24 |
197752871 ps |
| T81 |
/workspace/coverage/cover_reg_top/2.chip_tl_errors.402050833 |
|
|
Feb 18 03:27:59 PM PST 24 |
Feb 18 03:31:05 PM PST 24 |
3324405210 ps |
| T112 |
/workspace/coverage/cover_reg_top/26.chip_tl_errors.1276648331 |
|
|
Feb 18 03:32:50 PM PST 24 |
Feb 18 03:38:21 PM PST 24 |
3983807796 ps |
| T113 |
/workspace/coverage/cover_reg_top/57.xbar_access_same_device_slow_rsp.118127060 |
|
|
Feb 18 03:38:32 PM PST 24 |
Feb 18 03:47:33 PM PST 24 |
32282289779 ps |
| T82 |
/workspace/coverage/cover_reg_top/60.xbar_smoke_zero_delays.1554524007 |
|
|
Feb 18 03:39:15 PM PST 24 |
Feb 18 03:39:23 PM PST 24 |
46854535 ps |
| T156 |
/workspace/coverage/cover_reg_top/4.xbar_random_zero_delays.1098681639 |
|
|
Feb 18 03:28:31 PM PST 24 |
Feb 18 03:28:56 PM PST 24 |
268060576 ps |
| T404 |
/workspace/coverage/cover_reg_top/63.xbar_smoke.2052477706 |
|
|
Feb 18 03:39:20 PM PST 24 |
Feb 18 03:39:28 PM PST 24 |
165709297 ps |
| T501 |
/workspace/coverage/cover_reg_top/31.xbar_stress_all.3450467826 |
|
|
Feb 18 03:33:50 PM PST 24 |
Feb 18 03:34:02 PM PST 24 |
226100913 ps |
| T235 |
/workspace/coverage/cover_reg_top/37.xbar_random_zero_delays.519917438 |
|
|
Feb 18 03:34:48 PM PST 24 |
Feb 18 03:35:15 PM PST 24 |
277880427 ps |
| T411 |
/workspace/coverage/cover_reg_top/34.xbar_error_and_unmapped_addr.4002108040 |
|
|
Feb 18 03:34:23 PM PST 24 |
Feb 18 03:34:31 PM PST 24 |
33601766 ps |
| T474 |
/workspace/coverage/cover_reg_top/47.xbar_access_same_device.2435949648 |
|
|
Feb 18 03:36:43 PM PST 24 |
Feb 18 03:37:59 PM PST 24 |
1043931391 ps |
| T502 |
/workspace/coverage/cover_reg_top/10.xbar_smoke_large_delays.3045782440 |
|
|
Feb 18 03:28:55 PM PST 24 |
Feb 18 03:30:24 PM PST 24 |
7995411281 ps |
| T412 |
/workspace/coverage/cover_reg_top/96.xbar_error_and_unmapped_addr.40690586 |
|
|
Feb 18 03:45:07 PM PST 24 |
Feb 18 03:45:14 PM PST 24 |
74571131 ps |
| T504 |
/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.3719566585 |
|
|
Feb 18 03:36:07 PM PST 24 |
Feb 18 03:37:09 PM PST 24 |
3600154157 ps |
| T391 |
/workspace/coverage/cover_reg_top/88.xbar_access_same_device_slow_rsp.3349142328 |
|
|
Feb 18 03:43:35 PM PST 24 |
Feb 18 04:32:02 PM PST 24 |
149120612567 ps |
| T443 |
/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.1316601418 |
|
|
Feb 18 03:34:38 PM PST 24 |
Feb 18 03:37:59 PM PST 24 |
3068251768 ps |
| T421 |
/workspace/coverage/cover_reg_top/51.xbar_random_slow_rsp.1706763590 |
|
|
Feb 18 03:37:31 PM PST 24 |
Feb 18 03:58:38 PM PST 24 |
71693705402 ps |
| T604 |
/workspace/coverage/cover_reg_top/27.xbar_smoke_slow_rsp.3228317474 |
|
|
Feb 18 03:32:55 PM PST 24 |
Feb 18 03:34:07 PM PST 24 |
4124666519 ps |
| T439 |
/workspace/coverage/cover_reg_top/56.xbar_unmapped_addr.1832890844 |
|
|
Feb 18 03:38:28 PM PST 24 |
Feb 18 03:39:23 PM PST 24 |
1381960153 ps |
| T499 |
/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_error.2029991635 |
|
|
Feb 18 03:34:19 PM PST 24 |
Feb 18 03:37:32 PM PST 24 |
6149315646 ps |
| T503 |
/workspace/coverage/cover_reg_top/58.xbar_random.2122095017 |
|
|
Feb 18 03:38:34 PM PST 24 |
Feb 18 03:39:55 PM PST 24 |
2143154256 ps |
| T430 |
/workspace/coverage/cover_reg_top/15.xbar_random.1465435242 |
|
|
Feb 18 03:30:15 PM PST 24 |
Feb 18 03:30:59 PM PST 24 |
523717472 ps |
| T500 |
/workspace/coverage/cover_reg_top/89.xbar_random_zero_delays.4110337071 |
|
|
Feb 18 03:43:58 PM PST 24 |
Feb 18 03:44:48 PM PST 24 |
565869904 ps |
| T602 |
/workspace/coverage/cover_reg_top/55.xbar_random_slow_rsp.3314148939 |
|
|
Feb 18 03:38:08 PM PST 24 |
Feb 18 03:40:00 PM PST 24 |
6089869203 ps |
| T841 |
/workspace/coverage/cover_reg_top/32.xbar_random_slow_rsp.2366809647 |
|
|
Feb 18 03:33:50 PM PST 24 |
Feb 18 03:34:53 PM PST 24 |
3676837946 ps |
| T398 |
/workspace/coverage/cover_reg_top/83.xbar_stress_all.2511365880 |
|
|
Feb 18 03:42:51 PM PST 24 |
Feb 18 03:46:05 PM PST 24 |
2350652533 ps |
| T612 |
/workspace/coverage/cover_reg_top/73.xbar_smoke.1480338458 |
|
|
Feb 18 03:41:10 PM PST 24 |
Feb 18 03:41:21 PM PST 24 |
240433849 ps |
| T507 |
/workspace/coverage/cover_reg_top/25.xbar_error_random.3855398014 |
|
|
Feb 18 03:32:33 PM PST 24 |
Feb 18 03:33:07 PM PST 24 |
383360973 ps |
| T549 |
/workspace/coverage/cover_reg_top/79.xbar_smoke_zero_delays.1665015620 |
|
|
Feb 18 03:42:09 PM PST 24 |
Feb 18 03:42:17 PM PST 24 |
41157638 ps |
| T525 |
/workspace/coverage/cover_reg_top/24.xbar_stress_all_with_rand_reset.2094459043 |
|
|
Feb 18 03:32:17 PM PST 24 |
Feb 18 03:34:11 PM PST 24 |
1293339929 ps |
| T475 |
/workspace/coverage/cover_reg_top/71.xbar_random_zero_delays.2983822743 |
|
|
Feb 18 03:40:51 PM PST 24 |
Feb 18 03:41:45 PM PST 24 |
554390115 ps |
| T392 |
/workspace/coverage/cover_reg_top/3.xbar_stress_all.749387833 |
|
|
Feb 18 03:28:19 PM PST 24 |
Feb 18 03:33:44 PM PST 24 |
9645641768 ps |
| T878 |
/workspace/coverage/cover_reg_top/95.xbar_access_same_device.3074333562 |
|
|
Feb 18 03:44:43 PM PST 24 |
Feb 18 03:44:55 PM PST 24 |
96874245 ps |
| T543 |
/workspace/coverage/cover_reg_top/60.xbar_unmapped_addr.2978198351 |
|
|
Feb 18 03:39:14 PM PST 24 |
Feb 18 03:39:39 PM PST 24 |
202407617 ps |
| T506 |
/workspace/coverage/cover_reg_top/79.xbar_error_random.3767309572 |
|
|
Feb 18 03:42:25 PM PST 24 |
Feb 18 03:43:48 PM PST 24 |
2286156586 ps |
| T844 |
/workspace/coverage/cover_reg_top/55.xbar_error_and_unmapped_addr.3121709211 |
|
|
Feb 18 03:38:11 PM PST 24 |
Feb 18 03:38:19 PM PST 24 |
63889230 ps |
| T505 |
/workspace/coverage/cover_reg_top/36.xbar_stress_all_with_reset_error.766051059 |
|
|
Feb 18 03:34:45 PM PST 24 |
Feb 18 03:41:20 PM PST 24 |
7151288715 ps |
| T1320 |
/workspace/coverage/cover_reg_top/21.xbar_smoke.1085207393 |
|
|
Feb 18 03:31:33 PM PST 24 |
Feb 18 03:31:42 PM PST 24 |
177618526 ps |
| T1321 |
/workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.3665045737 |
|
|
Feb 18 03:32:30 PM PST 24 |
Feb 18 03:32:38 PM PST 24 |
39517651 ps |
| T689 |
/workspace/coverage/cover_reg_top/24.xbar_access_same_device_slow_rsp.1012413024 |
|
|
Feb 18 03:32:14 PM PST 24 |
Feb 18 03:48:35 PM PST 24 |
58422850211 ps |
| T1322 |
/workspace/coverage/cover_reg_top/3.xbar_smoke_zero_delays.1868075305 |
|
|
Feb 18 03:28:08 PM PST 24 |
Feb 18 03:28:18 PM PST 24 |
54130487 ps |
| T548 |
/workspace/coverage/cover_reg_top/33.xbar_smoke_large_delays.3670256466 |
|
|
Feb 18 03:33:57 PM PST 24 |
Feb 18 03:35:46 PM PST 24 |
9521275977 ps |
| T1323 |
/workspace/coverage/cover_reg_top/43.xbar_smoke_slow_rsp.3073535074 |
|
|
Feb 18 03:35:47 PM PST 24 |
Feb 18 03:37:20 PM PST 24 |
5312549371 ps |
| T422 |
/workspace/coverage/cover_reg_top/99.xbar_stress_all.3164782399 |
|
|
Feb 18 03:45:32 PM PST 24 |
Feb 18 03:53:20 PM PST 24 |
11974526093 ps |
| T395 |
/workspace/coverage/cover_reg_top/32.xbar_stress_all.2288507747 |
|
|
Feb 18 03:34:01 PM PST 24 |
Feb 18 03:39:48 PM PST 24 |
10972390768 ps |
| T880 |
/workspace/coverage/cover_reg_top/82.xbar_stress_all_with_reset_error.1617574233 |
|
|
Feb 18 03:42:46 PM PST 24 |
Feb 18 03:43:39 PM PST 24 |
102296964 ps |
| T641 |
/workspace/coverage/cover_reg_top/55.xbar_smoke_slow_rsp.716739259 |
|
|
Feb 18 03:38:06 PM PST 24 |
Feb 18 03:39:39 PM PST 24 |
5575459426 ps |
| T1324 |
/workspace/coverage/cover_reg_top/20.xbar_smoke_zero_delays.3568665365 |
|
|
Feb 18 03:31:23 PM PST 24 |
Feb 18 03:31:31 PM PST 24 |
38333252 ps |
| T864 |
/workspace/coverage/cover_reg_top/57.xbar_access_same_device.3558445784 |
|
|
Feb 18 03:38:34 PM PST 24 |
Feb 18 03:38:44 PM PST 24 |
104887656 ps |
| T417 |
/workspace/coverage/cover_reg_top/62.xbar_stress_all.1645210813 |
|
|
Feb 18 03:39:22 PM PST 24 |
Feb 18 03:46:26 PM PST 24 |
11768088882 ps |
| T399 |
/workspace/coverage/cover_reg_top/22.xbar_stress_all.466190668 |
|
|
Feb 18 03:32:02 PM PST 24 |
Feb 18 03:39:45 PM PST 24 |
12996816340 ps |
| T659 |
/workspace/coverage/cover_reg_top/4.xbar_error_random.4020326527 |
|
|
Feb 18 03:28:41 PM PST 24 |
Feb 18 03:30:12 PM PST 24 |
2417074026 ps |