| T921 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.475649374 |
|
|
Feb 29 03:30:59 PM PST 24 |
Feb 29 04:22:27 PM PST 24 |
22857796748 ps |
| T235 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3068742652 |
|
|
Feb 29 03:43:55 PM PST 24 |
Feb 29 03:49:08 PM PST 24 |
3204166640 ps |
| T800 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.3218488688 |
|
|
Feb 29 04:12:58 PM PST 24 |
Feb 29 04:20:22 PM PST 24 |
3918735280 ps |
| T157 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.938387203 |
|
|
Feb 29 03:44:34 PM PST 24 |
Feb 29 03:56:46 PM PST 24 |
5197715244 ps |
| T109 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.28632577 |
|
|
Feb 29 03:58:50 PM PST 24 |
Feb 29 04:29:11 PM PST 24 |
8549156640 ps |
| T922 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4250432168 |
|
|
Feb 29 03:45:41 PM PST 24 |
Feb 29 04:05:24 PM PST 24 |
7740121781 ps |
| T923 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.4091021109 |
|
|
Feb 29 03:41:10 PM PST 24 |
Feb 29 03:46:04 PM PST 24 |
3119530712 ps |
| T749 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2647340393 |
|
|
Feb 29 03:41:56 PM PST 24 |
Feb 29 03:45:44 PM PST 24 |
3159269766 ps |
| T314 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.1464505207 |
|
|
Feb 29 03:41:13 PM PST 24 |
Feb 29 04:00:43 PM PST 24 |
8800836687 ps |
| T150 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.676738518 |
|
|
Feb 29 03:54:19 PM PST 24 |
Feb 29 04:10:02 PM PST 24 |
4934392995 ps |
| T924 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1657669463 |
|
|
Feb 29 04:00:26 PM PST 24 |
Feb 29 04:09:30 PM PST 24 |
7099640616 ps |
| T286 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.3329581007 |
|
|
Feb 29 04:03:08 PM PST 24 |
Feb 29 04:45:42 PM PST 24 |
14193510280 ps |
| T228 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1849901665 |
|
|
Feb 29 03:28:33 PM PST 24 |
Feb 29 03:59:34 PM PST 24 |
12252552210 ps |
| T221 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2142884674 |
|
|
Feb 29 03:29:16 PM PST 24 |
Feb 29 03:37:26 PM PST 24 |
4813799500 ps |
| T158 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3236342204 |
|
|
Feb 29 03:30:02 PM PST 24 |
Feb 29 03:43:19 PM PST 24 |
5349318560 ps |
| T169 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.2867731570 |
|
|
Feb 29 03:54:35 PM PST 24 |
Feb 29 03:58:57 PM PST 24 |
3267897464 ps |
| T925 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.767601939 |
|
|
Feb 29 03:37:08 PM PST 24 |
Feb 29 04:20:14 PM PST 24 |
8811616162 ps |
| T226 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.392487656 |
|
|
Feb 29 03:51:03 PM PST 24 |
Feb 29 04:01:33 PM PST 24 |
5010066020 ps |
| T746 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3083022139 |
|
|
Feb 29 03:28:59 PM PST 24 |
Feb 29 03:44:57 PM PST 24 |
8076964138 ps |
| T751 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.1272927380 |
|
|
Feb 29 03:27:33 PM PST 24 |
Feb 29 03:46:51 PM PST 24 |
7635837392 ps |
| T926 |
/workspace/coverage/default/0.chip_sw_aes_entropy.3115754972 |
|
|
Feb 29 03:30:25 PM PST 24 |
Feb 29 03:33:22 PM PST 24 |
2317643408 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.2479183202 |
|
|
Feb 29 03:50:22 PM PST 24 |
Feb 29 03:53:34 PM PST 24 |
3029757168 ps |
| T283 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2490148015 |
|
|
Feb 29 03:45:03 PM PST 24 |
Feb 29 03:56:34 PM PST 24 |
4293077432 ps |
| T260 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.1309671802 |
|
|
Feb 29 04:00:27 PM PST 24 |
Feb 29 04:13:01 PM PST 24 |
5781299880 ps |
| T927 |
/workspace/coverage/default/1.chip_sw_hmac_smoketest.1721545685 |
|
|
Feb 29 03:48:14 PM PST 24 |
Feb 29 03:55:19 PM PST 24 |
2861042692 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.290880107 |
|
|
Feb 29 03:27:33 PM PST 24 |
Feb 29 03:35:53 PM PST 24 |
4048987500 ps |
| T682 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2129507221 |
|
|
Feb 29 04:04:10 PM PST 24 |
Feb 29 04:10:54 PM PST 24 |
3981963360 ps |
| T110 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.268633147 |
|
|
Feb 29 03:46:07 PM PST 24 |
Feb 29 04:50:02 PM PST 24 |
24675513164 ps |
| T928 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2442072472 |
|
|
Feb 29 03:30:41 PM PST 24 |
Feb 29 03:46:32 PM PST 24 |
5718689608 ps |
| T929 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.2259745293 |
|
|
Feb 29 03:50:04 PM PST 24 |
Feb 29 04:07:32 PM PST 24 |
8975054908 ps |
| T930 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2981565889 |
|
|
Feb 29 03:41:03 PM PST 24 |
Feb 29 03:54:21 PM PST 24 |
5708038400 ps |
| T127 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2307336725 |
|
|
Feb 29 03:27:23 PM PST 24 |
Feb 29 03:30:05 PM PST 24 |
2291716462 ps |
| T64 |
/workspace/coverage/default/1.chip_tap_straps_rma.131344236 |
|
|
Feb 29 03:44:50 PM PST 24 |
Feb 29 03:48:29 PM PST 24 |
2734090413 ps |
| T931 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.3453536224 |
|
|
Feb 29 03:37:44 PM PST 24 |
Feb 29 04:19:35 PM PST 24 |
8617689592 ps |
| T932 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3461693031 |
|
|
Feb 29 03:59:21 PM PST 24 |
Feb 29 04:02:35 PM PST 24 |
2571718708 ps |
| T933 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2181918391 |
|
|
Feb 29 03:54:37 PM PST 24 |
Feb 29 04:00:15 PM PST 24 |
2824245704 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3364471945 |
|
|
Feb 29 03:52:33 PM PST 24 |
Feb 29 03:58:40 PM PST 24 |
6694900680 ps |
| T935 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1417306346 |
|
|
Feb 29 03:38:41 PM PST 24 |
Feb 29 04:18:26 PM PST 24 |
9197853344 ps |
| T19 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.417109474 |
|
|
Feb 29 03:52:17 PM PST 24 |
Feb 29 04:43:56 PM PST 24 |
20584554930 ps |
| T775 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.1205161227 |
|
|
Feb 29 04:01:51 PM PST 24 |
Feb 29 04:08:03 PM PST 24 |
3756803468 ps |
| T936 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.662609979 |
|
|
Feb 29 04:02:54 PM PST 24 |
Feb 29 05:19:56 PM PST 24 |
23388087418 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.957403207 |
|
|
Feb 29 03:29:27 PM PST 24 |
Feb 29 03:58:19 PM PST 24 |
7619860328 ps |
| T938 |
/workspace/coverage/default/2.chip_tap_straps_prod.3057944680 |
|
|
Feb 29 03:55:32 PM PST 24 |
Feb 29 03:58:31 PM PST 24 |
2861830974 ps |
| T939 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.3498626011 |
|
|
Feb 29 03:42:25 PM PST 24 |
Feb 29 03:57:50 PM PST 24 |
6375823144 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.3105176914 |
|
|
Feb 29 03:27:18 PM PST 24 |
Feb 29 03:32:51 PM PST 24 |
4919352402 ps |
| T941 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1452224176 |
|
|
Feb 29 03:27:22 PM PST 24 |
Feb 29 03:37:43 PM PST 24 |
4738036916 ps |
| T59 |
/workspace/coverage/default/2.chip_tap_straps_rma.732958603 |
|
|
Feb 29 03:56:33 PM PST 24 |
Feb 29 04:05:36 PM PST 24 |
4976274134 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3329625460 |
|
|
Feb 29 03:26:39 PM PST 24 |
Feb 29 03:32:37 PM PST 24 |
3523570649 ps |
| T651 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.458171678 |
|
|
Feb 29 03:57:03 PM PST 24 |
Feb 29 04:58:19 PM PST 24 |
25321209053 ps |
| T942 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.1732996418 |
|
|
Feb 29 04:00:03 PM PST 24 |
Feb 29 04:21:13 PM PST 24 |
6183178072 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.2684790980 |
|
|
Feb 29 03:56:19 PM PST 24 |
Feb 29 04:08:02 PM PST 24 |
4569874432 ps |
| T752 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.4136584194 |
|
|
Feb 29 03:53:38 PM PST 24 |
Feb 29 04:03:09 PM PST 24 |
4452497020 ps |
| T944 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3970220062 |
|
|
Feb 29 03:44:30 PM PST 24 |
Feb 29 03:51:03 PM PST 24 |
5464181540 ps |
| T945 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1302616106 |
|
|
Feb 29 03:51:10 PM PST 24 |
Feb 29 04:17:45 PM PST 24 |
8194178716 ps |
| T741 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3946944262 |
|
|
Feb 29 04:08:34 PM PST 24 |
Feb 29 04:19:48 PM PST 24 |
5227934208 ps |
| T946 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.1917994200 |
|
|
Feb 29 04:01:34 PM PST 24 |
Feb 29 04:10:58 PM PST 24 |
7494016369 ps |
| T947 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1153854775 |
|
|
Feb 29 03:55:36 PM PST 24 |
Feb 29 04:04:43 PM PST 24 |
3106625144 ps |
| T193 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2662554540 |
|
|
Feb 29 03:39:00 PM PST 24 |
Feb 29 03:55:31 PM PST 24 |
5413169524 ps |
| T805 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.4262292482 |
|
|
Feb 29 04:08:26 PM PST 24 |
Feb 29 04:13:42 PM PST 24 |
4014430090 ps |
| T788 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.4260721820 |
|
|
Feb 29 04:04:45 PM PST 24 |
Feb 29 04:15:25 PM PST 24 |
4962155800 ps |
| T72 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4134738760 |
|
|
Feb 29 03:56:24 PM PST 24 |
Feb 29 04:05:18 PM PST 24 |
4222770890 ps |
| T948 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1454056089 |
|
|
Feb 29 03:38:24 PM PST 24 |
Feb 29 03:41:31 PM PST 24 |
2711679452 ps |
| T784 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1812458321 |
|
|
Feb 29 04:04:58 PM PST 24 |
Feb 29 04:10:55 PM PST 24 |
3549754180 ps |
| T142 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1738446863 |
|
|
Feb 29 03:32:08 PM PST 24 |
Feb 29 03:41:12 PM PST 24 |
4654409054 ps |
| T198 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.278959386 |
|
|
Feb 29 03:41:10 PM PST 24 |
Feb 29 03:47:41 PM PST 24 |
3078131705 ps |
| T949 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.467877660 |
|
|
Feb 29 03:37:03 PM PST 24 |
Feb 29 04:13:32 PM PST 24 |
7686016694 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3949361228 |
|
|
Feb 29 03:29:46 PM PST 24 |
Feb 29 03:37:01 PM PST 24 |
3558310041 ps |
| T42 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.3070884553 |
|
|
Feb 29 03:30:22 PM PST 24 |
Feb 29 03:39:41 PM PST 24 |
3987546824 ps |
| T367 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3737648040 |
|
|
Feb 29 03:53:39 PM PST 24 |
Feb 29 04:56:25 PM PST 24 |
16907310690 ps |
| T170 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.3585179636 |
|
|
Feb 29 03:44:44 PM PST 24 |
Feb 29 03:49:21 PM PST 24 |
2337581601 ps |
| T73 |
/workspace/coverage/default/1.chip_jtag_mem_access.1269368917 |
|
|
Feb 29 03:38:00 PM PST 24 |
Feb 29 04:05:50 PM PST 24 |
13206245560 ps |
| T96 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3177082235 |
|
|
Feb 29 03:50:39 PM PST 24 |
Feb 29 04:13:51 PM PST 24 |
23060027030 ps |
| T368 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1561738525 |
|
|
Feb 29 03:40:18 PM PST 24 |
Feb 29 04:11:35 PM PST 24 |
7443593032 ps |
| T369 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.195760722 |
|
|
Feb 29 04:02:20 PM PST 24 |
Feb 29 04:04:53 PM PST 24 |
2844454160 ps |
| T370 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.676383461 |
|
|
Feb 29 03:37:37 PM PST 24 |
Feb 29 03:43:36 PM PST 24 |
5520867960 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2398917412 |
|
|
Feb 29 03:48:26 PM PST 24 |
Feb 29 03:52:32 PM PST 24 |
2578426304 ps |
| T7 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.2026330286 |
|
|
Feb 29 03:32:22 PM PST 24 |
Feb 29 03:37:11 PM PST 24 |
2584109351 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3443173593 |
|
|
Feb 29 03:37:57 PM PST 24 |
Feb 29 03:41:33 PM PST 24 |
2470639387 ps |
| T951 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.1988008472 |
|
|
Feb 29 03:50:12 PM PST 24 |
Feb 29 04:08:49 PM PST 24 |
8821173404 ps |
| T739 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.366581074 |
|
|
Feb 29 04:10:12 PM PST 24 |
Feb 29 04:21:45 PM PST 24 |
6004496630 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.776255524 |
|
|
Feb 29 03:40:57 PM PST 24 |
Feb 29 03:55:33 PM PST 24 |
12109082223 ps |
| T742 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.967332933 |
|
|
Feb 29 04:09:22 PM PST 24 |
Feb 29 04:22:49 PM PST 24 |
5332518378 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.187999533 |
|
|
Feb 29 03:37:00 PM PST 24 |
Feb 29 03:41:49 PM PST 24 |
2550321320 ps |
| T954 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.557893665 |
|
|
Feb 29 03:27:06 PM PST 24 |
Feb 29 03:44:07 PM PST 24 |
6202891846 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.444880055 |
|
|
Feb 29 03:27:06 PM PST 24 |
Feb 29 03:34:08 PM PST 24 |
5565459290 ps |
| T955 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2619367606 |
|
|
Feb 29 03:56:41 PM PST 24 |
Feb 29 04:01:18 PM PST 24 |
3001499839 ps |
| T956 |
/workspace/coverage/default/1.rom_e2e_smoke.1972200620 |
|
|
Feb 29 03:48:26 PM PST 24 |
Feb 29 04:14:38 PM PST 24 |
8536884666 ps |
| T229 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.1383501930 |
|
|
Feb 29 04:05:27 PM PST 24 |
Feb 29 04:11:42 PM PST 24 |
3556018410 ps |
| T266 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.2614034982 |
|
|
Feb 29 03:30:14 PM PST 24 |
Feb 29 03:34:48 PM PST 24 |
3231585652 ps |
| T239 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2009044472 |
|
|
Feb 29 03:30:38 PM PST 24 |
Feb 29 03:39:14 PM PST 24 |
2750467992 ps |
| T267 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.824565353 |
|
|
Feb 29 03:59:02 PM PST 24 |
Feb 29 04:05:53 PM PST 24 |
5299096652 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.2738375794 |
|
|
Feb 29 03:30:52 PM PST 24 |
Feb 29 03:33:46 PM PST 24 |
2162011578 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2744962387 |
|
|
Feb 29 03:52:59 PM PST 24 |
Feb 29 04:01:47 PM PST 24 |
4392371518 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2768635203 |
|
|
Feb 29 03:33:55 PM PST 24 |
Feb 29 04:42:05 PM PST 24 |
12945843112 ps |
| T270 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.222009034 |
|
|
Feb 29 04:10:10 PM PST 24 |
Feb 29 04:16:24 PM PST 24 |
3633086110 ps |
| T271 |
/workspace/coverage/default/8.chip_sw_uart_rand_baudrate.822995192 |
|
|
Feb 29 04:00:06 PM PST 24 |
Feb 29 04:36:00 PM PST 24 |
12517639228 ps |
| T272 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1607172016 |
|
|
Feb 29 04:01:31 PM PST 24 |
Feb 29 04:08:34 PM PST 24 |
6712052672 ps |
| T230 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2145823085 |
|
|
Feb 29 04:08:07 PM PST 24 |
Feb 29 04:14:21 PM PST 24 |
3404389512 ps |
| T957 |
/workspace/coverage/default/1.rom_e2e_static_critical.2896711341 |
|
|
Feb 29 03:50:31 PM PST 24 |
Feb 29 04:38:26 PM PST 24 |
10236633748 ps |
| T958 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3750556838 |
|
|
Feb 29 04:04:48 PM PST 24 |
Feb 29 05:14:40 PM PST 24 |
23115740840 ps |
| T959 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.3361045355 |
|
|
Feb 29 03:43:27 PM PST 24 |
Feb 29 03:46:43 PM PST 24 |
2373144340 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.782981803 |
|
|
Feb 29 03:46:50 PM PST 24 |
Feb 29 03:51:56 PM PST 24 |
3486466886 ps |
| T143 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2191857987 |
|
|
Feb 29 03:54:18 PM PST 24 |
Feb 29 04:08:12 PM PST 24 |
3900275850 ps |
| T961 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.3816525540 |
|
|
Feb 29 03:28:03 PM PST 24 |
Feb 29 03:45:26 PM PST 24 |
5927801066 ps |
| T313 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2403048620 |
|
|
Feb 29 03:41:35 PM PST 24 |
Feb 29 03:52:31 PM PST 24 |
18373935870 ps |
| T962 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1799088957 |
|
|
Feb 29 03:57:31 PM PST 24 |
Feb 29 04:18:26 PM PST 24 |
5709632226 ps |
| T660 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.2495327375 |
|
|
Feb 29 04:03:22 PM PST 24 |
Feb 29 04:09:09 PM PST 24 |
3634534324 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.72584744 |
|
|
Feb 29 03:26:55 PM PST 24 |
Feb 29 03:48:12 PM PST 24 |
7326316552 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.933184347 |
|
|
Feb 29 03:31:52 PM PST 24 |
Feb 29 04:29:24 PM PST 24 |
11941483900 ps |
| T231 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.2646896895 |
|
|
Feb 29 04:08:26 PM PST 24 |
Feb 29 04:15:44 PM PST 24 |
3981386204 ps |
| T964 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3210284291 |
|
|
Feb 29 03:26:48 PM PST 24 |
Feb 29 03:33:53 PM PST 24 |
5941153562 ps |
| T52 |
/workspace/coverage/default/0.chip_sw_alert_test.1059395372 |
|
|
Feb 29 03:28:33 PM PST 24 |
Feb 29 03:34:34 PM PST 24 |
3243829438 ps |
| T738 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.57437251 |
|
|
Feb 29 04:02:10 PM PST 24 |
Feb 29 04:08:04 PM PST 24 |
3810461890 ps |
| T74 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1439338037 |
|
|
Feb 29 03:48:46 PM PST 24 |
Feb 29 04:09:28 PM PST 24 |
10569075208 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.864880375 |
|
|
Feb 29 03:28:21 PM PST 24 |
Feb 29 03:33:15 PM PST 24 |
2673555816 ps |
| T65 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.1431493237 |
|
|
Feb 29 03:55:55 PM PST 24 |
Feb 29 04:04:14 PM PST 24 |
5217690829 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2909891189 |
|
|
Feb 29 03:41:09 PM PST 24 |
Feb 29 03:56:14 PM PST 24 |
5036261600 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2794488182 |
|
|
Feb 29 03:34:56 PM PST 24 |
Feb 29 03:45:10 PM PST 24 |
5000256408 ps |
| T966 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.2777037860 |
|
|
Feb 29 03:39:55 PM PST 24 |
Feb 29 03:58:54 PM PST 24 |
8176285784 ps |
| T764 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.2186627069 |
|
|
Feb 29 04:05:57 PM PST 24 |
Feb 29 04:15:05 PM PST 24 |
5582163616 ps |
| T665 |
/workspace/coverage/default/3.chip_tap_straps_dev.219493101 |
|
|
Feb 29 03:58:36 PM PST 24 |
Feb 29 04:09:08 PM PST 24 |
7629387491 ps |
| T747 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1228303577 |
|
|
Feb 29 04:07:42 PM PST 24 |
Feb 29 04:18:35 PM PST 24 |
4992821772 ps |
| T285 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1835580972 |
|
|
Feb 29 03:54:28 PM PST 24 |
Feb 29 04:16:34 PM PST 24 |
6104742412 ps |
| T967 |
/workspace/coverage/default/1.chip_sw_edn_kat.644064668 |
|
|
Feb 29 03:43:58 PM PST 24 |
Feb 29 03:52:56 PM PST 24 |
3706713380 ps |
| T733 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.3247475576 |
|
|
Feb 29 04:03:38 PM PST 24 |
Feb 29 04:11:57 PM PST 24 |
3874155332 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.4095810545 |
|
|
Feb 29 03:57:07 PM PST 24 |
Feb 29 04:07:15 PM PST 24 |
5451385960 ps |
| T297 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.250383706 |
|
|
Feb 29 03:39:16 PM PST 24 |
Feb 29 03:51:24 PM PST 24 |
5096232560 ps |
| T195 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.3542593322 |
|
|
Feb 29 03:39:24 PM PST 24 |
Feb 29 07:05:32 PM PST 24 |
65344815423 ps |
| T969 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.4087430257 |
|
|
Feb 29 03:31:00 PM PST 24 |
Feb 29 03:35:09 PM PST 24 |
3238855170 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.1253961287 |
|
|
Feb 29 03:39:56 PM PST 24 |
Feb 29 03:44:53 PM PST 24 |
3843259516 ps |
| T48 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3438387157 |
|
|
Feb 29 03:37:28 PM PST 24 |
Feb 29 03:42:24 PM PST 24 |
3505505000 ps |
| T356 |
/workspace/coverage/default/2.chip_sw_aes_idle.2581739695 |
|
|
Feb 29 03:53:02 PM PST 24 |
Feb 29 03:57:08 PM PST 24 |
2745528790 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.535091067 |
|
|
Feb 29 03:28:50 PM PST 24 |
Feb 29 03:46:29 PM PST 24 |
8895978352 ps |
| T358 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3852065063 |
|
|
Feb 29 03:30:40 PM PST 24 |
Feb 29 03:34:31 PM PST 24 |
2580299812 ps |
| T263 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2318788928 |
|
|
Feb 29 03:41:20 PM PST 24 |
Feb 29 03:50:05 PM PST 24 |
3569674784 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.908183398 |
|
|
Feb 29 03:28:43 PM PST 24 |
Feb 29 04:53:28 PM PST 24 |
18918720424 ps |
| T359 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.893184067 |
|
|
Feb 29 04:03:05 PM PST 24 |
Feb 29 04:15:27 PM PST 24 |
5381404520 ps |
| T360 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1643495229 |
|
|
Feb 29 03:55:27 PM PST 24 |
Feb 29 04:02:04 PM PST 24 |
5635158054 ps |
| T361 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2311768164 |
|
|
Feb 29 03:48:32 PM PST 24 |
Feb 29 03:52:40 PM PST 24 |
3477632444 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.549386814 |
|
|
Feb 29 03:30:07 PM PST 24 |
Feb 29 03:33:54 PM PST 24 |
3103813736 ps |
| T769 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.827618690 |
|
|
Feb 29 03:59:28 PM PST 24 |
Feb 29 04:10:04 PM PST 24 |
4574177032 ps |
| T971 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.2220170102 |
|
|
Feb 29 03:44:16 PM PST 24 |
Feb 29 04:20:03 PM PST 24 |
16950914916 ps |
| T972 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.263985220 |
|
|
Feb 29 03:31:25 PM PST 24 |
Feb 29 03:36:23 PM PST 24 |
3816463609 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.719359001 |
|
|
Feb 29 03:27:40 PM PST 24 |
Feb 29 03:48:52 PM PST 24 |
6321733220 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3065760098 |
|
|
Feb 29 03:55:29 PM PST 24 |
Feb 29 04:00:30 PM PST 24 |
2842454408 ps |
| T213 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.4161991946 |
|
|
Feb 29 03:46:09 PM PST 24 |
Feb 29 03:54:21 PM PST 24 |
3497923920 ps |
| T199 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.3729697919 |
|
|
Feb 29 03:29:30 PM PST 24 |
Feb 29 03:33:57 PM PST 24 |
3162073031 ps |
| T776 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.2674297692 |
|
|
Feb 29 04:01:51 PM PST 24 |
Feb 29 04:11:28 PM PST 24 |
5854517270 ps |
| T975 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.759048704 |
|
|
Feb 29 03:52:54 PM PST 24 |
Feb 29 04:02:45 PM PST 24 |
4581520488 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1837558011 |
|
|
Feb 29 03:56:52 PM PST 24 |
Feb 29 04:13:24 PM PST 24 |
7006867800 ps |
| T802 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.822637961 |
|
|
Feb 29 04:06:34 PM PST 24 |
Feb 29 04:17:34 PM PST 24 |
5413047156 ps |
| T25 |
/workspace/coverage/default/1.chip_sw_gpio.580860082 |
|
|
Feb 29 03:42:11 PM PST 24 |
Feb 29 03:47:36 PM PST 24 |
3852628649 ps |
| T43 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4109312222 |
|
|
Feb 29 03:56:59 PM PST 24 |
Feb 29 04:02:52 PM PST 24 |
3701990260 ps |
| T713 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2122939464 |
|
|
Feb 29 04:08:16 PM PST 24 |
Feb 29 04:20:01 PM PST 24 |
6383520312 ps |
| T714 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.4134650088 |
|
|
Feb 29 04:09:31 PM PST 24 |
Feb 29 04:18:08 PM PST 24 |
3643627960 ps |
| T287 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.336389075 |
|
|
Feb 29 03:57:57 PM PST 24 |
Feb 29 04:13:34 PM PST 24 |
6121650515 ps |
| T389 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.1549640447 |
|
|
Feb 29 03:46:50 PM PST 24 |
Feb 29 03:59:26 PM PST 24 |
3985087640 ps |
| T715 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3904197110 |
|
|
Feb 29 03:50:50 PM PST 24 |
Feb 29 03:59:30 PM PST 24 |
5919069110 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3737072722 |
|
|
Feb 29 03:38:47 PM PST 24 |
Feb 29 03:45:47 PM PST 24 |
4622204296 ps |
| T288 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2295842749 |
|
|
Feb 29 03:48:25 PM PST 24 |
Feb 29 03:54:37 PM PST 24 |
3622183136 ps |
| T20 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.3038667217 |
|
|
Feb 29 03:40:18 PM PST 24 |
Feb 29 04:06:35 PM PST 24 |
22155097194 ps |
| T716 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.829439342 |
|
|
Feb 29 03:55:05 PM PST 24 |
Feb 29 04:07:43 PM PST 24 |
4913118588 ps |
| T264 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.81406617 |
|
|
Feb 29 04:03:42 PM PST 24 |
Feb 29 04:16:17 PM PST 24 |
5401266888 ps |
| T339 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.1958621378 |
|
|
Feb 29 03:56:59 PM PST 24 |
Feb 29 04:00:19 PM PST 24 |
2864367380 ps |
| T977 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3157674790 |
|
|
Feb 29 03:52:09 PM PST 24 |
Feb 29 04:14:49 PM PST 24 |
5052911346 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.461366595 |
|
|
Feb 29 03:56:55 PM PST 24 |
Feb 29 04:16:01 PM PST 24 |
7108469895 ps |
| T149 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3105465920 |
|
|
Feb 29 03:46:51 PM PST 24 |
Feb 29 04:29:11 PM PST 24 |
13367531101 ps |
| T809 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2382491429 |
|
|
Feb 29 04:09:21 PM PST 24 |
Feb 29 04:17:38 PM PST 24 |
4332732154 ps |
| T743 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.4206809633 |
|
|
Feb 29 04:00:41 PM PST 24 |
Feb 29 04:06:51 PM PST 24 |
3988504440 ps |
| T183 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.3961051275 |
|
|
Feb 29 03:38:44 PM PST 24 |
Feb 29 03:45:56 PM PST 24 |
3564060783 ps |
| T97 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1544337889 |
|
|
Feb 29 03:46:06 PM PST 24 |
Feb 29 03:53:48 PM PST 24 |
6775711288 ps |
| T98 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1234857389 |
|
|
Feb 29 03:33:55 PM PST 24 |
Feb 29 03:41:24 PM PST 24 |
7248465800 ps |
| T750 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.115874071 |
|
|
Feb 29 04:04:51 PM PST 24 |
Feb 29 04:11:26 PM PST 24 |
3397899056 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.60289813 |
|
|
Feb 29 03:50:58 PM PST 24 |
Feb 29 04:10:41 PM PST 24 |
5849098717 ps |
| T757 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.1852073887 |
|
|
Feb 29 04:01:54 PM PST 24 |
Feb 29 04:12:20 PM PST 24 |
4404501844 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2354057477 |
|
|
Feb 29 03:55:05 PM PST 24 |
Feb 29 04:08:01 PM PST 24 |
5361475088 ps |
| T766 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.170903799 |
|
|
Feb 29 04:04:06 PM PST 24 |
Feb 29 04:15:05 PM PST 24 |
5140442840 ps |
| T980 |
/workspace/coverage/default/1.chip_sw_example_rom.1023899293 |
|
|
Feb 29 03:37:49 PM PST 24 |
Feb 29 03:39:47 PM PST 24 |
2553668224 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.2768995774 |
|
|
Feb 29 03:27:04 PM PST 24 |
Feb 29 03:54:00 PM PST 24 |
8127362008 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2743738227 |
|
|
Feb 29 03:52:22 PM PST 24 |
Feb 29 04:30:35 PM PST 24 |
9354692390 ps |
| T982 |
/workspace/coverage/default/0.chip_sw_hmac_enc.1908341681 |
|
|
Feb 29 03:28:00 PM PST 24 |
Feb 29 03:32:56 PM PST 24 |
3045911532 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.3886956623 |
|
|
Feb 29 03:40:36 PM PST 24 |
Feb 29 04:40:06 PM PST 24 |
12058477400 ps |
| T984 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.331593691 |
|
|
Feb 29 03:55:31 PM PST 24 |
Feb 29 04:03:55 PM PST 24 |
4033761564 ps |
| T9 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.3488515641 |
|
|
Feb 29 03:49:26 PM PST 24 |
Feb 29 03:53:51 PM PST 24 |
2993132627 ps |
| T985 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.3826954182 |
|
|
Feb 29 03:34:06 PM PST 24 |
Feb 29 07:05:15 PM PST 24 |
63106620231 ps |
| T53 |
/workspace/coverage/default/1.chip_sw_alert_test.4021192531 |
|
|
Feb 29 03:43:34 PM PST 24 |
Feb 29 03:48:34 PM PST 24 |
3410754104 ps |
| T986 |
/workspace/coverage/default/0.chip_tap_straps_rma.2265884032 |
|
|
Feb 29 03:31:18 PM PST 24 |
Feb 29 03:38:03 PM PST 24 |
5275024003 ps |
| T987 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.3561294777 |
|
|
Feb 29 03:38:29 PM PST 24 |
Feb 29 04:15:49 PM PST 24 |
8713337594 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.259252839 |
|
|
Feb 29 03:50:00 PM PST 24 |
Feb 29 04:12:44 PM PST 24 |
5342654103 ps |
| T989 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1086139496 |
|
|
Feb 29 03:39:45 PM PST 24 |
Feb 29 04:35:47 PM PST 24 |
11679535859 ps |
| T990 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2285921958 |
|
|
Feb 29 03:50:43 PM PST 24 |
Feb 29 03:55:02 PM PST 24 |
3493174794 ps |
| T991 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.2120907177 |
|
|
Feb 29 03:45:47 PM PST 24 |
Feb 29 03:48:50 PM PST 24 |
3236171141 ps |
| T992 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1316694369 |
|
|
Feb 29 03:33:10 PM PST 24 |
Feb 29 03:38:43 PM PST 24 |
3245566772 ps |
| T26 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.2849545662 |
|
|
Feb 29 03:37:25 PM PST 24 |
Feb 29 03:40:35 PM PST 24 |
2866387827 ps |
| T993 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.132819770 |
|
|
Feb 29 03:44:34 PM PST 24 |
Feb 29 03:52:42 PM PST 24 |
5034025788 ps |
| T760 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.259002526 |
|
|
Feb 29 04:11:26 PM PST 24 |
Feb 29 04:22:30 PM PST 24 |
4299628440 ps |
| T659 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.735242439 |
|
|
Feb 29 03:42:10 PM PST 24 |
Feb 29 04:48:53 PM PST 24 |
17681825974 ps |
| T994 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.3863063314 |
|
|
Feb 29 03:40:36 PM PST 24 |
Feb 29 04:15:58 PM PST 24 |
8532933764 ps |
| T995 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.3624306984 |
|
|
Feb 29 03:39:24 PM PST 24 |
Feb 29 04:12:02 PM PST 24 |
8497807953 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2321023500 |
|
|
Feb 29 03:28:21 PM PST 24 |
Feb 29 03:36:38 PM PST 24 |
4356961670 ps |
| T753 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2333353369 |
|
|
Feb 29 04:04:55 PM PST 24 |
Feb 29 04:12:12 PM PST 24 |
4573621158 ps |
| T996 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3510564579 |
|
|
Feb 29 04:01:07 PM PST 24 |
Feb 29 04:17:22 PM PST 24 |
6304475496 ps |
| T997 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3143840980 |
|
|
Feb 29 03:39:00 PM PST 24 |
Feb 29 03:58:17 PM PST 24 |
6321988992 ps |
| T998 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.4002126705 |
|
|
Feb 29 03:28:12 PM PST 24 |
Feb 29 03:45:26 PM PST 24 |
5363029500 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1280584056 |
|
|
Feb 29 03:55:30 PM PST 24 |
Feb 29 04:07:54 PM PST 24 |
3838092600 ps |
| T1000 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.343801892 |
|
|
Feb 29 03:54:18 PM PST 24 |
Feb 29 04:07:30 PM PST 24 |
6795553752 ps |
| T1001 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1425646263 |
|
|
Feb 29 03:34:21 PM PST 24 |
Feb 29 04:10:31 PM PST 24 |
13515244573 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.10307209 |
|
|
Feb 29 03:45:31 PM PST 24 |
Feb 29 03:53:38 PM PST 24 |
5769634066 ps |
| T1003 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.892972272 |
|
|
Feb 29 03:47:32 PM PST 24 |
Feb 29 03:50:46 PM PST 24 |
2664680914 ps |
| T1004 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.70110800 |
|
|
Feb 29 03:55:23 PM PST 24 |
Feb 29 04:05:09 PM PST 24 |
4179979052 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.302347276 |
|
|
Feb 29 03:28:31 PM PST 24 |
Feb 29 03:31:21 PM PST 24 |
2532577876 ps |
| T1006 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.731682780 |
|
|
Feb 29 03:59:07 PM PST 24 |
Feb 29 04:10:13 PM PST 24 |
4916754976 ps |
| T683 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.3749552940 |
|
|
Feb 29 04:05:52 PM PST 24 |
Feb 29 04:12:47 PM PST 24 |
3710117680 ps |
| T1007 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1304431414 |
|
|
Feb 29 04:09:38 PM PST 24 |
Feb 29 04:16:09 PM PST 24 |
3984893420 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3751925122 |
|
|
Feb 29 03:48:55 PM PST 24 |
Feb 29 03:59:18 PM PST 24 |
4442365912 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1282168546 |
|
|
Feb 29 03:26:43 PM PST 24 |
Feb 29 05:01:00 PM PST 24 |
48805289372 ps |
| T789 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.221591220 |
|
|
Feb 29 04:03:35 PM PST 24 |
Feb 29 04:15:15 PM PST 24 |
4731894978 ps |
| T66 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.733574957 |
|
|
Feb 29 03:28:47 PM PST 24 |
Feb 29 05:30:01 PM PST 24 |
31549437320 ps |
| T768 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2834280790 |
|
|
Feb 29 04:12:40 PM PST 24 |
Feb 29 04:20:31 PM PST 24 |
3667843488 ps |
| T201 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.3930655719 |
|
|
Feb 29 03:31:01 PM PST 24 |
Feb 29 03:40:06 PM PST 24 |
5583169520 ps |
| T1008 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.3984413846 |
|
|
Feb 29 03:45:08 PM PST 24 |
Feb 29 03:55:48 PM PST 24 |
5845524064 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3359901253 |
|
|
Feb 29 03:30:07 PM PST 24 |
Feb 29 03:39:51 PM PST 24 |
4883144680 ps |
| T762 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.691474431 |
|
|
Feb 29 04:05:02 PM PST 24 |
Feb 29 04:11:22 PM PST 24 |
3861032920 ps |
| T1010 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.1171259175 |
|
|
Feb 29 04:03:48 PM PST 24 |
Feb 29 04:39:47 PM PST 24 |
9180437256 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.1150655538 |
|
|
Feb 29 03:49:48 PM PST 24 |
Feb 29 04:04:17 PM PST 24 |
4403961448 ps |
| T82 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.3959646693 |
|
|
Feb 29 04:03:44 PM PST 24 |
Feb 29 04:17:45 PM PST 24 |
5247293324 ps |
| T87 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2406505356 |
|
|
Feb 29 03:31:15 PM PST 24 |
Feb 29 03:46:11 PM PST 24 |
4121782152 ps |
| T88 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.1548605063 |
|
|
Feb 29 03:26:46 PM PST 24 |
Feb 29 04:21:08 PM PST 24 |
42073382694 ps |
| T89 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.1984225562 |
|
|
Feb 29 03:50:26 PM PST 24 |
Feb 29 03:54:07 PM PST 24 |
3213782988 ps |
| T90 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3498879473 |
|
|
Feb 29 03:57:06 PM PST 24 |
Feb 29 04:05:11 PM PST 24 |
4796254857 ps |
| T91 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1155325239 |
|
|
Feb 29 04:04:07 PM PST 24 |
Feb 29 04:52:05 PM PST 24 |
13743030250 ps |
| T92 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.437996733 |
|
|
Feb 29 03:36:34 PM PST 24 |
Feb 29 03:40:10 PM PST 24 |
2342452484 ps |
| T93 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.4029687481 |
|
|
Feb 29 03:28:25 PM PST 24 |
Feb 29 03:48:07 PM PST 24 |
8366184136 ps |
| T94 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.4075749105 |
|
|
Feb 29 04:01:40 PM PST 24 |
Feb 29 04:09:23 PM PST 24 |
4942580056 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.2085206219 |
|
|
Feb 29 03:45:42 PM PST 24 |
Feb 29 04:28:20 PM PST 24 |
18812663677 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.433328832 |
|
|
Feb 29 04:01:05 PM PST 24 |
Feb 29 04:06:14 PM PST 24 |
3247489220 ps |
| T83 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2768172286 |
|
|
Feb 29 04:04:31 PM PST 24 |
Feb 29 04:10:51 PM PST 24 |
3712387640 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.939969167 |
|
|
Feb 29 03:41:21 PM PST 24 |
Feb 29 04:00:21 PM PST 24 |
5954724418 ps |
| T1014 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.3113792898 |
|
|
Feb 29 03:42:19 PM PST 24 |
Feb 29 03:53:30 PM PST 24 |
5700885574 ps |
| T1015 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.156307233 |
|
|
Feb 29 03:50:55 PM PST 24 |
Feb 29 03:57:05 PM PST 24 |
6592937616 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3715185395 |
|
|
Feb 29 03:31:01 PM PST 24 |
Feb 29 03:34:45 PM PST 24 |
2489572379 ps |
| T1017 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.775775787 |
|
|
Feb 29 03:48:12 PM PST 24 |
Feb 29 03:56:56 PM PST 24 |
5837536920 ps |
| T1018 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.488435841 |
|
|
Feb 29 04:06:11 PM PST 24 |
Feb 29 04:17:38 PM PST 24 |
4725096218 ps |
| T218 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3063713064 |
|
|
Feb 29 03:50:40 PM PST 24 |
Feb 29 05:12:58 PM PST 24 |
44650196019 ps |
| T1019 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3139200871 |
|
|
Feb 29 03:28:21 PM PST 24 |
Feb 29 03:34:21 PM PST 24 |
4170120310 ps |
| T1020 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.252589891 |
|
|
Feb 29 03:51:28 PM PST 24 |
Feb 29 04:00:09 PM PST 24 |
3569316168 ps |
| T691 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.1930808267 |
|
|
Feb 29 03:40:38 PM PST 24 |
Feb 29 03:45:19 PM PST 24 |
3318948300 ps |
| T1021 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.4149088556 |
|
|
Feb 29 03:42:25 PM PST 24 |
Feb 29 03:46:10 PM PST 24 |
2324170904 ps |
| T1022 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2592449886 |
|
|
Feb 29 03:36:41 PM PST 24 |
Feb 29 03:41:41 PM PST 24 |
3026276800 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.3656545570 |
|
|
Feb 29 03:30:17 PM PST 24 |
Feb 29 03:52:20 PM PST 24 |
11092663274 ps |