| T777 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.1268473281 |
|
|
Feb 29 04:07:43 PM PST 24 |
Feb 29 04:13:48 PM PST 24 |
3941503368 ps |
| T1184 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.454086899 |
|
|
Feb 29 03:44:30 PM PST 24 |
Feb 29 03:48:46 PM PST 24 |
3432143000 ps |
| T1185 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.839222373 |
|
|
Feb 29 04:06:23 PM PST 24 |
Feb 29 04:17:11 PM PST 24 |
5747814840 ps |
| T655 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2842009998 |
|
|
Feb 29 03:41:52 PM PST 24 |
Feb 29 04:01:19 PM PST 24 |
4924114214 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1386500106 |
|
|
Feb 29 03:51:31 PM PST 24 |
Feb 29 04:00:30 PM PST 24 |
6514403570 ps |
| T243 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.1725370618 |
|
|
Feb 29 04:00:38 PM PST 24 |
Feb 29 04:09:35 PM PST 24 |
5227989412 ps |
| T1187 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.911226199 |
|
|
Feb 29 03:29:34 PM PST 24 |
Feb 29 03:33:58 PM PST 24 |
3061542444 ps |
| T294 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.2343355583 |
|
|
Feb 29 03:43:34 PM PST 24 |
Feb 29 04:06:36 PM PST 24 |
5928998574 ps |
| T669 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.4255805295 |
|
|
Feb 29 03:40:21 PM PST 24 |
Feb 29 03:42:10 PM PST 24 |
2561623183 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2374796050 |
|
|
Feb 29 03:39:13 PM PST 24 |
Feb 29 03:40:48 PM PST 24 |
2099882059 ps |
| T86 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2885062125 |
|
|
Feb 29 04:08:25 PM PST 24 |
Feb 29 04:19:08 PM PST 24 |
4908236750 ps |
| T1188 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.3787275581 |
|
|
Feb 29 04:04:42 PM PST 24 |
Feb 29 04:13:39 PM PST 24 |
4589468848 ps |
| T1189 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3333823251 |
|
|
Feb 29 03:50:19 PM PST 24 |
Feb 29 03:54:11 PM PST 24 |
2529922136 ps |
| T1190 |
/workspace/coverage/default/2.rom_e2e_smoke.2297092789 |
|
|
Feb 29 03:57:31 PM PST 24 |
Feb 29 04:36:02 PM PST 24 |
9236756296 ps |
| T1191 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.4281454374 |
|
|
Feb 29 03:41:49 PM PST 24 |
Feb 29 04:17:15 PM PST 24 |
13458208153 ps |
| T1192 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.3388335971 |
|
|
Feb 29 03:54:06 PM PST 24 |
Feb 29 04:06:08 PM PST 24 |
3807498738 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.1892361218 |
|
|
Feb 29 03:41:43 PM PST 24 |
Feb 29 04:48:25 PM PST 24 |
18808581746 ps |
| T1194 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4130756287 |
|
|
Feb 29 03:38:23 PM PST 24 |
Feb 29 04:08:26 PM PST 24 |
8690247665 ps |
| T1195 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2489716724 |
|
|
Feb 29 03:27:21 PM PST 24 |
Feb 29 03:40:23 PM PST 24 |
7847344543 ps |
| T1196 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3196370158 |
|
|
Feb 29 04:07:53 PM PST 24 |
Feb 29 04:13:23 PM PST 24 |
3191660448 ps |
| T1197 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.421062192 |
|
|
Feb 29 03:36:54 PM PST 24 |
Feb 29 03:41:31 PM PST 24 |
3150047764 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.2164171011 |
|
|
Feb 29 03:48:06 PM PST 24 |
Feb 29 03:52:52 PM PST 24 |
2590969904 ps |
| T667 |
/workspace/coverage/default/1.chip_tap_straps_dev.3405073109 |
|
|
Feb 29 03:44:43 PM PST 24 |
Feb 29 04:13:49 PM PST 24 |
14309707354 ps |
| T1199 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.3505483652 |
|
|
Feb 29 03:28:05 PM PST 24 |
Feb 29 03:34:45 PM PST 24 |
4284384422 ps |
| T759 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.4013036346 |
|
|
Feb 29 04:09:54 PM PST 24 |
Feb 29 04:18:57 PM PST 24 |
3808765456 ps |
| T732 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.1685217572 |
|
|
Feb 29 04:09:21 PM PST 24 |
Feb 29 04:19:35 PM PST 24 |
5618930312 ps |
| T1200 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2770696557 |
|
|
Feb 29 03:43:21 PM PST 24 |
Feb 29 04:53:17 PM PST 24 |
16736355804 ps |
| T1201 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.1714996219 |
|
|
Feb 29 03:38:02 PM PST 24 |
Feb 29 04:06:58 PM PST 24 |
6971472772 ps |
| T670 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_raw_to_scrap.220609994 |
|
|
Feb 29 03:27:58 PM PST 24 |
Feb 29 03:29:55 PM PST 24 |
3323865302 ps |
| T794 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.658701423 |
|
|
Feb 29 04:08:43 PM PST 24 |
Feb 29 04:18:32 PM PST 24 |
4535624984 ps |
| T1202 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.3464960216 |
|
|
Feb 29 04:04:31 PM PST 24 |
Feb 29 04:16:24 PM PST 24 |
4850964664 ps |
| T1203 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1326318580 |
|
|
Feb 29 04:10:02 PM PST 24 |
Feb 29 04:19:44 PM PST 24 |
4697526056 ps |
| T1204 |
/workspace/coverage/default/1.rom_keymgr_functest.4149649716 |
|
|
Feb 29 03:47:24 PM PST 24 |
Feb 29 03:55:22 PM PST 24 |
3475267112 ps |
| T1205 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.797992671 |
|
|
Feb 29 03:30:28 PM PST 24 |
Feb 29 03:40:26 PM PST 24 |
3879145970 ps |
| T1206 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.1590636793 |
|
|
Feb 29 03:42:29 PM PST 24 |
Feb 29 04:08:50 PM PST 24 |
6132044176 ps |
| T1207 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.3323336613 |
|
|
Feb 29 03:38:00 PM PST 24 |
Feb 29 04:17:37 PM PST 24 |
8450978632 ps |
| T329 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.341572239 |
|
|
Feb 29 03:30:58 PM PST 24 |
Feb 29 03:40:35 PM PST 24 |
5149276880 ps |
| T1208 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.2409930588 |
|
|
Feb 29 04:00:34 PM PST 24 |
Feb 29 04:18:41 PM PST 24 |
9090948016 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.157563168 |
|
|
Feb 29 03:29:23 PM PST 24 |
Feb 29 03:31:21 PM PST 24 |
2387287591 ps |
| T792 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2853212676 |
|
|
Feb 29 04:05:53 PM PST 24 |
Feb 29 04:13:22 PM PST 24 |
3700861314 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.2891852861 |
|
|
Feb 29 03:43:19 PM PST 24 |
Feb 29 03:53:55 PM PST 24 |
4064268882 ps |
| T60 |
/workspace/coverage/default/4.chip_tap_straps_rma.212911756 |
|
|
Feb 29 04:01:29 PM PST 24 |
Feb 29 04:04:51 PM PST 24 |
3168019870 ps |
| T1211 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3223918495 |
|
|
Feb 29 03:49:24 PM PST 24 |
Feb 29 03:53:09 PM PST 24 |
2382380656 ps |
| T1212 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.4040957658 |
|
|
Feb 29 04:01:07 PM PST 24 |
Feb 29 04:05:41 PM PST 24 |
2212768677 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1157583024 |
|
|
Feb 29 03:29:09 PM PST 24 |
Feb 29 03:38:00 PM PST 24 |
3995545072 ps |
| T1214 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.1175031139 |
|
|
Feb 29 03:57:50 PM PST 24 |
Feb 29 04:02:11 PM PST 24 |
2666104584 ps |
| T1215 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.3787799629 |
|
|
Feb 29 03:44:06 PM PST 24 |
Feb 29 03:53:17 PM PST 24 |
5161567586 ps |
| T1216 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1418630376 |
|
|
Feb 29 04:06:16 PM PST 24 |
Feb 29 04:12:17 PM PST 24 |
3421436060 ps |
| T1217 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.60418085 |
|
|
Feb 29 04:09:19 PM PST 24 |
Feb 29 04:15:41 PM PST 24 |
3438433176 ps |
| T1218 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.726259882 |
|
|
Feb 29 03:32:21 PM PST 24 |
Feb 29 04:12:40 PM PST 24 |
12336072825 ps |
| T1219 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.437027246 |
|
|
Feb 29 03:27:23 PM PST 24 |
Feb 29 03:47:14 PM PST 24 |
7701760840 ps |
| T1220 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.151635879 |
|
|
Feb 29 03:59:24 PM PST 24 |
Feb 29 04:07:58 PM PST 24 |
3699329050 ps |
| T164 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1182629660 |
|
|
Feb 29 03:44:23 PM PST 24 |
Feb 29 03:52:05 PM PST 24 |
5304595950 ps |
| T722 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3980176588 |
|
|
Feb 29 03:49:24 PM PST 24 |
Feb 29 03:54:50 PM PST 24 |
3309911700 ps |
| T61 |
/workspace/coverage/default/3.chip_tap_straps_rma.2356227418 |
|
|
Feb 29 03:59:18 PM PST 24 |
Feb 29 04:01:27 PM PST 24 |
1840971450 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.3657043555 |
|
|
Feb 29 03:51:09 PM PST 24 |
Feb 29 04:17:21 PM PST 24 |
8716693800 ps |
| T720 |
/workspace/coverage/default/2.rom_raw_unlock.2146388125 |
|
|
Feb 29 03:59:04 PM PST 24 |
Feb 29 04:37:28 PM PST 24 |
15715821038 ps |
| T1222 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.141912532 |
|
|
Feb 29 03:51:35 PM PST 24 |
Feb 29 04:30:23 PM PST 24 |
26253487794 ps |
| T1223 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2950199589 |
|
|
Feb 29 04:08:11 PM PST 24 |
Feb 29 04:20:33 PM PST 24 |
4832745178 ps |
| T1224 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1497255013 |
|
|
Feb 29 03:44:58 PM PST 24 |
Feb 29 03:58:19 PM PST 24 |
4111071960 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2847805509 |
|
|
Feb 29 03:42:07 PM PST 24 |
Feb 29 03:47:42 PM PST 24 |
4791864936 ps |
| T1226 |
/workspace/coverage/default/1.chip_sw_aes_entropy.531729661 |
|
|
Feb 29 03:42:56 PM PST 24 |
Feb 29 03:47:54 PM PST 24 |
3374161648 ps |
| T807 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422389632 |
|
|
Feb 29 04:05:27 PM PST 24 |
Feb 29 04:11:57 PM PST 24 |
3968390362 ps |
| T778 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.3920749482 |
|
|
Feb 29 04:08:28 PM PST 24 |
Feb 29 04:16:10 PM PST 24 |
3475248056 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.577685677 |
|
|
Feb 29 03:59:14 PM PST 24 |
Feb 29 04:04:19 PM PST 24 |
3154489932 ps |
| T1228 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.2471607686 |
|
|
Feb 29 03:38:36 PM PST 24 |
Feb 29 04:41:46 PM PST 24 |
20478537824 ps |
| T663 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.4257497054 |
|
|
Feb 29 03:31:08 PM PST 24 |
Feb 29 03:42:35 PM PST 24 |
5936576427 ps |
| T401 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.563228030 |
|
|
Feb 29 03:34:56 PM PST 24 |
Feb 29 03:50:42 PM PST 24 |
4991007380 ps |
| T1229 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.1244659631 |
|
|
Feb 29 03:29:35 PM PST 24 |
Feb 29 03:43:15 PM PST 24 |
11061002291 ps |
| T54 |
/workspace/coverage/default/2.chip_sw_alert_test.496406728 |
|
|
Feb 29 03:54:01 PM PST 24 |
Feb 29 03:57:58 PM PST 24 |
2908014646 ps |
| T214 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.2614746393 |
|
|
Feb 29 03:53:56 PM PST 24 |
Feb 29 04:06:04 PM PST 24 |
4936694912 ps |
| T51 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2017337172 |
|
|
Feb 29 03:23:45 PM PST 24 |
Feb 29 03:40:25 PM PST 24 |
9841433661 ps |
| T1230 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.3673252439 |
|
|
Feb 29 04:02:43 PM PST 24 |
Feb 29 04:14:06 PM PST 24 |
5895838020 ps |
| T1231 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2831950436 |
|
|
Feb 29 03:56:04 PM PST 24 |
Feb 29 04:06:56 PM PST 24 |
4905672016 ps |
| T1232 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.91842082 |
|
|
Feb 29 03:45:12 PM PST 24 |
Feb 29 03:50:25 PM PST 24 |
3237545075 ps |
| T208 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2380013294 |
|
|
Feb 29 03:51:36 PM PST 24 |
Feb 29 04:01:34 PM PST 24 |
4396579372 ps |
| T50 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2319664484 |
|
|
Feb 29 03:50:53 PM PST 24 |
Feb 29 04:23:48 PM PST 24 |
20876689500 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.3162217358 |
|
|
Feb 29 03:31:00 PM PST 24 |
Feb 29 03:33:55 PM PST 24 |
2871571800 ps |
| T1234 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.455909630 |
|
|
Feb 29 03:31:20 PM PST 24 |
Feb 29 03:39:14 PM PST 24 |
4557628216 ps |
| T1235 |
/workspace/coverage/default/2.chip_sw_aes_entropy.3682427433 |
|
|
Feb 29 03:54:32 PM PST 24 |
Feb 29 03:58:47 PM PST 24 |
2664809004 ps |
| T1236 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.928744079 |
|
|
Feb 29 03:45:01 PM PST 24 |
Feb 29 03:54:40 PM PST 24 |
3768457400 ps |
| T1237 |
/workspace/coverage/default/0.chip_sw_example_rom.622513673 |
|
|
Feb 29 03:26:57 PM PST 24 |
Feb 29 03:29:10 PM PST 24 |
2588410884 ps |
| T1238 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.4256777712 |
|
|
Feb 29 03:55:40 PM PST 24 |
Feb 29 03:59:26 PM PST 24 |
2692311900 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.816636970 |
|
|
Feb 29 03:29:38 PM PST 24 |
Feb 29 04:32:08 PM PST 24 |
16822303678 ps |
| T735 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.1136254029 |
|
|
Feb 29 04:03:10 PM PST 24 |
Feb 29 04:13:26 PM PST 24 |
4514743250 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2185728332 |
|
|
Feb 29 03:39:38 PM PST 24 |
Feb 29 03:55:41 PM PST 24 |
6300432209 ps |
| T1241 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1461986008 |
|
|
Feb 29 04:00:10 PM PST 24 |
Feb 29 04:37:41 PM PST 24 |
13021740426 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2029834720 |
|
|
Feb 29 03:50:27 PM PST 24 |
Feb 29 04:07:14 PM PST 24 |
5758925900 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3367313000 |
|
|
Feb 29 03:46:00 PM PST 24 |
Feb 29 03:53:05 PM PST 24 |
6056293808 ps |
| T1243 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1219229206 |
|
|
Feb 29 03:37:31 PM PST 24 |
Feb 29 03:49:14 PM PST 24 |
4260082260 ps |
| T1244 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.848338843 |
|
|
Feb 29 03:44:55 PM PST 24 |
Feb 29 03:56:15 PM PST 24 |
4060334980 ps |
| T1245 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.1091869575 |
|
|
Feb 29 03:39:29 PM PST 24 |
Feb 29 03:41:43 PM PST 24 |
2342135116 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4112930372 |
|
|
Feb 29 03:46:14 PM PST 24 |
Feb 29 03:52:08 PM PST 24 |
5307201964 ps |
| T1247 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.1524824141 |
|
|
Feb 29 03:28:08 PM PST 24 |
Feb 29 03:43:26 PM PST 24 |
5774701754 ps |
| T1248 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.1420273346 |
|
|
Feb 29 03:40:12 PM PST 24 |
Feb 29 03:49:59 PM PST 24 |
8733037464 ps |
| T1249 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1154837104 |
|
|
Feb 29 03:53:55 PM PST 24 |
Feb 29 04:09:22 PM PST 24 |
4166588440 ps |
| T1250 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2446584709 |
|
|
Feb 29 04:08:53 PM PST 24 |
Feb 29 04:15:55 PM PST 24 |
4277276284 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.629254070 |
|
|
Feb 29 03:38:17 PM PST 24 |
Feb 29 04:23:46 PM PST 24 |
10433877324 ps |
| T302 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2148724262 |
|
|
Feb 29 03:48:55 PM PST 24 |
Feb 29 04:06:12 PM PST 24 |
4931873512 ps |
| T1252 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.686571158 |
|
|
Feb 29 03:42:02 PM PST 24 |
Feb 29 03:46:55 PM PST 24 |
3073202818 ps |
| T1253 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3865139162 |
|
|
Feb 29 04:01:20 PM PST 24 |
Feb 29 04:13:02 PM PST 24 |
4947370024 ps |
| T121 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2139276931 |
|
|
Feb 29 03:29:32 PM PST 24 |
Feb 29 03:36:24 PM PST 24 |
3917466870 ps |
| T1254 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.2641495822 |
|
|
Feb 29 03:26:35 PM PST 24 |
Feb 29 03:32:42 PM PST 24 |
6888808170 ps |
| T1255 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3377180847 |
|
|
Feb 29 03:55:29 PM PST 24 |
Feb 29 04:03:20 PM PST 24 |
3132614956 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.695368674 |
|
|
Feb 29 03:28:07 PM PST 24 |
Feb 29 03:41:01 PM PST 24 |
7269321960 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1765169730 |
|
|
Feb 29 03:41:14 PM PST 24 |
Feb 29 03:43:14 PM PST 24 |
2726044017 ps |
| T730 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.654416586 |
|
|
Feb 29 04:04:12 PM PST 24 |
Feb 29 04:12:26 PM PST 24 |
3183651748 ps |
| T165 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2633068102 |
|
|
Feb 29 03:29:22 PM PST 24 |
Feb 29 03:36:30 PM PST 24 |
4577400336 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_hmac_enc.4206904549 |
|
|
Feb 29 03:43:18 PM PST 24 |
Feb 29 03:47:35 PM PST 24 |
2964292706 ps |
| T1258 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.978182116 |
|
|
Feb 29 03:56:03 PM PST 24 |
Feb 29 04:07:01 PM PST 24 |
4815329550 ps |
| T780 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3236840213 |
|
|
Feb 29 04:08:59 PM PST 24 |
Feb 29 04:19:18 PM PST 24 |
5125139404 ps |
| T796 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.1491377778 |
|
|
Feb 29 04:08:11 PM PST 24 |
Feb 29 04:20:38 PM PST 24 |
5556575296 ps |
| T1259 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2930245097 |
|
|
Feb 29 03:39:27 PM PST 24 |
Feb 29 03:54:31 PM PST 24 |
8176336544 ps |
| T1260 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3737492865 |
|
|
Feb 29 03:43:34 PM PST 24 |
Feb 29 03:51:54 PM PST 24 |
5349252786 ps |
| T68 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.1719240643 |
|
|
Feb 29 03:27:40 PM PST 24 |
Feb 29 03:31:23 PM PST 24 |
2855735920 ps |
| T1261 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1412761115 |
|
|
Feb 29 03:40:07 PM PST 24 |
Feb 29 04:02:39 PM PST 24 |
8659121154 ps |
| T1262 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.873609290 |
|
|
Feb 29 03:26:47 PM PST 24 |
Feb 29 03:28:49 PM PST 24 |
2858274405 ps |
| T1263 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.3941840334 |
|
|
Feb 29 03:59:13 PM PST 24 |
Feb 29 04:06:17 PM PST 24 |
4139103728 ps |
| T1264 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.2323419436 |
|
|
Feb 29 03:59:24 PM PST 24 |
Feb 29 04:16:33 PM PST 24 |
5926551296 ps |
| T1265 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3853779684 |
|
|
Feb 29 03:28:23 PM PST 24 |
Feb 29 03:33:37 PM PST 24 |
3180991736 ps |
| T664 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.1558814159 |
|
|
Feb 29 03:44:39 PM PST 24 |
Feb 29 03:53:37 PM PST 24 |
5750373070 ps |
| T709 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.1679618512 |
|
|
Feb 29 03:57:40 PM PST 24 |
Feb 29 04:06:28 PM PST 24 |
3919029562 ps |
| T1266 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.2328223444 |
|
|
Feb 29 03:50:35 PM PST 24 |
Feb 29 04:28:40 PM PST 24 |
8022307708 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1147521719 |
|
|
Feb 29 03:32:08 PM PST 24 |
Feb 29 03:44:34 PM PST 24 |
5682559789 ps |
| T1267 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1096504740 |
|
|
Feb 29 03:45:40 PM PST 24 |
Feb 29 03:51:46 PM PST 24 |
4125752618 ps |
| T296 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.4035916087 |
|
|
Feb 29 03:27:18 PM PST 24 |
Feb 29 03:44:22 PM PST 24 |
5055764360 ps |
| T1268 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.916019602 |
|
|
Feb 29 03:26:47 PM PST 24 |
Feb 29 03:36:29 PM PST 24 |
4737729872 ps |
| T1269 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1972255667 |
|
|
Feb 29 03:41:46 PM PST 24 |
Feb 29 04:39:02 PM PST 24 |
23770183399 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.4051304342 |
|
|
Feb 29 03:56:09 PM PST 24 |
Feb 29 04:04:13 PM PST 24 |
6086480588 ps |
| T1270 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2651566307 |
|
|
Feb 29 04:09:39 PM PST 24 |
Feb 29 04:20:48 PM PST 24 |
5888245256 ps |
| T1271 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1544590739 |
|
|
Feb 29 04:05:03 PM PST 24 |
Feb 29 04:13:40 PM PST 24 |
5936893840 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2624583702 |
|
|
Feb 29 03:54:33 PM PST 24 |
Feb 29 03:59:30 PM PST 24 |
2559727842 ps |
| T1273 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3714529059 |
|
|
Feb 29 03:44:57 PM PST 24 |
Feb 29 03:56:40 PM PST 24 |
4288934812 ps |
| T617 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2241389689 |
|
|
Feb 29 03:31:39 PM PST 24 |
Feb 29 03:39:23 PM PST 24 |
4052348215 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_aes_idle.3187260144 |
|
|
Feb 29 03:42:19 PM PST 24 |
Feb 29 03:47:23 PM PST 24 |
3172925596 ps |
| T711 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.371447848 |
|
|
Feb 29 03:48:59 PM PST 24 |
Feb 29 04:02:45 PM PST 24 |
4639639244 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.299364296 |
|
|
Feb 29 03:41:35 PM PST 24 |
Feb 29 04:40:55 PM PST 24 |
21049940173 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3268307779 |
|
|
Feb 29 03:29:28 PM PST 24 |
Feb 29 03:39:45 PM PST 24 |
5260859284 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.3805879447 |
|
|
Feb 29 03:28:36 PM PST 24 |
Feb 29 03:38:44 PM PST 24 |
6722981696 ps |
| T1278 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.2941913980 |
|
|
Feb 29 03:27:49 PM PST 24 |
Feb 29 03:45:31 PM PST 24 |
5429739529 ps |
| T1279 |
/workspace/coverage/default/2.chip_sw_aes_enc.332499037 |
|
|
Feb 29 03:53:27 PM PST 24 |
Feb 29 03:57:15 PM PST 24 |
2561083072 ps |
| T1280 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3416249255 |
|
|
Feb 29 04:07:57 PM PST 24 |
Feb 29 04:14:15 PM PST 24 |
3307578196 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1429568480 |
|
|
Feb 29 03:32:04 PM PST 24 |
Feb 29 03:34:51 PM PST 24 |
2862128456 ps |
| T1282 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2266151426 |
|
|
Feb 29 03:47:34 PM PST 24 |
Feb 29 03:52:15 PM PST 24 |
2848984546 ps |
| T1283 |
/workspace/coverage/default/2.chip_sw_edn_kat.1985408858 |
|
|
Feb 29 03:53:17 PM PST 24 |
Feb 29 04:03:33 PM PST 24 |
3604930210 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3258065040 |
|
|
Feb 29 03:54:39 PM PST 24 |
Feb 29 04:23:34 PM PST 24 |
8255165760 ps |
| T1285 |
/workspace/coverage/default/1.chip_sw_rv_timer_smoketest.2379231262 |
|
|
Feb 29 03:48:13 PM PST 24 |
Feb 29 03:52:09 PM PST 24 |
2382782920 ps |
| T1286 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.46166068 |
|
|
Feb 29 03:48:12 PM PST 24 |
Feb 29 03:51:03 PM PST 24 |
2644257190 ps |
| T1287 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.2390395363 |
|
|
Feb 29 03:38:42 PM PST 24 |
Feb 29 04:04:18 PM PST 24 |
8475829982 ps |
| T1288 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.649937051 |
|
|
Feb 29 04:01:39 PM PST 24 |
Feb 29 04:17:45 PM PST 24 |
8867790330 ps |
| T1289 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.1413067881 |
|
|
Feb 29 03:51:05 PM PST 24 |
Feb 29 04:09:14 PM PST 24 |
5342586852 ps |
| T1290 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3755353161 |
|
|
Feb 29 03:31:29 PM PST 24 |
Feb 29 03:41:16 PM PST 24 |
5355182216 ps |
| T1291 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1460420130 |
|
|
Feb 29 03:30:16 PM PST 24 |
Feb 29 03:55:32 PM PST 24 |
7084954296 ps |
| T770 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3136098597 |
|
|
Feb 29 04:04:51 PM PST 24 |
Feb 29 04:11:05 PM PST 24 |
2852307216 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_gpio.776929862 |
|
|
Feb 29 03:28:18 PM PST 24 |
Feb 29 03:35:45 PM PST 24 |
4262674806 ps |
| T622 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2282173917 |
|
|
Feb 29 03:43:19 PM PST 24 |
Feb 29 03:54:00 PM PST 24 |
5867412654 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1644231826 |
|
|
Feb 29 03:40:29 PM PST 24 |
Feb 29 03:51:47 PM PST 24 |
5384979912 ps |
| T1293 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1507275584 |
|
|
Feb 29 03:54:47 PM PST 24 |
Feb 29 04:48:00 PM PST 24 |
13683481670 ps |
| T1294 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2650258873 |
|
|
Feb 29 03:46:27 PM PST 24 |
Feb 29 03:54:21 PM PST 24 |
4033920322 ps |
| T1295 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1868286918 |
|
|
Feb 29 03:38:06 PM PST 24 |
Feb 29 07:19:54 PM PST 24 |
78404393600 ps |
| T758 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.2423166561 |
|
|
Feb 29 04:01:45 PM PST 24 |
Feb 29 04:06:52 PM PST 24 |
3530905458 ps |
| T717 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.3766050873 |
|
|
Feb 29 03:53:16 PM PST 24 |
Feb 29 04:05:29 PM PST 24 |
4626949532 ps |
| T1296 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.1977662876 |
|
|
Feb 29 03:40:43 PM PST 24 |
Feb 29 03:49:52 PM PST 24 |
8327914384 ps |
| T767 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.944322454 |
|
|
Feb 29 04:08:35 PM PST 24 |
Feb 29 04:17:39 PM PST 24 |
5639408750 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3720578414 |
|
|
Feb 29 03:42:05 PM PST 24 |
Feb 29 07:29:21 PM PST 24 |
255448884988 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3337579333 |
|
|
Feb 29 03:55:28 PM PST 24 |
Feb 29 04:04:56 PM PST 24 |
4583213570 ps |
| T1299 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.1757182447 |
|
|
Feb 29 04:01:40 PM PST 24 |
Feb 29 04:05:33 PM PST 24 |
2841342920 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_example_concurrency.3757235941 |
|
|
Feb 29 03:38:43 PM PST 24 |
Feb 29 03:43:00 PM PST 24 |
2893104404 ps |
| T295 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.3512508438 |
|
|
Feb 29 03:31:31 PM PST 24 |
Feb 29 03:52:36 PM PST 24 |
6045544328 ps |
| T1301 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.812062082 |
|
|
Feb 29 03:51:24 PM PST 24 |
Feb 29 04:10:18 PM PST 24 |
6350846004 ps |
| T1302 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1551319224 |
|
|
Feb 29 03:28:13 PM PST 24 |
Feb 29 04:58:33 PM PST 24 |
46872230166 ps |
| T1303 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2778879101 |
|
|
Feb 29 03:27:42 PM PST 24 |
Feb 29 03:42:15 PM PST 24 |
7176261289 ps |
| T1304 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.97590460 |
|
|
Feb 29 03:28:40 PM PST 24 |
Feb 29 03:36:51 PM PST 24 |
4752291854 ps |
| T1305 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.496261176 |
|
|
Feb 29 03:58:53 PM PST 24 |
Feb 29 04:02:28 PM PST 24 |
2643938472 ps |
| T1306 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1581555444 |
|
|
Feb 29 03:37:25 PM PST 24 |
Feb 29 03:52:51 PM PST 24 |
6077041792 ps |
| T712 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.1481978251 |
|
|
Feb 29 03:40:07 PM PST 24 |
Feb 29 03:52:49 PM PST 24 |
4588832294 ps |
| T779 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.2824616828 |
|
|
Feb 29 04:03:12 PM PST 24 |
Feb 29 04:11:47 PM PST 24 |
4679314660 ps |
| T1307 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1384050637 |
|
|
Feb 29 03:33:49 PM PST 24 |
Feb 29 04:10:36 PM PST 24 |
27785774472 ps |
| T773 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3830193232 |
|
|
Feb 29 04:05:22 PM PST 24 |
Feb 29 04:13:51 PM PST 24 |
3503533232 ps |
| T1308 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2418219657 |
|
|
Feb 29 03:58:03 PM PST 24 |
Feb 29 04:09:17 PM PST 24 |
5405028823 ps |
| T1309 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1248229500 |
|
|
Feb 29 03:29:56 PM PST 24 |
Feb 29 03:38:57 PM PST 24 |
3989909380 ps |
| T47 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.470077838 |
|
|
Feb 29 03:49:50 PM PST 24 |
Feb 29 03:55:15 PM PST 24 |
2864324510 ps |
| T1310 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1729292232 |
|
|
Feb 29 04:08:36 PM PST 24 |
Feb 29 04:18:45 PM PST 24 |
5170503536 ps |
| T1311 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.3601007815 |
|
|
Feb 29 04:09:29 PM PST 24 |
Feb 29 04:21:13 PM PST 24 |
5056401200 ps |
| T1312 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.620270034 |
|
|
Feb 29 03:42:49 PM PST 24 |
Feb 29 03:47:33 PM PST 24 |
2675057672 ps |
| T1313 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.2694841404 |
|
|
Feb 29 03:46:10 PM PST 24 |
Feb 29 04:05:43 PM PST 24 |
5792158114 ps |
| T1314 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.3586889156 |
|
|
Feb 29 03:42:19 PM PST 24 |
Feb 29 03:48:04 PM PST 24 |
3829068508 ps |
| T1315 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.231271461 |
|
|
Feb 29 03:48:55 PM PST 24 |
Feb 29 03:52:44 PM PST 24 |
2665764264 ps |
| T245 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.4238680153 |
|
|
Feb 29 04:02:17 PM PST 24 |
Feb 29 04:15:17 PM PST 24 |
5554740440 ps |
| T1316 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.3670934402 |
|
|
Feb 29 03:50:03 PM PST 24 |
Feb 29 04:09:42 PM PST 24 |
4787422948 ps |
| T246 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2434770399 |
|
|
Feb 29 04:06:33 PM PST 24 |
Feb 29 04:18:26 PM PST 24 |
5964783932 ps |
| T797 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.3779618090 |
|
|
Feb 29 04:13:03 PM PST 24 |
Feb 29 04:23:32 PM PST 24 |
6014640744 ps |
| T1317 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2933567195 |
|
|
Feb 29 03:28:13 PM PST 24 |
Feb 29 03:29:58 PM PST 24 |
2469622627 ps |
| T1318 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.2718695716 |
|
|
Feb 29 04:10:06 PM PST 24 |
Feb 29 04:22:43 PM PST 24 |
6014832120 ps |
| T1319 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.2804147147 |
|
|
Feb 29 03:39:34 PM PST 24 |
Feb 29 04:23:53 PM PST 24 |
9994807082 ps |
| T1320 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1651710443 |
|
|
Feb 29 03:57:36 PM PST 24 |
Feb 29 04:02:00 PM PST 24 |
3175361475 ps |
| T69 |
/workspace/coverage/cover_reg_top/84.xbar_error_random.2762745622 |
|
|
Feb 29 04:26:10 PM PST 24 |
Feb 29 04:27:13 PM PST 24 |
1745238718 ps |
| T118 |
/workspace/coverage/cover_reg_top/3.chip_same_csr_outstanding.1716551297 |
|
|
Feb 29 04:07:00 PM PST 24 |
Feb 29 05:01:00 PM PST 24 |
29853042124 ps |
| T70 |
/workspace/coverage/cover_reg_top/64.xbar_random_zero_delays.1226989930 |
|
|
Feb 29 04:22:42 PM PST 24 |
Feb 29 04:23:09 PM PST 24 |
268163843 ps |
| T71 |
/workspace/coverage/cover_reg_top/58.xbar_smoke_zero_delays.757708886 |
|
|
Feb 29 04:21:34 PM PST 24 |
Feb 29 04:21:41 PM PST 24 |
42069058 ps |
| T111 |
/workspace/coverage/cover_reg_top/56.xbar_smoke.3944098685 |
|
|
Feb 29 04:21:34 PM PST 24 |
Feb 29 04:21:41 PM PST 24 |
39714829 ps |
| T484 |
/workspace/coverage/cover_reg_top/96.xbar_smoke_zero_delays.3177173506 |
|
|
Feb 29 04:28:08 PM PST 24 |
Feb 29 04:28:15 PM PST 24 |
55004897 ps |
| T491 |
/workspace/coverage/cover_reg_top/26.xbar_smoke.1240253599 |
|
|
Feb 29 04:15:50 PM PST 24 |
Feb 29 04:15:57 PM PST 24 |
42672611 ps |
| T211 |
/workspace/coverage/cover_reg_top/32.xbar_same_source.1271294155 |
|
|
Feb 29 04:17:20 PM PST 24 |
Feb 29 04:17:53 PM PST 24 |
1007843167 ps |
| T233 |
/workspace/coverage/cover_reg_top/7.xbar_random_zero_delays.1183403335 |
|
|
Feb 29 04:09:24 PM PST 24 |
Feb 29 04:09:50 PM PST 24 |
250806270 ps |
| T490 |
/workspace/coverage/cover_reg_top/53.xbar_random_zero_delays.2515093221 |
|
|
Feb 29 04:20:53 PM PST 24 |
Feb 29 04:21:04 PM PST 24 |
101343163 ps |
| T232 |
/workspace/coverage/cover_reg_top/1.xbar_smoke_large_delays.3246530531 |
|
|
Feb 29 04:04:58 PM PST 24 |
Feb 29 04:06:55 PM PST 24 |
11187005743 ps |
| T485 |
/workspace/coverage/cover_reg_top/63.xbar_random.1185689590 |
|
|
Feb 29 04:22:30 PM PST 24 |
Feb 29 04:24:07 PM PST 24 |
2373278829 ps |
| T493 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_slow_rsp.192435547 |
|
|
Feb 29 04:03:27 PM PST 24 |
Feb 29 04:04:43 PM PST 24 |
4241221220 ps |
| T396 |
/workspace/coverage/cover_reg_top/98.xbar_stress_all_with_reset_error.2708012673 |
|
|
Feb 29 04:28:39 PM PST 24 |
Feb 29 04:32:52 PM PST 24 |
779227502 ps |
| T428 |
/workspace/coverage/cover_reg_top/60.xbar_smoke_slow_rsp.2823890335 |
|
|
Feb 29 04:21:55 PM PST 24 |
Feb 29 04:23:18 PM PST 24 |
4708592690 ps |
| T397 |
/workspace/coverage/cover_reg_top/65.xbar_stress_all_with_error.1675840737 |
|
|
Feb 29 04:23:01 PM PST 24 |
Feb 29 04:34:36 PM PST 24 |
17280525948 ps |
| T851 |
/workspace/coverage/cover_reg_top/2.chip_csr_bit_bash.165500031 |
|
|
Feb 29 04:05:48 PM PST 24 |
Feb 29 04:17:27 PM PST 24 |
6545038580 ps |
| T494 |
/workspace/coverage/cover_reg_top/19.xbar_random_slow_rsp.4154174906 |
|
|
Feb 29 04:14:07 PM PST 24 |
Feb 29 04:14:32 PM PST 24 |
1457071773 ps |
| T366 |
/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.3416450276 |
|
|
Feb 29 04:26:34 PM PST 24 |
Feb 29 04:31:41 PM PST 24 |
7977820879 ps |
| T363 |
/workspace/coverage/cover_reg_top/41.xbar_stress_all.638917949 |
|
|
Feb 29 04:18:54 PM PST 24 |
Feb 29 04:23:10 PM PST 24 |
6203639831 ps |
| T488 |
/workspace/coverage/cover_reg_top/39.xbar_error_random.261298900 |
|
|
Feb 29 04:18:36 PM PST 24 |
Feb 29 04:19:40 PM PST 24 |
1689177589 ps |
| T482 |
/workspace/coverage/cover_reg_top/99.xbar_error_random.3854989946 |
|
|
Feb 29 04:28:52 PM PST 24 |
Feb 29 04:29:25 PM PST 24 |
417136758 ps |
| T492 |
/workspace/coverage/cover_reg_top/64.xbar_stress_all_with_reset_error.1470943405 |
|
|
Feb 29 04:22:47 PM PST 24 |
Feb 29 04:23:35 PM PST 24 |
180495160 ps |
| T496 |
/workspace/coverage/cover_reg_top/31.xbar_smoke_zero_delays.1995245862 |
|
|
Feb 29 04:16:51 PM PST 24 |
Feb 29 04:16:58 PM PST 24 |
52317266 ps |
| T489 |
/workspace/coverage/cover_reg_top/45.xbar_error_random.1906651138 |
|
|
Feb 29 04:19:39 PM PST 24 |
Feb 29 04:20:10 PM PST 24 |
784141671 ps |
| T497 |
/workspace/coverage/cover_reg_top/22.xbar_smoke_zero_delays.943819083 |
|
|
Feb 29 04:14:53 PM PST 24 |
Feb 29 04:14:59 PM PST 24 |
55240874 ps |
| T483 |
/workspace/coverage/cover_reg_top/14.chip_tl_errors.1305810816 |
|
|
Feb 29 04:12:47 PM PST 24 |
Feb 29 04:15:33 PM PST 24 |
2884400230 ps |
| T487 |
/workspace/coverage/cover_reg_top/65.xbar_access_same_device_slow_rsp.1881088999 |
|
|
Feb 29 04:22:52 PM PST 24 |
Feb 29 05:00:13 PM PST 24 |
127896586305 ps |
| T495 |
/workspace/coverage/cover_reg_top/78.xbar_access_same_device_slow_rsp.4062776750 |
|
|
Feb 29 04:24:56 PM PST 24 |
Feb 29 05:06:19 PM PST 24 |
140899749199 ps |
| T354 |
/workspace/coverage/cover_reg_top/42.xbar_access_same_device_slow_rsp.2492512279 |
|
|
Feb 29 04:19:04 PM PST 24 |
Feb 29 04:54:04 PM PST 24 |
121324477413 ps |
| T528 |
/workspace/coverage/cover_reg_top/12.xbar_same_source.3358631450 |
|
|
Feb 29 04:11:43 PM PST 24 |
Feb 29 04:12:43 PM PST 24 |
1755549069 ps |
| T646 |
/workspace/coverage/cover_reg_top/13.xbar_error_random.3935556341 |
|
|
Feb 29 04:12:14 PM PST 24 |
Feb 29 04:13:02 PM PST 24 |
582104986 ps |
| T868 |
/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_reset_error.2228466964 |
|
|
Feb 29 04:24:59 PM PST 24 |
Feb 29 04:25:21 PM PST 24 |
83368444 ps |
| T469 |
/workspace/coverage/cover_reg_top/22.xbar_same_source.1637878984 |
|
|
Feb 29 04:15:06 PM PST 24 |
Feb 29 04:15:41 PM PST 24 |
1006443323 ps |
| T486 |
/workspace/coverage/cover_reg_top/27.xbar_stress_all_with_error.1150686196 |
|
|
Feb 29 04:16:24 PM PST 24 |
Feb 29 04:28:06 PM PST 24 |
16596851672 ps |
| T596 |
/workspace/coverage/cover_reg_top/77.xbar_smoke_zero_delays.2623511728 |
|
|
Feb 29 04:24:53 PM PST 24 |
Feb 29 04:24:59 PM PST 24 |
37316486 ps |
| T818 |
/workspace/coverage/cover_reg_top/78.xbar_access_same_device.566885743 |
|
|
Feb 29 04:25:12 PM PST 24 |
Feb 29 04:26:17 PM PST 24 |
1028123312 ps |
| T412 |
/workspace/coverage/cover_reg_top/44.xbar_unmapped_addr.999099643 |
|
|
Feb 29 04:19:27 PM PST 24 |
Feb 29 04:20:24 PM PST 24 |
1284391226 ps |
| T473 |
/workspace/coverage/cover_reg_top/92.xbar_random_zero_delays.4135729849 |
|
|
Feb 29 04:27:33 PM PST 24 |
Feb 29 04:28:09 PM PST 24 |
391888502 ps |
| T649 |
/workspace/coverage/cover_reg_top/77.xbar_error_and_unmapped_addr.3902306975 |
|
|
Feb 29 04:24:55 PM PST 24 |
Feb 29 04:25:13 PM PST 24 |
134274727 ps |
| T365 |
/workspace/coverage/cover_reg_top/82.xbar_random_large_delays.1239773565 |
|
|
Feb 29 04:25:53 PM PST 24 |
Feb 29 04:35:26 PM PST 24 |
50149295912 ps |
| T592 |
/workspace/coverage/cover_reg_top/58.xbar_unmapped_addr.10895054 |
|
|
Feb 29 04:21:44 PM PST 24 |
Feb 29 04:22:19 PM PST 24 |
749512891 ps |
| T504 |
/workspace/coverage/cover_reg_top/89.xbar_random.1035593313 |
|
|
Feb 29 04:26:59 PM PST 24 |
Feb 29 04:27:42 PM PST 24 |
428409387 ps |
| T685 |
/workspace/coverage/cover_reg_top/41.xbar_random.1465151000 |
|
|
Feb 29 04:18:52 PM PST 24 |
Feb 29 04:19:00 PM PST 24 |
90231072 ps |
| T834 |
/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_reset_error.353545886 |
|
|
Feb 29 04:20:22 PM PST 24 |
Feb 29 04:23:41 PM PST 24 |
1751087933 ps |
| T371 |
/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_rand_reset.1421421045 |
|
|
Feb 29 04:15:28 PM PST 24 |
Feb 29 04:21:45 PM PST 24 |
5995357402 ps |
| T1321 |
/workspace/coverage/cover_reg_top/57.xbar_error_random.4243889165 |
|
|
Feb 29 04:21:35 PM PST 24 |
Feb 29 04:21:44 PM PST 24 |
137794583 ps |
| T561 |
/workspace/coverage/cover_reg_top/78.xbar_same_source.3514914491 |
|
|
Feb 29 04:24:57 PM PST 24 |
Feb 29 04:25:32 PM PST 24 |
1092368701 ps |
| T1322 |
/workspace/coverage/cover_reg_top/14.xbar_error_and_unmapped_addr.3265183959 |
|
|
Feb 29 04:12:55 PM PST 24 |
Feb 29 04:13:06 PM PST 24 |
132491610 ps |
| T442 |
/workspace/coverage/cover_reg_top/37.xbar_random_slow_rsp.2093899079 |
|
|
Feb 29 04:18:12 PM PST 24 |
Feb 29 04:32:26 PM PST 24 |
45895301846 ps |
| T1323 |
/workspace/coverage/cover_reg_top/57.xbar_smoke_slow_rsp.2014537444 |
|
|
Feb 29 04:21:33 PM PST 24 |
Feb 29 04:23:06 PM PST 24 |
4864623040 ps |
| T643 |
/workspace/coverage/cover_reg_top/44.xbar_smoke_zero_delays.3293926421 |
|
|
Feb 29 04:19:17 PM PST 24 |
Feb 29 04:19:24 PM PST 24 |
48116075 ps |
| T364 |
/workspace/coverage/cover_reg_top/67.xbar_unmapped_addr.1555876208 |
|
|
Feb 29 04:23:19 PM PST 24 |
Feb 29 04:24:19 PM PST 24 |
1259241547 ps |
| T684 |
/workspace/coverage/cover_reg_top/32.xbar_smoke_large_delays.585577714 |
|
|
Feb 29 04:17:03 PM PST 24 |
Feb 29 04:18:35 PM PST 24 |
8354604837 ps |