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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
95.91 95.21 93.87 95.03 94.38 97.38 99.58


Total test records in report: 2847
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T1023 /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3053554 Feb 29 03:50:21 PM PST 24 Feb 29 04:40:59 PM PST 24 23486141046 ps
T1024 /workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.912180520 Feb 29 03:51:11 PM PST 24 Feb 29 04:20:19 PM PST 24 11125274123 ps
T1025 /workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3730516230 Feb 29 03:37:40 PM PST 24 Feb 29 03:41:55 PM PST 24 2218928720 ps
T1026 /workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1659310335 Feb 29 03:40:57 PM PST 24 Feb 29 03:46:07 PM PST 24 3236277494 ps
T1027 /workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.2546765855 Feb 29 03:39:43 PM PST 24 Feb 29 04:07:35 PM PST 24 6355754359 ps
T1028 /workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.2075312361 Feb 29 03:43:18 PM PST 24 Feb 29 03:57:34 PM PST 24 7182692220 ps
T1029 /workspace/coverage/default/0.chip_sw_rstmgr_sw_req.3110658479 Feb 29 03:28:14 PM PST 24 Feb 29 03:34:22 PM PST 24 4625728700 ps
T1030 /workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.19853309 Feb 29 03:41:01 PM PST 24 Feb 29 04:30:41 PM PST 24 36901950198 ps
T1031 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.185938199 Feb 29 03:27:34 PM PST 24 Feb 29 04:33:28 PM PST 24 18325287387 ps
T1032 /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1267913617 Feb 29 03:29:45 PM PST 24 Feb 29 03:39:55 PM PST 24 4697972068 ps
T1033 /workspace/coverage/default/0.chip_sw_csrng_kat_test.1440471449 Feb 29 03:28:20 PM PST 24 Feb 29 03:32:34 PM PST 24 2517739448 ps
T1034 /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.3832050027 Feb 29 03:31:51 PM PST 24 Feb 29 03:38:02 PM PST 24 5024412286 ps
T1035 /workspace/coverage/default/1.chip_sw_entropy_src_smoketest.2876282774 Feb 29 03:47:56 PM PST 24 Feb 29 03:56:20 PM PST 24 3272206858 ps
T692 /workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.3679072434 Feb 29 03:29:20 PM PST 24 Feb 29 03:33:29 PM PST 24 2915434550 ps
T120 /workspace/coverage/default/1.chip_plic_all_irqs_10.3626589113 Feb 29 03:43:26 PM PST 24 Feb 29 03:52:24 PM PST 24 4099376560 ps
T1036 /workspace/coverage/default/2.chip_sw_kmac_entropy.2970931731 Feb 29 03:50:24 PM PST 24 Feb 29 03:55:23 PM PST 24 3497093414 ps
T1037 /workspace/coverage/default/1.chip_tap_straps_prod.3413211327 Feb 29 03:44:27 PM PST 24 Feb 29 04:06:33 PM PST 24 13194936501 ps
T1038 /workspace/coverage/default/1.chip_sw_flash_ctrl_ops.321546561 Feb 29 03:42:18 PM PST 24 Feb 29 03:57:12 PM PST 24 5171937132 ps
T303 /workspace/coverage/default/0.chip_sw_pattgen_ios.2141450779 Feb 29 03:27:31 PM PST 24 Feb 29 03:30:41 PM PST 24 2553926288 ps
T1039 /workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.2278085819 Feb 29 03:50:23 PM PST 24 Feb 29 04:01:17 PM PST 24 9078235090 ps
T1040 /workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1246384449 Feb 29 03:39:22 PM PST 24 Feb 29 04:03:01 PM PST 24 9676653320 ps
T813 /workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.2737550350 Feb 29 03:54:32 PM PST 24 Feb 29 04:00:11 PM PST 24 3225761202 ps
T44 /workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.4040450689 Feb 29 03:50:54 PM PST 24 Feb 29 03:57:05 PM PST 24 4598945816 ps
T241 /workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.4165523840 Feb 29 03:43:16 PM PST 24 Feb 29 04:03:23 PM PST 24 10342814630 ps
T1041 /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.770033221 Feb 29 03:37:26 PM PST 24 Feb 29 03:40:22 PM PST 24 2870519148 ps
T1042 /workspace/coverage/default/1.chip_sw_alert_handler_escalation.3301045455 Feb 29 03:42:03 PM PST 24 Feb 29 03:52:05 PM PST 24 4830145002 ps
T227 /workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.742984087 Feb 29 03:40:05 PM PST 24 Feb 29 03:47:45 PM PST 24 6562438848 ps
T790 /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128882525 Feb 29 04:09:24 PM PST 24 Feb 29 04:15:57 PM PST 24 3988398858 ps
T1043 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3529492336 Feb 29 03:39:00 PM PST 24 Feb 29 04:32:54 PM PST 24 11755107438 ps
T1044 /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3212753797 Feb 29 04:00:52 PM PST 24 Feb 29 04:09:32 PM PST 24 5341121292 ps
T1045 /workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1000562971 Feb 29 03:29:24 PM PST 24 Feb 29 03:47:16 PM PST 24 5305486986 ps
T736 /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.703928122 Feb 29 04:09:28 PM PST 24 Feb 29 04:15:44 PM PST 24 3603437880 ps
T140 /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1832661188 Feb 29 03:26:37 PM PST 24 Feb 29 03:28:36 PM PST 24 2648866237 ps
T724 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3812889078 Feb 29 03:29:28 PM PST 24 Feb 29 03:35:08 PM PST 24 4701683212 ps
T67 /workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2947773163 Feb 29 03:27:43 PM PST 24 Feb 29 03:35:15 PM PST 24 2953657800 ps
T1046 /workspace/coverage/default/1.chip_tap_straps_testunlock0.1319478743 Feb 29 03:45:00 PM PST 24 Feb 29 03:56:51 PM PST 24 6713250767 ps
T1047 /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.2333321866 Feb 29 03:31:42 PM PST 24 Feb 29 03:36:51 PM PST 24 2772822424 ps
T1048 /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.36859140 Feb 29 04:03:21 PM PST 24 Feb 29 04:11:40 PM PST 24 3621834380 ps
T1049 /workspace/coverage/default/58.chip_sw_all_escalation_resets.1829214467 Feb 29 04:11:07 PM PST 24 Feb 29 04:19:28 PM PST 24 4975200866 ps
T756 /workspace/coverage/default/24.chip_sw_all_escalation_resets.967753680 Feb 29 04:02:22 PM PST 24 Feb 29 04:10:46 PM PST 24 3788403848 ps
T1050 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1195774012 Feb 29 03:51:55 PM PST 24 Feb 29 03:56:06 PM PST 24 2582313723 ps
T811 /workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.765017069 Feb 29 04:02:20 PM PST 24 Feb 29 04:09:08 PM PST 24 3719784952 ps
T1051 /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3372469574 Feb 29 03:29:37 PM PST 24 Feb 29 04:35:36 PM PST 24 10821361838 ps
T1052 /workspace/coverage/default/1.rom_e2e_asm_init_prod.2168524226 Feb 29 03:52:30 PM PST 24 Feb 29 04:31:30 PM PST 24 8729593288 ps
T481 /workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3881789030 Feb 29 03:29:59 PM PST 24 Feb 29 03:43:20 PM PST 24 4206042006 ps
T35 /workspace/coverage/default/1.chip_sw_spi_device_tpm.1956947112 Feb 29 03:40:36 PM PST 24 Feb 29 03:49:02 PM PST 24 3597389951 ps
T1053 /workspace/coverage/default/0.chip_sw_entropy_src_kat_test.3221147951 Feb 29 03:29:49 PM PST 24 Feb 29 03:33:30 PM PST 24 2661535352 ps
T1054 /workspace/coverage/default/93.chip_sw_all_escalation_resets.2428533428 Feb 29 04:10:03 PM PST 24 Feb 29 04:17:39 PM PST 24 4140070480 ps
T1055 /workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.807392889 Feb 29 03:40:37 PM PST 24 Feb 29 05:24:54 PM PST 24 51023773903 ps
T1056 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.946381793 Feb 29 03:51:16 PM PST 24 Feb 29 03:55:35 PM PST 24 3386191837 ps
T798 /workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2640501994 Feb 29 04:04:53 PM PST 24 Feb 29 04:11:16 PM PST 24 2902575258 ps
T1057 /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1224393262 Feb 29 04:08:10 PM PST 24 Feb 29 04:17:04 PM PST 24 4011371668 ps
T318 /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3925629620 Feb 29 03:32:03 PM PST 24 Feb 29 03:38:32 PM PST 24 2922773454 ps
T1058 /workspace/coverage/default/0.rom_e2e_smoke.544478316 Feb 29 03:34:22 PM PST 24 Feb 29 04:07:39 PM PST 24 8630548792 ps
T1059 /workspace/coverage/default/2.chip_sw_kmac_smoketest.3017061343 Feb 29 03:58:30 PM PST 24 Feb 29 04:05:43 PM PST 24 2982246362 ps
T1060 /workspace/coverage/default/2.chip_sw_clkmgr_smoketest.1495100384 Feb 29 03:58:06 PM PST 24 Feb 29 04:01:53 PM PST 24 2245787558 ps
T1061 /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.416282730 Feb 29 03:28:43 PM PST 24 Feb 29 03:38:41 PM PST 24 5912471528 ps
T1062 /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.774994790 Feb 29 04:04:51 PM PST 24 Feb 29 04:11:30 PM PST 24 4031306034 ps
T112 /workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2077042496 Feb 29 03:50:05 PM PST 24 Feb 29 06:51:12 PM PST 24 59473228758 ps
T737 /workspace/coverage/default/17.chip_sw_all_escalation_resets.1211623277 Feb 29 04:02:38 PM PST 24 Feb 29 04:15:08 PM PST 24 5876260060 ps
T1063 /workspace/coverage/default/0.chip_sw_aes_smoketest.3730338723 Feb 29 03:36:45 PM PST 24 Feb 29 03:41:35 PM PST 24 3265322110 ps
T400 /workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.688495766 Feb 29 03:38:24 PM PST 24 Feb 29 03:46:40 PM PST 24 3969265422 ps
T1064 /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.2931451751 Feb 29 04:02:01 PM PST 24 Feb 29 04:15:12 PM PST 24 5118657047 ps
T801 /workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1953648850 Feb 29 04:02:57 PM PST 24 Feb 29 04:08:43 PM PST 24 3287278720 ps
T21 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3785110276 Feb 29 03:28:04 PM PST 24 Feb 29 03:54:26 PM PST 24 23096453300 ps
T1065 /workspace/coverage/default/2.chip_sw_flash_ctrl_access.2664485153 Feb 29 03:49:04 PM PST 24 Feb 29 04:05:47 PM PST 24 5291521300 ps
T653 /workspace/coverage/default/0.chip_sw_edn_auto_mode.1602934331 Feb 29 03:31:14 PM PST 24 Feb 29 03:59:27 PM PST 24 5525553000 ps
T754 /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3062545515 Feb 29 04:02:08 PM PST 24 Feb 29 04:11:18 PM PST 24 3967492904 ps
T27 /workspace/coverage/default/2.chip_sw_gpio.1040318633 Feb 29 03:49:39 PM PST 24 Feb 29 03:56:38 PM PST 24 3730758658 ps
T1066 /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.1527446204 Feb 29 04:01:26 PM PST 24 Feb 29 05:11:32 PM PST 24 22939655004 ps
T806 /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.4259429659 Feb 29 04:01:28 PM PST 24 Feb 29 04:08:00 PM PST 24 3845101240 ps
T316 /workspace/coverage/default/0.chip_sival_flash_info_access.1629293190 Feb 29 03:32:22 PM PST 24 Feb 29 03:41:59 PM PST 24 3483460344 ps
T1067 /workspace/coverage/default/1.chip_sw_uart_smoketest.1280678334 Feb 29 03:49:01 PM PST 24 Feb 29 03:54:06 PM PST 24 3247272380 ps
T1068 /workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2663179093 Feb 29 03:54:52 PM PST 24 Feb 29 04:04:47 PM PST 24 4956017046 ps
T1069 /workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.1056359624 Feb 29 03:40:08 PM PST 24 Feb 29 05:13:27 PM PST 24 46620819802 ps
T654 /workspace/coverage/default/2.chip_sw_edn_auto_mode.840010873 Feb 29 03:54:56 PM PST 24 Feb 29 04:25:10 PM PST 24 7826533200 ps
T765 /workspace/coverage/default/5.chip_sw_all_escalation_resets.724018574 Feb 29 04:00:40 PM PST 24 Feb 29 04:12:30 PM PST 24 4381051782 ps
T723 /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2428004700 Feb 29 03:51:55 PM PST 24 Feb 29 04:27:01 PM PST 24 23347089256 ps
T1070 /workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.269380420 Feb 29 03:44:55 PM PST 24 Feb 29 03:58:15 PM PST 24 5018372032 ps
T1071 /workspace/coverage/default/10.chip_sw_lc_ctrl_transition.133097947 Feb 29 04:00:39 PM PST 24 Feb 29 04:09:52 PM PST 24 6442638785 ps
T1072 /workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.2410180910 Feb 29 03:39:18 PM PST 24 Feb 29 04:11:27 PM PST 24 6863196160 ps
T729 /workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.2878903633 Feb 29 03:28:09 PM PST 24 Feb 29 04:26:55 PM PST 24 20212384779 ps
T1073 /workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3553124099 Feb 29 03:42:49 PM PST 24 Feb 29 03:52:29 PM PST 24 5762140396 ps
T323 /workspace/coverage/default/2.chip_sw_edn_boot_mode.2204683998 Feb 29 03:52:55 PM PST 24 Feb 29 04:04:35 PM PST 24 2901289368 ps
T1074 /workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.3189721653 Feb 29 03:57:10 PM PST 24 Feb 29 04:00:59 PM PST 24 2850994982 ps
T207 /workspace/coverage/default/1.chip_sw_spi_device_pass_through.2284358537 Feb 29 03:38:26 PM PST 24 Feb 29 03:49:14 PM PST 24 6010135864 ps
T1075 /workspace/coverage/default/2.chip_sw_aes_masking_off.3757074101 Feb 29 03:52:16 PM PST 24 Feb 29 03:58:05 PM PST 24 3023030023 ps
T1076 /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2567113280 Feb 29 03:31:20 PM PST 24 Feb 29 03:54:00 PM PST 24 5948023672 ps
T1077 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3911351874 Feb 29 03:38:05 PM PST 24 Feb 29 04:12:01 PM PST 24 9030942642 ps
T1078 /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.806450079 Feb 29 04:00:30 PM PST 24 Feb 29 04:19:42 PM PST 24 13279788647 ps
T799 /workspace/coverage/default/90.chip_sw_all_escalation_resets.2405359565 Feb 29 04:11:02 PM PST 24 Feb 29 04:22:58 PM PST 24 5185972080 ps
T113 /workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2412734108 Feb 29 03:39:35 PM PST 24 Feb 29 06:40:12 PM PST 24 59509259286 ps
T1079 /workspace/coverage/default/1.rom_e2e_shutdown_exception_c.4264962011 Feb 29 03:50:57 PM PST 24 Feb 29 04:29:31 PM PST 24 8814724330 ps
T1080 /workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.375717599 Feb 29 03:31:23 PM PST 24 Feb 29 03:36:39 PM PST 24 3384137638 ps
T265 /workspace/coverage/default/16.chip_sw_all_escalation_resets.2035986265 Feb 29 04:04:44 PM PST 24 Feb 29 04:15:27 PM PST 24 5008826408 ps
T1081 /workspace/coverage/default/1.chip_sw_kmac_entropy.2886900407 Feb 29 03:40:25 PM PST 24 Feb 29 03:46:38 PM PST 24 2314833204 ps
T1082 /workspace/coverage/default/2.rom_e2e_asm_init_rma.1233927775 Feb 29 04:02:09 PM PST 24 Feb 29 04:33:48 PM PST 24 8950571867 ps
T1083 /workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2376024938 Feb 29 03:39:31 PM PST 24 Feb 29 03:49:21 PM PST 24 4776353395 ps
T652 /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.4263908899 Feb 29 03:31:15 PM PST 24 Feb 29 04:47:05 PM PST 24 25361193081 ps
T1084 /workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3921809044 Feb 29 03:52:56 PM PST 24 Feb 29 04:40:37 PM PST 24 28729338592 ps
T206 /workspace/coverage/default/1.chip_jtag_csr_rw.522958669 Feb 29 03:37:52 PM PST 24 Feb 29 04:21:04 PM PST 24 21780530000 ps
T708 /workspace/coverage/default/0.chip_sw_power_sleep_load.2478466431 Feb 29 03:33:15 PM PST 24 Feb 29 03:40:06 PM PST 24 4689711480 ps
T1085 /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.3988009979 Feb 29 04:00:28 PM PST 24 Feb 29 04:17:02 PM PST 24 5541449496 ps
T1086 /workspace/coverage/default/1.chip_sw_power_idle_load.3867483000 Feb 29 03:46:50 PM PST 24 Feb 29 03:58:15 PM PST 24 4160380618 ps
T1087 /workspace/coverage/default/0.chip_sw_uart_smoketest_signed.2856527286 Feb 29 03:41:10 PM PST 24 Feb 29 04:14:23 PM PST 24 8400530256 ps
T1088 /workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.4259305035 Feb 29 03:43:49 PM PST 24 Feb 29 03:49:20 PM PST 24 3082360797 ps
T1089 /workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.33835846 Feb 29 03:40:12 PM PST 24 Feb 29 03:49:30 PM PST 24 5821948170 ps
T1090 /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.905268547 Feb 29 03:49:22 PM PST 24 Feb 29 04:07:28 PM PST 24 5794846180 ps
T1091 /workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3158243464 Feb 29 03:50:49 PM PST 24 Feb 29 04:17:25 PM PST 24 6878694908 ps
T1092 /workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1166298934 Feb 29 03:28:19 PM PST 24 Feb 29 03:35:23 PM PST 24 4889377682 ps
T1093 /workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.3231155915 Feb 29 03:38:49 PM PST 24 Feb 29 04:16:43 PM PST 24 8568110032 ps
T812 /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.601408469 Feb 29 04:08:31 PM PST 24 Feb 29 04:16:46 PM PST 24 3945105320 ps
T133 /workspace/coverage/default/30.chip_sw_all_escalation_resets.2345409555 Feb 29 04:02:59 PM PST 24 Feb 29 04:11:32 PM PST 24 5555512896 ps
T1094 /workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2559780796 Feb 29 03:54:39 PM PST 24 Feb 29 07:04:37 PM PST 24 256001276840 ps
T1095 /workspace/coverage/default/14.chip_sw_uart_rand_baudrate.2329984982 Feb 29 04:01:59 PM PST 24 Feb 29 04:43:42 PM PST 24 14055846028 ps
T163 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1768795405 Feb 29 03:54:31 PM PST 24 Feb 29 04:02:02 PM PST 24 5199657008 ps
T781 /workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.800856252 Feb 29 04:06:51 PM PST 24 Feb 29 04:14:35 PM PST 24 3202051154 ps
T1096 /workspace/coverage/default/2.rom_e2e_static_critical.1835584447 Feb 29 04:02:18 PM PST 24 Feb 29 04:37:46 PM PST 24 11101725864 ps
T46 /workspace/coverage/default/1.chip_sw_sleep_pin_retention.580531343 Feb 29 03:39:20 PM PST 24 Feb 29 03:44:57 PM PST 24 3998914040 ps
T1097 /workspace/coverage/default/71.chip_sw_all_escalation_resets.975757845 Feb 29 04:07:35 PM PST 24 Feb 29 04:18:22 PM PST 24 5795042666 ps
T785 /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.1062212294 Feb 29 04:04:51 PM PST 24 Feb 29 04:12:47 PM PST 24 3460963368 ps
T814 /workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.3041477431 Feb 29 04:07:23 PM PST 24 Feb 29 04:14:06 PM PST 24 3433186108 ps
T1098 /workspace/coverage/default/2.rom_e2e_asm_init_dev.2646473229 Feb 29 04:03:31 PM PST 24 Feb 29 04:34:48 PM PST 24 8183154899 ps
T1099 /workspace/coverage/default/2.chip_sw_alert_handler_escalation.3787879353 Feb 29 03:52:28 PM PST 24 Feb 29 04:03:31 PM PST 24 4854118460 ps
T1100 /workspace/coverage/default/0.rom_e2e_asm_init_prod.3540791808 Feb 29 03:38:42 PM PST 24 Feb 29 04:17:43 PM PST 24 8689530481 ps
T1101 /workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.4141952130 Feb 29 03:56:03 PM PST 24 Feb 29 04:08:06 PM PST 24 6671393370 ps
T1102 /workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1047564986 Feb 29 03:31:26 PM PST 24 Feb 29 03:37:52 PM PST 24 4860747513 ps
T1103 /workspace/coverage/default/0.rom_keymgr_functest.93319692 Feb 29 03:37:16 PM PST 24 Feb 29 03:47:20 PM PST 24 5052259294 ps
T1104 /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.201579001 Feb 29 03:59:14 PM PST 24 Feb 29 04:15:19 PM PST 24 6218671636 ps
T1105 /workspace/coverage/default/0.rom_e2e_asm_init_prod_end.4284909330 Feb 29 03:39:14 PM PST 24 Feb 29 04:16:00 PM PST 24 9390884410 ps
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T1157 /workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1859489001 Feb 29 03:48:57 PM PST 24 Feb 29 03:53:53 PM PST 24 2456853872 ps
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