CHIP Simulation Results

Thursday February 29 2024 20:02:24 UTC

GitHub Revision: `e0c4026501`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 37435771356197831901593787335841447308974032110687249165442170486932885997295

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	4.155m	2.635ms	3	3	100.00
		chip_sw_example_rom	2.211m	2.588ms	3	3	100.00
		chip_sw_example_manufacturer	3.510m	2.782ms	3	3	100.00
		chip_sw_example_concurrency	4.293m	2.893ms	3	3	100.00
		chip_sw_uart_smoketest_signed	38.205m	9.355ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	7.085m	7.122ms	5	5	100.00
V1	csr_rw	chip_csr_rw	15.965m	6.005ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.779h	61.348ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.740h	68.840ms	5	5	100.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.141m	2.812ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.740h	68.840ms	5	5	100.00
		chip_csr_rw	15.965m	6.005ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.700s	266.660us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.443m	4.263ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.443m	4.263ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.443m	4.263ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.303m	4.955ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.303m	4.955ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	17.208m	5.363ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	18.127m	5.955ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	17.147m	5.927ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.397h	23.127ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	45.299m	13.949ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	50.611m	23.486ms	4	5	80.00
V1		TOTAL			202	223	90.58
V2	chip_pin_mux	chip_padctrl_attributes	6.027m	4.432ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	6.027m	4.432ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	4.811m	2.584ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	4.927m	3.506ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.610m	3.999ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	29.097m	14.310ms	5	5	100.00
		chip_tap_straps_testunlock0	11.845m	6.713ms	5	5	100.00
		chip_tap_straps_rma	9.040m	4.976ms	5	5	100.00
		chip_tap_straps_prod	22.098m	13.195ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.428m	3.310ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	26.468m	9.121ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	12.567m	5.781ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	12.567m	5.781ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	16.538m	7.007ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	17.857m	5.305ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.680m	5.849ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.140h	19.082ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.716m	2.675ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.556m	5.792ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.487m	2.923ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.020m	3.807ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.711m	3.008ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.926m	5.361ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.644m	3.182ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.263m	3.384ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	19.503m	9.561ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	19.503m	9.561ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.683m	5.305ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	4.604m	2.338ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	7.683m	5.305ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.689m	2.794ms	3	3	100.00
		chip_sw_aes_smoketest	4.831m	3.265ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.929m	2.457ms	3	3	100.00
		chip_sw_clkmgr_smoketest	3.780m	2.246ms	3	3	100.00
		chip_sw_csrng_smoketest	5.147m	3.247ms	3	3	100.00
		chip_sw_entropy_src_smoketest	8.574m	3.699ms	3	3	100.00
		chip_sw_gpio_smoketest	4.675m	2.849ms	3	3	100.00
		chip_sw_hmac_smoketest	7.079m	2.861ms	3	3	100.00
		chip_sw_kmac_smoketest	7.204m	2.982ms	3	3	100.00
		chip_sw_otbn_smoketest	45.469m	10.434ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	4.042m	2.364ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.737m	5.838ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.264m	5.822ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.986m	2.829ms	3	3	100.00
		chip_sw_rv_timer_smoketest	4.857m	2.747ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.136m	3.478ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.776m	2.436ms	3	3	100.00
		chip_sw_uart_smoketest	5.076m	3.247ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	12.368m	5.397ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	38.205m	9.355ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.696h	78.404ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.510m	9.237ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	38.389m	15.716ms	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	11.392m	4.160ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	8.792m	3.919ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.144h	57.737ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.518h	63.107ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.639m	3.524ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	6.639m	3.524ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.740h	68.840ms	5	5	100.00
		chip_same_csr_outstanding	1.036h	29.857ms	20	20	100.00
		chip_csr_hw_reset	7.085m	7.122ms	5	5	100.00
		chip_csr_rw	15.965m	6.005ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.740h	68.840ms	5	5	100.00
		chip_same_csr_outstanding	1.036h	29.857ms	20	20	100.00
		chip_csr_hw_reset	7.085m	7.122ms	5	5	100.00
		chip_csr_rw	15.965m	6.005ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.911m	2.500ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.790s	61.412us	100	100	100.00
		xbar_smoke_large_delays	2.117m	11.164ms	100	100	100.00
		xbar_smoke_slow_rsp	2.086m	6.250ms	100	100	100.00
		xbar_random_zero_delays	1.047m	591.162us	100	100	100.00
		xbar_random_large_delays	21.463m	112.008ms	100	100	100.00
		xbar_random_slow_rsp	22.582m	73.996ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.283m	1.519ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.034m	1.560ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.794m	2.392ms	100	100	100.00
		xbar_error_and_unmapped_addr	1.034m	1.560ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.577m	3.665ms	100	100	100.00
		xbar_access_same_device_slow_rsp	49.728m	156.834ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.618m	2.718ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.821m	19.539ms	100	100	100.00
		xbar_stress_all_with_error	13.768m	21.407ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	16.815m	8.599ms	100	100	100.00
		xbar_stress_all_with_reset_error	15.269m	18.870ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.510m	9.237ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	1.053h	20.479ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	38.566m	8.815ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	32.149m	6.863ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	44.129m	9.137ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	39.623m	8.451ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	38.689m	8.807ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	41.838m	8.618ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	31.262m	7.444ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	43.075m	8.367ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	43.084m	8.812ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	35.362m	8.533ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	39.749m	9.198ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	44.998m	9.755ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	57.768m	12.074ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	1.088h	11.846ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	53.879m	11.755ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	59.490m	12.058ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	44.314m	9.995ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	56.018m	11.680ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	1.012h	12.534ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	59.651m	12.066ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	57.803m	12.204ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.480m	7.307ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	35.168m	8.338ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	29.590m	8.707ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	32.816m	8.276ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	37.889m	8.568ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	28.906m	6.971ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	33.579m	8.653ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	24.441m	9.039ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	33.915m	9.031ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	30.030m	8.690ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	27.858m	6.356ms	3	3	100.00
		rom_e2e_asm_init_dev	35.443m	9.027ms	3	3	100.00
		rom_e2e_asm_init_prod	38.992m	8.730ms	3	3	100.00
		rom_e2e_asm_init_prod_end	36.766m	9.391ms	3	3	100.00
		rom_e2e_asm_init_rma	38.091m	8.022ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	53.235m	10.835ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	4.527m	3.207ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.716m	2.675ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.944m	3.374ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.172m	2.593ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	12.117m	4.937ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.937m	18.374ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.937m	18.374ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.678m	3.569ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	8.737m	5.838ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.678m	3.569ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.852m	8.180ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	14.852m	8.180ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.308m	6.459ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	9.973m	5.912ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	15.405m	6.376ms	3	3	100.00
		chip_sw_aes_idle	5.172m	2.593ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.631m	2.824ms	3	3	100.00
		chip_sw_kmac_idle	4.772m	2.696ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	10.268m	5.261ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.129m	5.034ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	6.971m	4.577ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.462m	4.583ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	24.970m	9.043ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.383m	3.838ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.334m	4.111ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.716m	4.289ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.186m	5.198ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.329m	4.060ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.335m	5.018ms	3	3	100.00
		chip_sw_ast_clk_outputs	16.538m	7.007ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.413m	11.855ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.716m	4.289ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.186m	5.198ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	17.857m	5.305ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.680m	5.849ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.140h	19.082ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	4.716m	2.675ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	19.556m	5.792ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.487m	2.923ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.020m	3.807ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.711m	3.008ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.926m	5.361ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.644m	3.182ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.615m	3.001ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	17.395m	5.412ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.712m	7.740ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.264h	25.361ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	5.203m	3.238ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	6.213m	3.442ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.071m	4.796ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.546m	3.246ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	11.218m	5.405ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	42.614m	18.813ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.163h	23.129ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	16.538m	7.007ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	10.856m	4.906ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.856m	3.133ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	34.712m	9.548ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	25.389m	6.895ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	10.376m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	16.197m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.237m	2.518ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.266m	7.326ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	35.083m	23.347ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.496m	3.078ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	40.450s	10.380us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.290m	4.254ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	35.083m	23.347ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	35.083m	23.347ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	59.320m	21.050ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	59.320m	21.050ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.973m	6.514ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.937m	18.374ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.112h	17.682ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	5.384m	3.528ms	3	3	100.00
		chip_sw_edn_entropy_reqs	21.887m	5.609ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	5.384m	3.528ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	25.389m	6.895ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.438m	2.204ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.553m	22.515ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.196m	6.322ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.680m	5.849ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	19.648m	4.787ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	17.857m	5.305ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	10.631m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.553m	22.515ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.800m	3.421ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.587m	4.064ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.913m	5.394ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	10.631m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	8.913m	5.394ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.913m	5.394ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	8.913m	5.394ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	8.913m	5.394ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	8.591m	11.923ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	22.713m	5.343ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.134m	5.680ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.134m	5.680ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	4.914m	3.046ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	6.487m	2.923ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.631m	2.824ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	17.064m	5.056ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	16.500m	5.413ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.263m	4.932ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	10.367m	4.442ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.587m	4.064ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	12.020m	3.807ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.732m	5.312ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	12.117m	4.937ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.136h	12.946ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.027m	2.842ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.628m	3.278ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	6.711m	3.008ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.587m	4.064ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.782m	3.217ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	6.204m	2.315ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.772m	2.696ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.058m	4.854ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	29.097m	14.310ms	5	5	100.00
		chip_tap_straps_rma	9.040m	4.976ms	5	5	100.00
		chip_tap_straps_prod	22.098m	13.195ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.165m	3.236ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.971m	5.102ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	8.913m	5.394ms	3	3	100.00
		chip_sw_flash_rma_unlocked	10.631m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.086m	4.162ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.183m	8.717ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	19.692m	8.366ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.576m	8.194ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
		chip_sw_keymgr_key_derivation	10.587m	4.064ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	9.623m	9.868ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	10.112m	10.021ms	0	3	0.00
		chip_prim_tl_access	8.591m	11.923ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.413m	11.855ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.383m	3.838ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	13.334m	4.111ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.716m	4.289ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.186m	5.198ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.329m	4.060ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.335m	5.018ms	3	3	100.00
		chip_tap_straps_dev	29.097m	14.310ms	5	5	100.00
		chip_tap_straps_rma	9.040m	4.976ms	5	5	100.00
		chip_tap_straps_prod	22.098m	13.195ms	5	5	100.00
		chip_rv_dm_lc_disabled	7.446m	12.269ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.029m	2.858ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	1.923m	3.324ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	1.976m	2.649ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	3.199m	3.030ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	38.638m	30.169ms	3	3	100.00
		chip_rv_dm_lc_disabled	7.446m	12.269ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.738h	51.024ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.558h	50.410ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	17.471m	8.975ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.555h	46.621ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	38.638m	30.169ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	1.985m	2.726ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	1.807m	2.562ms	3	3	100.00
		rom_volatile_raw_unlock	2.092m	2.414ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.553m	22.515ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.750m	3.570ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.587m	4.064ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.903m	3.900ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.275m	2.970ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.553m	22.515ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.750m	3.570ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.587m	4.064ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	13.903m	3.900ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.275m	2.970ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	17.600m	14.334ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.165m	3.236ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	13.086m	4.162ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.183m	8.717ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	19.692m	8.366ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	26.576m	8.194ms	3	3	100.00
		chip_sw_lc_ctrl_transition	19.188m	13.280ms	15	15	100.00
		chip_prim_tl_access	8.591m	11.923ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	8.591m	11.923ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.755m	8.733ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	32.898m	20.877ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.704m	6.776ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	11.707m	7.571ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	9.986m	17.544ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	33.214m	22.500ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	20.112m	13.548ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	14.852m	8.180ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	20.043m	12.766ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	10.110m	4.997ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.755m	8.733ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	8.704m	4.270ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	54.368m	42.073ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	7.674m	6.500ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	8.950m	5.515ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	57.246m	23.770ms	2	3	66.67
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	21.266m	7.326ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	35.409m	13.458ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	51.445m	22.858ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.684m	3.319ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	9.623m	9.868ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	9.623m	9.868ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	35.409m	13.458ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	57.246m	23.770ms	2	3	66.67
		chip_sw_pwrmgr_wdog_reset	10.110m	4.997ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	8.737m	5.838ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	9.295m	3.988ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	12.909m	7.269ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	6.166m	4.385ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	31.003m	12.253ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.303m	3.493ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	38.303m	8.518ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.090m	6.105ms	3	3	100.00
		chip_plic_all_irqs_10	8.964m	4.099ms	3	3	100.00
		chip_plic_all_irqs_20	14.921m	4.122ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.206m	3.204ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.889m	3.120ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.510m	9.237ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	15.587m	7.199ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.948m	4.397ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	8.444m	3.597ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.269m	2.962ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	13.903m	3.900ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.926m	5.361ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.261m	7.183ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	14.014m	7.987ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.112m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
		chip_sw_data_integrity_escalation	12.567m	5.781ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.029m	2.929ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.697m	2.856ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	7.516m	2.954ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.288m	4.357ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	26.904m	8.127ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	2.020h	31.549ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	57.484m	11.941ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.017m	3.244ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.058m	4.854ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	6.648m	4.284ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	31.003m	12.253ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	11.173m	5.701ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.610m	3.493ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	22.044m	11.093ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	34.712m	9.548ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	38.303m	8.518ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.787h	255.449ms	2	3	66.67
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	43.197m	21.781ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	28.055m	13.234ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	9.295m	3.988ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.069m	5.583ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.141m	5.451ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	9.040m	4.976ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	7.446m	12.269ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2585	2657	97.29
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.814m	3.023ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.877h	50.345ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	12.284m	3.923ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.542m	1.788ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.133m	2.449ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.635m	1.747ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	1.346h	46.731ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.205h	40.844ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.019h	41.124ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	41.787m	10.288ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	9.121m	3.107ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	11.667m	2.901ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	30.230m	7.827ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	42.395m	10.211ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.014m	3.524ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.173m	5.828ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	4.548m	2.766ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	10.363m	5.416ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.610m	5.149ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.335m	5.243ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	35.409m	13.458ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	14.216m	5.758ms	96	100	96.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.303m	4.955ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.412h	18.919ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.542m	1.788ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.133m	2.449ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.635m	1.747ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	11.454m	5.937ms	3	3	100.00
V3		TOTAL			33	48	68.75
	Unmapped tests	chip_sival_flash_info_access	9.609m	3.483ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	11.694m	4.260ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.165h	16.736ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	22.664m	5.053ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	13.329m	4.206ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.044m	6.671ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.316m	2.923ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	3.328m	2.864ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2847	2958	96.25

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	17	89.47
V2	290	276	250	86.21
V2S	1	1	1	100.00
V3	91	22	13	14.29

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
95.91	95.21	93.87	95.03	--	94.38	97.38	99.58

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.97207041017915809795836729236979237525509691647497471828052333588147235360047
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:25:11) Loading:
  (15:25:12) Loading:
  (15:25:12) Loading: 4 packages loaded
  (15:25:12) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:25:12) WARNING: Target pattern parsing failed.
  (15:25:12) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:25:12) INFO: Elapsed time: 22.678s
  (15:25:12) INFO: 0 processes.
  (15:25:12) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.50791941680520412392841836581483294544999678066044787389044931984809518621341
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:38:59) Loading:
  (15:39:00) Loading:
  (15:39:00) Loading: 4 packages loaded
  (15:39:00) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:39:00) WARNING: Target pattern parsing failed.
  (15:39:00) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:39:00) INFO: Elapsed time: 21.073s
  (15:39:00) INFO: 0 processes.
  (15:39:00) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.30815080419813598911618308459600046613128489191711418026244243512990103782198
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:28:45) Loading:
  (15:28:45) Loading:
  (15:28:45) Loading: 4 packages loaded
  (15:28:45) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:28:45) WARNING: Target pattern parsing failed.
  (15:28:45) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:28:45) INFO: Elapsed time: 17.201s
  (15:28:45) INFO: 0 processes.
  (15:28:45) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.109330054990958035662654527412940523588794564797132167725261291752361090765638
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:40:58) Loading:
  (15:40:59) Loading:
  (15:40:59) Loading: 4 packages loaded
  (15:40:59) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:59) WARNING: Target pattern parsing failed.
  (15:40:59) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:59) INFO: Elapsed time: 26.878s
  (15:40:59) INFO: 0 processes.
  (15:40:59) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.10314831653478514339993082062796908198195137376523451256072207119402518434791
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:29:02) Loading:
  (15:29:03) Loading:
  (15:29:03) Loading: 4 packages loaded
  (15:29:03) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:29:03) WARNING: Target pattern parsing failed.
  (15:29:03) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:29:03) INFO: Elapsed time: 20.730s
  (15:29:03) INFO: 0 processes.
  (15:29:03) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.77030904511479623824722188027970527897379834467070653032466787683638154174076
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:40:39) Loading:
  (15:40:39) Loading:
  (15:40:39) Loading: 4 packages loaded
  (15:40:40) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:40) WARNING: Target pattern parsing failed.
  (15:40:40) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:40) INFO: Elapsed time: 24.658s
  (15:40:40) INFO: 0 processes.
  (15:40:40) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.68216249125115444563160720685268068019483665762397776052272400701058853291555
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:28:56) Loading:
  (15:28:57) Loading:
  (15:28:57) Loading: 4 packages loaded
  (15:28:57) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:28:57) WARNING: Target pattern parsing failed.
  (15:28:57) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:28:57) INFO: Elapsed time: 20.021s
  (15:28:57) INFO: 0 processes.
  (15:28:57) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.106043835012599508345216254887098923424656635315461045058838738633394107660021
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:40:30) Loading:
  (15:40:31) Loading:
  (15:40:31) Loading: 4 packages loaded
  (15:40:31) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:31) WARNING: Target pattern parsing failed.
  (15:40:31) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:40:31) INFO: Elapsed time: 23.038s
  (15:40:31) INFO: 0 processes.
  (15:40:31) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.22221302483870491038508961766117671519986200578775459829374576081931319738497
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:29:05) Loading:
  (15:29:05) Loading:
  (15:29:05) Loading: 4 packages loaded
  (15:29:05) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:29:05) WARNING: Target pattern parsing failed.
  (15:29:05) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:29:05) INFO: Elapsed time: 18.663s
  (15:29:05) INFO: 0 processes.
  (15:29:05) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.21474543907687002357951657922371547695095524724612129243126253939935239701130
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:40:40) Loading:
  (15:40:41) Loading:
  (15:40:41) Loading: 4 packages loaded
  (15:40:41) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:40:41) WARNING: Target pattern parsing failed.
  (15:40:41) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:40:41) INFO: Elapsed time: 27.306s
  (15:40:41) INFO: 0 processes.
  (15:40:41) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:788) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.11565215536486791590551617710023819736041651863599732355944987874575971592240
    Line 394, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2174.303194 us: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2174.303194 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.66759798443069554928131422141205337595428161030731416660501624665064194733787
    Line 373, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2429.141611 us: (cip_base_vseq.sv:788) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
  UVM_INFO @ 2429.141611 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 11 failures:
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.34685515522680773113979423324731320892106288377005067787948720723381437620319
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:d268afd8-f14c-46a0-848b-62d54107b55d
```
  - 1.chip_sw_rv_timer_systick_test.92693890616702096481601147634541493970202875188076314712126657446437562731303
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:ff111fc9-45cc-4691-910c-a6cd37450aa0
```
  - ... and 1 more failures.
- Test chip_sw_alert_handler_reverse_ping_in_deep_sleep has 1 failures.
  - 0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.114190403435072495100333499249422742833554689207867561268932956781937685422456
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep/latest/run.log
```
  Job ID: smart:12a0de57-2e9b-41a0-9ac0-baa01c9cb8c8
```
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.56556661334185704890133636502745704113916618268008277376423475010588158023603
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:20f644a4-1a7a-4f9a-b3a8-a3747be2f1ed
```
  - 1.chip_sw_ast_clk_rst_inputs.30102467819026913254913379412591633683442011974244118676242416883365867605399
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:847095be-b0f1-4697-9a65-7d1bc76b7159
```
  - ... and 1 more failures.
- Test chip_sw_power_virus has 2 failures.
  - 1.chip_sw_power_virus.36351351369424857411332511222638389899025730644334455517953339445325610090521
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:6d1a4b55-d688-4871-a772-55da6e9a08e3
```
  - 2.chip_sw_power_virus.35515936175175777208943651209143642267211624559194473414860309117749352503840
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  Job ID: smart:36995570-31df-44a5-81a6-e617c09f6e3a
```
- Test rom_raw_unlock has 1 failures.
  - 1.rom_raw_unlock.100777753797529945098616013834041281866316075423922631639793637391355666864677
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_raw_unlock/latest/run.log
```
  Job ID: smart:3c327ba7-a26c-4cbf-8a37-76ee46c3e5e3
```
- ... and 1 more tests.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.
  - 29.chip_sw_alert_handler_lpg_sleep_mode_alerts.39751727326657189802373581038486161442671581898456696032768761282800101266352
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/29.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3492.993836 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3492.993836 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 39.chip_sw_alert_handler_lpg_sleep_mode_alerts.8779510892709564135415305548317984766273263730137033790930045111773562520933
    Line 887, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/39.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3306.029812 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3306.029812 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 4 failures:
- Test chip_sw_all_escalation_resets has 4 failures.
  - 31.chip_sw_all_escalation_resets.78082775662314279515268334664135661628840900518747488707308706775814059255654
    Line 728, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/31.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2584.957464 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2584.957464 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 37.chip_sw_all_escalation_resets.93255301617681848946832275370745221092782189033863658867287121440841093398899
    Line 745, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/37.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 3374.185878 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 3374.185878 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 2 more failures.
UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.46646096572535499294823160930669951079531982848341964994659549328573003305068
    Line 661, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.180001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.32321774618542822110030433373931081499254618354085151861276743427860821772240
    Line 685, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.200001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.71472316743466182775910781992064445652691563138521483753514550920605797616959
    Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.220001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.220001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.57002326455960976269545692463062307864578278253870720297384427894734977037370
    Line 727, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.380001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.525012849699734581016463949069192226966064696952012163033960261873932644679
    Line 814, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.340001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.340001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.94046506803362340464124172695999564940614892127882494973116116510395879975019
    Line 717, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.200001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.30998756971864199589129947940701687351093909593918012560249437694214904090357
    Line 836, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.28995263873046602403589179099309706170176745027382113905294957039419062120951
    Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.34697202088601004100734597798284914864626559288447100927921412673008518625814
    Line 717, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.700001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.700001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.20809565156304222283467337641852929562089401984628284402213922526574565415501
    Line 724, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.500001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.500001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.60591935010068224145231043762340328616119635267088607829008346628862868370888
    Line 763, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 15276.073080 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15276.073080 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.32815985936242603022797068295758459993558327356226268620279024487522597084454
    Line 703, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14962.470900 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14962.470900 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.21231379998905686389384119762894649426516694600216367917899039730158311908407
    Line 681, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 1788.151500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1788.151500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.62048692713079739152016637519934537743589867092454375089441257316180219281328
    Line 709, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2449.317500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2449.317500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.12015000618571839642124252142144543535689039414462669689856691582172606494424
    Line 680, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 1747.459500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1747.459500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.5477324258528571712425346042824583526885010061701889400041493614680173942384
    Line 711, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 46731.227382 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 46731.227382 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.15952944428468456147237648454115331829318358767023460031643015417574245184260
    Line 752, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 40843.557325 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40843.557325 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.49837588660552666541573636261983612153040989927881919278698778204292511310332
    Line 720, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 41123.910657 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41123.910657 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.74435336251314147678177330609126989513567983852368257463844097866404104209846
Line 731, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9647.650102 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9647.650102 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.79497605683660268834634249401718357953077217149945313858597296540854080585888
Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10288.183734 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10288.183734 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Offending '(pend_req[h2d.a_source].pend == *)' has 1 failures:
- Test chip_sw_pwrmgr_random_sleep_all_reset_reqs has 1 failures.
  - 0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.69931016115608566708550224841609507451230210763118483067346260716041946163522
    Line 827, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs/latest/run.log
```
      Offending '(pend_req[h2d.a_source].pend == 0)'
  UVM_ERROR @ 17048.801280 us: (tlul_assert.sv:263) [ASSERT FAILED] pendingReqPerSrc_M
  UVM_INFO @ 17048.801280 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 1 failures:
- Test chip_sw_power_virus has 1 failures.
  - 0.chip_sw_power_virus.15859878313781556986197701963324166350125868997268409026535582735321117131962
    Line 951, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 3923.013638 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 3923.013638 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 1 failures:
- Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.
  - 1.chip_sw_pwrmgr_normal_sleep_por_reset.93452520547621261139309546371590042020248396427972797444295129139901742545016
    Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 17543.981652 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17543.981652 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```