CHIP Simulation Results

Sunday February 18 2024 20:02:30 UTC

GitHub Revision: `8faf04697a`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 18983509472502570446328716692660256492766541929441074968843370054317032656232

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.199m	2.705ms	3	3	100.00
		chip_sw_example_rom	2.223m	2.608ms	3	3	100.00
		chip_sw_example_manufacturer	4.337m	2.735ms	3	3	100.00
		chip_sw_example_concurrency	6.186m	3.458ms	3	3	100.00
		chip_sw_uart_smoketest_signed	35.950m	9.259ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.183m	7.117ms	5	5	100.00
V1	csr_rw	chip_csr_rw	12.488m	5.839ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	1.897h	65.362ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.938h	71.343ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	2.047m	2.599ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.938h	71.343ms	4	5	80.00
		chip_csr_rw	12.488m	5.839ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.580s	241.224us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	8.295m	4.479ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	8.295m	4.479ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	8.295m	4.479ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	16.003m	5.402ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	16.003m	5.402ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	17.548m	5.198ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	19.205m	5.888ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	17.757m	5.653ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.247h	22.973ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.172h	23.110ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	34.320m	22.908ms	4	5	80.00
V1		TOTAL			201	223	90.13
V2	chip_pin_mux	chip_padctrl_attributes	4.686m	4.161ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.686m	4.161ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.499m	2.979ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.647m	4.671ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	6.453m	3.121ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	27.202m	14.187ms	5	5	100.00
		chip_tap_straps_testunlock0	15.800m	9.225ms	5	5	100.00
		chip_tap_straps_rma	12.805m	7.761ms	5	5	100.00
		chip_tap_straps_prod	15.223m	10.013ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	5.269m	3.227ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	29.508m	8.832ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.835m	6.277ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.835m	6.277ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	20.423m	6.438ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.121m	5.399ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.010m	5.932ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.224h	18.687ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.546m	3.570ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.527m	5.819ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.772m	2.606ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.562m	5.048ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.897m	3.749ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.242m	4.903ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.021m	2.970ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.191m	2.387ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	12.474m	8.593ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	12.474m	8.593ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.139m	5.212ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.360m	2.722ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	10.139m	5.212ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.940m	2.717ms	3	3	100.00
		chip_sw_aes_smoketest	4.990m	2.874ms	3	3	100.00
		chip_sw_aon_timer_smoketest	5.451m	2.487ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.462m	3.077ms	3	3	100.00
		chip_sw_csrng_smoketest	3.721m	3.257ms	3	3	100.00
		chip_sw_entropy_src_smoketest	9.273m	3.539ms	3	3	100.00
		chip_sw_gpio_smoketest	5.346m	2.697ms	3	3	100.00
		chip_sw_hmac_smoketest	7.393m	3.061ms	3	3	100.00
		chip_sw_kmac_smoketest	5.374m	3.079ms	3	3	100.00
		chip_sw_otbn_smoketest	40.604m	11.147ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.720m	2.818ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.166m	4.788ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	9.008m	4.780ms	3	3	100.00
		chip_sw_rv_plic_smoketest	6.236m	3.396ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.953m	2.618ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.683m	2.533ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	6.097m	3.193ms	3	3	100.00
		chip_sw_uart_smoketest	5.027m	3.014ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	9.681m	4.684ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	35.950m	9.259ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.639h	78.593ms	1	3	33.33
V2	chip_sw_secure_boot	rom_e2e_smoke	33.200m	9.058ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	36.889m	14.056ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	14.514m	4.207ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.318m	10.453ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.909h	59.154ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.283h	66.311ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.490m	4.748ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.490m	4.748ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.938h	71.343ms	4	5	80.00
		chip_same_csr_outstanding	1.341h	32.320ms	20	20	100.00
		chip_csr_hw_reset	6.183m	7.117ms	5	5	100.00
		chip_csr_rw	12.488m	5.839ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.938h	71.343ms	4	5	80.00
		chip_same_csr_outstanding	1.341h	32.320ms	20	20	100.00
		chip_csr_hw_reset	6.183m	7.117ms	5	5	100.00
		chip_csr_rw	12.488m	5.839ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.804m	2.572ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.430s	54.281us	100	100	100.00
		xbar_smoke_large_delays	2.101m	11.451ms	100	100	100.00
		xbar_smoke_slow_rsp	2.046m	7.308ms	100	100	100.00
		xbar_random_zero_delays	56.810s	629.991us	100	100	100.00
		xbar_random_large_delays	22.618m	119.491ms	100	100	100.00
		xbar_random_slow_rsp	21.862m	63.489ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.077m	1.366ms	100	100	100.00
		xbar_error_and_unmapped_addr	57.760s	1.438ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.591m	2.602ms	100	100	100.00
		xbar_error_and_unmapped_addr	57.760s	1.438ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.448m	3.856ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.691m	180.829ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.312m	2.708ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	11.431m	16.280ms	100	100	100.00
		xbar_stress_all_with_error	9.756m	16.705ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.080m	11.285ms	100	100	100.00
		xbar_stress_all_with_reset_error	12.309m	15.984ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	33.200m	9.058ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	48.074m	24.119ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.060m	8.176ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	27.267m	7.331ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	35.735m	8.844ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	32.956m	8.546ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	32.610m	9.178ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	35.043m	8.630ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	26.995m	7.564ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	32.447m	8.719ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	37.999m	8.589ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	40.888m	8.207ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	37.444m	8.561ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	45.882m	9.712ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	51.490m	12.098ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	58.954m	12.107ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	49.947m	12.467ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	49.507m	12.024ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	39.668m	10.143ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	39.574m	11.417ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	47.170m	10.808ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	46.644m	11.229ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	42.057m	11.076ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.800m	6.949ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	32.459m	7.660ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	30.890m	8.170ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	37.850m	8.578ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	35.378m	8.463ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.708m	7.175ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	32.423m	8.336ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	32.533m	8.582ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	29.384m	8.976ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	33.050m	9.095ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	29.118m	6.994ms	3	3	100.00
		rom_e2e_asm_init_dev	32.331m	8.888ms	3	3	100.00
		rom_e2e_asm_init_prod	34.413m	8.558ms	3	3	100.00
		rom_e2e_asm_init_prod_end	34.636m	8.352ms	3	3	100.00
		rom_e2e_asm_init_rma	31.802m	8.117ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	45.625m	10.664ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	5.673m	3.032ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.546m	3.570ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.519m	3.447ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.220m	2.433ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	10.217m	5.499ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.719m	18.886ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.719m	18.886ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.463m	4.477ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.166m	4.788ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.463m	4.477ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.375m	7.242ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	16.375m	7.242ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	9.852m	8.052ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.191m	4.996ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	16.730m	5.920ms	3	3	100.00
		chip_sw_aes_idle	4.220m	2.433ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.869m	3.283ms	3	3	100.00
		chip_sw_kmac_idle	6.372m	2.899ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	8.184m	4.299ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	8.421m	5.318ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	9.222m	4.321ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	9.000m	5.102ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	24.921m	13.425ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.461m	3.924ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.496m	4.937ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.101m	3.700ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.324m	4.692ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.894m	3.998ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.072m	4.976ms	3	3	100.00
		chip_sw_ast_clk_outputs	20.423m	6.438ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	19.758m	10.813ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.101m	3.700ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.324m	4.692ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	18.121m	5.399ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.010m	5.932ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.224h	18.687ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.546m	3.570ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.527m	5.819ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.772m	2.606ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.562m	5.048ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.897m	3.749ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.242m	4.903ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.021m	2.970ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.375m	3.374ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	18.014m	6.765ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	22.158m	7.952ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.009h	24.356ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.119m	2.853ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	6.698m	2.810ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.411m	4.287ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.222m	2.988ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	9.960m	4.791ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.248m	20.862ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.238h	30.072ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	20.423m	6.438ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.017m	4.642ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.690m	2.959ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	29.553m	7.399ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	34.575m	8.366ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	12.736m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	20.577m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	4.973m	2.554ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.524m	8.273ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	32.782m	22.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	6.441m	2.964ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	43.420s	10.400us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.105m	4.149ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	32.782m	22.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	32.782m	22.972ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	1.005h	20.212ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	1.005h	20.212ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	9.977m	6.081ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.719m	18.886ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.040h	15.191ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	3.598m	3.251ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.575m	6.025ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	3.598m	3.251ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	34.575m	8.366ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.522m	3.339ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	37.338m	23.487ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.810m	5.547ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	18.010m	5.932ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	15.809m	5.181ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	18.121m	5.399ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	12.550m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	37.338m	23.487ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.515m	3.807ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.130m	4.461ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.302m	4.059ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	12.550m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.302m	4.059ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.302m	4.059ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.302m	4.059ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.302m	4.059ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	4.181m	6.081ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	20.805m	5.498ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.774m	5.562ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.774m	5.562ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.210m	3.369ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	4.772m	2.606ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.869m	3.283ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	18.849m	5.668ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	18.893m	5.491ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	17.306m	5.173ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	11.606m	4.481ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.130m	4.461ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.562m	5.048ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.329m	4.805ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	10.217m	5.499ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.115h	18.256ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	6.213m	3.525ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.546m	3.353ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.897m	3.749ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.130m	4.461ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	3.527m	2.678ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	4.659m	2.827ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	6.372m	2.899ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.196m	5.982ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	27.202m	14.187ms	5	5	100.00
		chip_tap_straps_rma	12.805m	7.761ms	5	5	100.00
		chip_tap_straps_prod	15.223m	10.013ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.882m	2.626ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	9.295m	3.671ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.302m	4.059ms	3	3	100.00
		chip_sw_flash_rma_unlocked	12.550m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.932m	3.672ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.582m	7.855ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.964m	8.883ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	20.606m	8.045ms	3	3	100.00
		chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
		chip_sw_keymgr_key_derivation	10.130m	4.461ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	11.829m	9.777ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	10.545m	10.020ms	0	3	0.00
		chip_prim_tl_access	4.181m	6.081ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	19.758m	10.813ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	11.461m	3.924ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.496m	4.937ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	12.101m	3.700ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.324m	4.692ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	11.894m	3.998ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	11.072m	4.976ms	3	3	100.00
		chip_tap_straps_dev	27.202m	14.187ms	5	5	100.00
		chip_tap_straps_rma	12.805m	7.761ms	5	5	100.00
		chip_tap_straps_prod	15.223m	10.013ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.514m	7.505ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	5.250m	2.867ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.583m	3.601ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.445m	3.291ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.472m	3.638ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	42.644m	28.366ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.514m	7.505ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.543h	49.275ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.549h	51.858ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.409m	9.429ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.585h	46.194ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	42.644m	28.366ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.041m	1.946ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.123m	2.535ms	3	3	100.00
		rom_volatile_raw_unlock	1.916m	2.495ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	37.338m	23.487ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.566m	3.577ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.130m	4.461ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.762m	5.662ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.787m	2.352ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	37.338m	23.487ms	3	3	100.00
		chip_sw_otbn_mem_scramble	8.566m	3.577ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.130m	4.461ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	10.762m	5.662ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	3.787m	2.352ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	15.091m	14.570ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	4.882m	2.626ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	11.932m	3.672ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	24.582m	7.855ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	26.964m	8.883ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	20.606m	8.045ms	3	3	100.00
		chip_sw_lc_ctrl_transition	23.060m	12.058ms	15	15	100.00
		chip_prim_tl_access	4.181m	6.081ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	4.181m	6.081ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.836m	7.809ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	30.435m	20.934ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	9.489m	7.832ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.367m	7.644ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	12.721m	7.533ms	1	3	33.33
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	25.451m	17.860ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	26.247m	11.256ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	16.375m	7.242ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	22.744m	13.303ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	9.665m	4.479ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.836m	7.809ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.667m	5.295ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	57.804m	38.922ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	10.278m	7.401ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	9.488m	5.501ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	48.252m	28.356ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.524m	8.273ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	30.815m	12.593ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	53.416m	26.732ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	5.146m	2.732ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	11.829m	9.777ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	11.829m	9.777ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	30.815m	12.593ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	48.252m	28.356ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	9.665m	4.479ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.166m	4.788ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.115m	4.417ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	9.680m	7.312ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.421m	3.574ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	34.316m	13.790ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.005m	2.863ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	29.240m	7.595ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.651m	6.176ms	3	3	100.00
		chip_plic_all_irqs_10	8.982m	3.832ms	3	3	100.00
		chip_plic_all_irqs_20	16.205m	4.579ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.800m	2.446ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	3.818m	3.158ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	33.200m	9.058ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	17.106m	8.265ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	11.265m	4.066ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	7.949m	2.786ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	6.058m	3.296ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	10.762m	5.662ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.242m	4.903ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	10.504m	7.250ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	12.005m	6.944ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	10.545m	10.020ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
		chip_sw_data_integrity_escalation	14.835m	6.277ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	2.914m	2.879ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	4.515m	3.086ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.654m	3.605ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	9.544m	4.427ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	33.210m	7.986ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.973h	31.196ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	46.966m	11.567ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.727m	3.451ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.196m	5.982ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	7.650m	4.116ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	34.316m	13.790ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	9.650m	5.549ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	8.937m	3.640ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	27.886m	12.452ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	29.553m	7.399ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	29.240m	7.595ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.440h	254.541ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	39.259m	21.458ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.114m	13.011ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.115m	4.417ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	9.296m	5.607ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	10.402m	5.251ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	12.805m	7.761ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.514m	7.505ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2585	2657	97.29
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.501m	3.150ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.760h	50.104ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	19.968m	6.314ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.979m	2.364ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.987m	2.280ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.841m	2.172ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	52.630m	40.904ms	0	1	0.00
		rom_e2e_jtag_inject_dev	1.103h	51.313ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.147h	51.490ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	37.962m	9.468ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.861m	3.586ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	10.406m	2.867ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	21.878m	5.738ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	28.303m	7.990ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.830m	3.571ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	23.881m	5.853ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	2.068m	2.234ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.077m	4.908ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	8.792m	6.553ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.769m	4.324ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	30.815m	12.593ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.660m	6.466ms	95	100	95.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	16.003m	5.402ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.076h	19.261ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.979m	2.364ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.987m	2.280ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.841m	2.172ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.262m	5.334ms	3	3	100.00
V3		TOTAL			33	48	68.75
	Unmapped tests	chip_sival_flash_info_access	7.940m	3.576ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	13.155m	6.166ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.131h	16.768ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	17.662m	5.719ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	16.535m	4.763ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	12.165m	5.914ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.968m	2.603ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	2.205m	2.195ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2846	2958	96.21

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	16	84.21
V2	290	276	251	86.55
V2S	1	1	1	100.00
V3	91	22	13	14.29

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.29	95.43	94.62	95.05	--	95.30	97.75	99.59

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.19138775218687577555743938044235695035682946254487343292135805524880918463240
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:48:11) Loading:
  (15:48:11) Loading:
  (15:48:11) Loading: 4 packages loaded
  (15:48:11) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:48:11) WARNING: Target pattern parsing failed.
  (15:48:11) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:48:12) INFO: Elapsed time: 20.925s
  (15:48:12) INFO: 0 processes.
  (15:48:12) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.40335479178655803716886035788950507067131531727474161623991690283999592375548
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (15:59:11) Loading:
  (15:59:11) Loading:
  (15:59:11) Loading: 4 packages loaded
  (15:59:11) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:59:11) WARNING: Target pattern parsing failed.
  (15:59:11) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (15:59:11) INFO: Elapsed time: 20.719s
  (15:59:11) INFO: 0 processes.
  (15:59:11) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.20321530053644239774978874930535101710753508333762045195181219350948924125649
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (15:49:35) Loading:
  (15:49:36) Loading:
  (15:49:36) Loading: 4 packages loaded
  (15:49:36) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:36) WARNING: Target pattern parsing failed.
  (15:49:36) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:36) INFO: Elapsed time: 34.291s
  (15:49:36) INFO: 0 processes.
  (15:49:36) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.104868177364539244251055361510964192799441934756695442218730217343562109661071
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:00:27) Loading:
  (16:00:27) Loading:
  (16:00:27) Loading: 4 packages loaded
  (16:00:27) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:00:27) WARNING: Target pattern parsing failed.
  (16:00:27) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:00:27) INFO: Elapsed time: 28.187s
  (16:00:27) INFO: 0 processes.
  (16:00:27) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.13711329811810505877752493018383531051577319901879756657000010461805954031688
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (15:49:22) Loading:
  (15:49:22) Loading:
  (15:49:22) Loading: 4 packages loaded
  (15:49:22) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:22) WARNING: Target pattern parsing failed.
  (15:49:22) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:23) INFO: Elapsed time: 18.442s
  (15:49:23) INFO: 0 processes.
  (15:49:23) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.33669006438089538555666682975491958411278423465077366450497195282949807817460
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:00:19) Loading:
  (16:00:19) Loading:
  (16:00:19) Loading: 4 packages loaded
  (16:00:19) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:00:19) WARNING: Target pattern parsing failed.
  (16:00:19) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:00:19) INFO: Elapsed time: 17.814s
  (16:00:19) INFO: 0 processes.
  (16:00:19) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.78879431467055594054924068078759240037297464059720525142568970569467061932427
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (15:49:52) Loading:
  (15:49:53) Loading:
  (15:49:53) Loading: 4 packages loaded
  (15:49:53) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:53) WARNING: Target pattern parsing failed.
  (15:49:54) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (15:49:54) INFO: Elapsed time: 23.916s
  (15:49:54) INFO: 0 processes.
  (15:49:54) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.56491264778749619969966170676493831396481270600637256998840704402595163483914
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:00:18) Loading:
  (16:00:19) Loading:
  (16:00:19) Loading: 4 packages loaded
  (16:00:19) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:00:19) WARNING: Target pattern parsing failed.
  (16:00:19) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:00:19) INFO: Elapsed time: 19.185s
  (16:00:19) INFO: 0 processes.
  (16:00:19) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.67242788978463211037813476138351607280964768773712603310802479795237939675579
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (15:49:56) Loading:
  (15:49:57) Loading:
  (15:49:57) Loading: 4 packages loaded
  (15:49:57) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:49:57) WARNING: Target pattern parsing failed.
  (15:49:57) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (15:49:57) INFO: Elapsed time: 33.231s
  (15:49:57) INFO: 0 processes.
  (15:49:57) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.59512832325595745109771943818061512985113988059430503636650646341137806206789
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:00:22) Loading:
  (16:00:22) Loading:
  (16:00:22) Loading: 4 packages loaded
  (16:00:22) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:00:22) WARNING: Target pattern parsing failed.
  (16:00:22) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:00:22) INFO: Elapsed time: 19.761s
  (16:00:22) INFO: 0 processes.
  (16:00:22) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

UVM_ERROR @ * us: (cip_base_vseq.sv:756) [chip_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset. has 20 failures:
- Test chip_csr_mem_rw_with_rand_reset has 20 failures.
  - 0.chip_csr_mem_rw_with_rand_reset.1496672625287430312465775613196838990230980835874571982495501699060862203753
    Line 377, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2882.756021 us: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 2882.756021 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_csr_mem_rw_with_rand_reset.12952627083922204723257346293933743357477342745078384364853558142804472687137
    Line 371, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log
```
  UVM_ERROR @ 2506.449632 us: (cip_base_vseq.sv:756) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Outstanding access never cleared to allow us to reset.
  UVM_INFO @ 2506.449632 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 18 more failures.
Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 9 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 2 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.54897120028505275042915206421990891761529754583055832577045224904860808236212
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:1d1e3cb9-eb87-4d31-9493-17e0b7888b3e
```
  - 2.chip_sw_uart_tx_rx_bootstrap.105228020339305244018705198547669964594835380147718039888743071810232809299538
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:5007661f-3e38-4677-a163-2839d5766261
```
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.111357156681186465973269363563868834531535267125937830347543311697357754960004
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:eb43ef39-471a-448e-923b-3dbf373c486a
```
  - 1.chip_sw_rv_timer_systick_test.73170037295339520073095336947451761258806352719744549356595571886570601771964
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:0db1f57b-1ea4-48c5-9047-58f8d48d4474
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.102829121664705745400395328532220368766417055032002508004722490028175481836510
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:f4d2f624-b6c8-4b6a-a04c-8bfd9b09fcd7
```
  - 1.chip_sw_ast_clk_rst_inputs.42565328256740388200811551537093636821457408356705819277640092055989209534218
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:bf2c29de-6b7d-4f2a-9ffa-e80d69bc238c
```
  - ... and 1 more failures.
- Test chip_sw_uart_tx_rx_alt_clk_freq_low_speed has 1 failures.
  - 4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.92082320119446841391770250131411739318838839654127723621460579411493337435610
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed/latest/run.log
```
  Job ID: smart:99f604e7-2e0a-4b4b-871f-371221c870c4
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 5 failures:
- Test chip_sw_all_escalation_resets has 5 failures.
  - 12.chip_sw_all_escalation_resets.56583125672182459431616061867156484671099136179830806986923927297852015875714
    Line 776, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/12.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2666.153064 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2666.153064 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 18.chip_sw_all_escalation_resets.88798671201638469463613541059381800160628634530755270700138057670273566505750
    Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/18.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2307.854806 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2307.854806 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 3 more failures.

UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 4 failures:

Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_deep_sleep_por_reset.86885502496234599913253204121320289765540274526433952319354464517293900022622
Line 835, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 16544.664171 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 16544.664171 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.chip_sw_pwrmgr_deep_sleep_por_reset.12757676855398298272687761184582043550398579451736057387878934208293906940412
Line 768, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17155.535152 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17155.535152 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

Test chip_sw_pwrmgr_normal_sleep_por_reset has 2 failures.

0.chip_sw_pwrmgr_normal_sleep_por_reset.86869632795362016385568921554986990466641576437343566445911461923615267901279
Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17665.203220 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17665.203220 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

2.chip_sw_pwrmgr_normal_sleep_por_reset.102079877233911361138443782084059805687505371899658445619593781589356254309308
Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

  UVM_ERROR @ 17110.103740 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17110.103740 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_flash_rma_unlocked has 3 failures.
  - 0.chip_sw_flash_rma_unlocked.44498587537050357306132584142125523241304448227551421773276439202653811974647
    Line 715, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_flash_rma_unlocked.85141642207331087986955603117073106064174214859349457093471357933244371404974
    Line 735, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log
```
  UVM_FATAL @ 10010.400001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
  UVM_INFO @ 10010.400001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.10430090410632828372861889094931303106983832430043830787375086347761114109683
    Line 732, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.100001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.100001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.108441345721390934849422997700533986363499786760852725757936136170482767315612
    Line 742, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.280001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:
- Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.
  - 0.chip_sw_csrng_lc_hw_debug_en_test.36329054113508704072261047809015940999626303116397877760340095491224233841309
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.380001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_lc_hw_debug_en_test.39439527937758513207776393622922847810204157195986073989573977171471459734016
    Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log
```
  UVM_FATAL @ 20010.320001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
  UVM_INFO @ 20010.320001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:
- Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.
  - 0.chip_sw_csrng_fuse_en_sw_app_read_test.20907074776327678122835664018974846365867714852299359726918653725068011830931
    Line 737, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.280001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.280001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_csrng_fuse_en_sw_app_read_test.46966899257503266724033724254773898060637189249131923717446755681648209766283
    Line 807, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log
```
  UVM_FATAL @ 10010.240001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
  UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:
- Test chip_sw_sram_ctrl_execution_main has 3 failures.
  - 0.chip_sw_sram_ctrl_execution_main.33496891427091678540662815824440220009933508552601211279758186604018004764354
    Line 733, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.300001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sram_ctrl_execution_main.64913029223212837992981403598383656441649146497242866135748710869244232751353
    Line 769, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log
```
  UVM_FATAL @ 10020.580001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
  UVM_INFO @ 10020.580001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:
- Test chip_sw_lc_ctrl_program_error has 3 failures.
  - 0.chip_sw_lc_ctrl_program_error.1478789318043461704361366257681380368191806247178505173989836230993922643534
    Line 887, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14810.587364 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14810.587364 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 1.chip_sw_lc_ctrl_program_error.64379009033942488921028063088995325505704457605185370567826936670043389257047
    Line 751, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log
```
  UVM_ERROR @ 14570.233160 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 14570.233160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - ... and 1 more failures.
UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 3 failures:
- Test chip_sw_power_virus has 3 failures.
  - 0.chip_sw_power_virus.41284580718549019394572018975602192950421219815857077627689762533625657459872
    Line 952, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 4978.843036 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 4978.843036 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_power_virus.114993952339151114068336311993368891664484129031686792101382301988692740046037
    Line 989, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 6313.752512 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 6313.752512 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.13495958084221642410574294648023397292757028918416380697740392830033576672791
    Line 746, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2364.280500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2364.280500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.47321045550534453264315496351884076122959125596608221560283219145132874350623
    Line 734, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 2279.792000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2279.792000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.40581804305357244349198484775431038217155891952467861979416463056263651800918
    Line 703, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2172.413000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2172.413000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.102638682283565130789890444112854422620960941293510413307700745205886417623021
    Line 773, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 40904.371489 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40904.371489 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.16932947161484157417536088476700303741657393713648450247414571050793376697758
    Line 785, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 51312.866550 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51312.866550 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.54371187057889879054391192784196979970277166212022310661320354763615343109383
    Line 770, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 51490.371750 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 51490.371750 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.105230303964018000155472909407019267370521752818918226278194102153166159130039
Line 758, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9614.568312 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9614.568312 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.73904687662962988792980175969562786583785519202733395207274791659826592613455
Line 743, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9468.214776 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9468.214776 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 3.chip_csr_aliasing.36803956262717767458664698160042810389452549437942774335593339979075021633870
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:af291323-803a-4570-874b-456cc6135fdc
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 46.chip_sw_alert_handler_lpg_sleep_mode_alerts.62726027796891861238621755065394737987413204815461823463515793903712814757757
    Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/46.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3640.178462 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3640.178462 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```