CHIP Simulation Results

Wednesday February 07 2024 20:02:46 UTC

GitHub Revision: `5c87d18988`

Branch: os_regression

Simulator: VCS

Build randomization enabled with --build-seed 42540109002295994234923032062842839138270099951232798724643629525632267455156

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.088m	2.796ms	3	3	100.00
		chip_sw_example_rom	2.144m	1.911ms	3	3	100.00
		chip_sw_example_manufacturer	4.347m	3.031ms	3	3	100.00
		chip_sw_example_concurrency	5.158m	2.834ms	3	3	100.00
		chip_sw_uart_smoketest_signed	37.309m	9.061ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.255m	7.275ms	5	5	100.00
V1	csr_rw	chip_csr_rw	10.137m	6.078ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	2.410h	78.319ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.751h	61.335ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	6.471m	8.624ms	20	20	100.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.751h	61.335ms	4	5	80.00
		chip_csr_rw	10.137m	6.078ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	11.090s	272.851us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.647m	3.216ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.647m	3.216ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.647m	3.216ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.630m	5.950ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.630m	5.950ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	17.998m	6.183ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	19.008m	5.345ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	18.476m	5.643ms	5	5	100.00
V1	chip_sw_uart_rand_baudrate	chip_sw_uart_rand_baudrate	1.085h	23.300ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	50.186m	13.717ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	37.080m	12.751ms	5	5	100.00
V1		TOTAL			222	223	99.55
V2	chip_pin_mux	chip_padctrl_attributes	5.606m	4.682ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	5.606m	4.682ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	6.081m	3.814ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	7.773m	4.930ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.890m	3.870ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	24.220m	14.672ms	5	5	100.00
		chip_tap_straps_testunlock0	9.198m	7.321ms	5	5	100.00
		chip_tap_straps_rma	22.918m	12.627ms	5	5	100.00
		chip_tap_straps_prod	17.150m	10.125ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	3.857m	2.862ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	31.415m	9.104ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	14.951m	6.606ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	14.951m	6.606ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	19.750m	7.508ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	16.766m	4.690ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.967m	6.368ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.036h	19.026ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.236m	2.699ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.074m	5.767ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.798m	3.647ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.326m	5.509ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.206m	3.136ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.765m	4.452ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.024m	2.713ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.858m	3.035ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	17.064m	6.276ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	17.064m	6.276ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.106m	4.943ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.622m	3.459ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	9.106m	4.943ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	5.080m	3.208ms	3	3	100.00
		chip_sw_aes_smoketest	5.560m	2.953ms	3	3	100.00
		chip_sw_aon_timer_smoketest	6.951m	3.219ms	3	3	100.00
		chip_sw_clkmgr_smoketest	5.370m	2.739ms	3	3	100.00
		chip_sw_csrng_smoketest	4.939m	2.951ms	3	3	100.00
		chip_sw_entropy_src_smoketest	11.492m	3.993ms	3	3	100.00
		chip_sw_gpio_smoketest	5.957m	3.338ms	3	3	100.00
		chip_sw_hmac_smoketest	6.625m	3.297ms	3	3	100.00
		chip_sw_kmac_smoketest	5.925m	2.780ms	3	3	100.00
		chip_sw_otbn_smoketest	32.104m	10.980ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.335m	2.925ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.918m	5.125ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	6.134m	5.450ms	3	3	100.00
		chip_sw_rv_plic_smoketest	5.166m	2.652ms	3	3	100.00
		chip_sw_rv_timer_smoketest	3.635m	2.805ms	3	3	100.00
		chip_sw_rstmgr_smoketest	5.448m	3.099ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.557m	2.581ms	3	3	100.00
		chip_sw_uart_smoketest	5.228m	2.860ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.374m	4.222ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	37.309m	9.061ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.646h	77.640ms	2	3	66.67
V2	chip_sw_secure_boot	rom_e2e_smoke	40.589m	8.886ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	39.404m	14.719ms	2	3	66.67
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.849m	4.602ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.473m	10.575ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	3.458h	57.964ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.542h	64.742ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	6.766m	4.477ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	6.766m	4.477ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.751h	61.335ms	4	5	80.00
		chip_same_csr_outstanding	1.168h	31.005ms	20	20	100.00
		chip_csr_hw_reset	6.255m	7.275ms	5	5	100.00
		chip_csr_rw	10.137m	6.078ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.751h	61.335ms	4	5	80.00
		chip_same_csr_outstanding	1.168h	31.005ms	20	20	100.00
		chip_csr_hw_reset	6.255m	7.275ms	5	5	100.00
		chip_csr_rw	10.137m	6.078ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.575m	2.610ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.220s	54.958us	100	100	100.00
		xbar_smoke_large_delays	1.995m	10.316ms	100	100	100.00
		xbar_smoke_slow_rsp	2.309m	7.361ms	100	100	100.00
		xbar_random_zero_delays	52.720s	550.884us	100	100	100.00
		xbar_random_large_delays	22.694m	116.341ms	100	100	100.00
		xbar_random_slow_rsp	21.062m	73.918ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	58.460s	1.297ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.020s	1.342ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.579m	2.486ms	100	100	100.00
		xbar_error_and_unmapped_addr	59.020s	1.342ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.534m	3.325ms	100	100	100.00
		xbar_access_same_device_slow_rsp	52.502m	160.030ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.493m	2.730ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	14.827m	20.817ms	100	100	100.00
		xbar_stress_all_with_error	10.559m	16.817ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	21.114m	27.391ms	100	100	100.00
		xbar_stress_all_with_reset_error	19.600m	8.840ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	40.589m	8.886ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	54.009m	24.924ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	36.403m	8.670ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	30.581m	7.161ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	35.108m	9.152ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	34.118m	8.882ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	35.417m	8.642ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	32.829m	8.804ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.654m	6.402ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	32.761m	8.879ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	35.137m	8.844ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	35.765m	8.348ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	33.475m	8.438ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	42.058m	10.598ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	54.666m	11.998ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	48.622m	12.218ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	46.553m	11.772ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	49.651m	12.406ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	45.496m	10.186ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	50.620m	12.070ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	46.734m	11.874ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	53.604m	11.427ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	56.427m	12.041ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	25.517m	7.147ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	38.302m	9.003ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	31.846m	8.680ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	39.839m	9.037ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.971m	8.538ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	27.021m	6.934ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	38.739m	8.536ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	31.535m	9.127ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	34.069m	9.067ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	36.486m	8.307ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	26.121m	7.164ms	3	3	100.00
		rom_e2e_asm_init_dev	36.807m	9.674ms	3	3	100.00
		rom_e2e_asm_init_prod	39.272m	8.476ms	3	3	100.00
		rom_e2e_asm_init_prod_end	37.781m	8.065ms	3	3	100.00
		rom_e2e_asm_init_rma	34.432m	8.541ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	40.891m	10.790ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.014m	2.924ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.236m	2.699ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	4.565m	2.594ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	4.641m	2.103ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	11.268m	4.148ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.305m	19.101ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.305m	19.101ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	9.022m	4.156ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	7.918m	5.125ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	9.022m	4.156ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.171m	9.614ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	18.171m	9.614ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.104m	6.318ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	15.245m	6.333ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	20.092m	6.048ms	3	3	100.00
		chip_sw_aes_idle	4.641m	2.103ms	3	3	100.00
		chip_sw_hmac_enc_idle	5.936m	3.441ms	3	3	100.00
		chip_sw_kmac_idle	3.831m	2.573ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	11.180m	5.759ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	10.344m	3.933ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	8.363m	3.755ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	11.041m	4.342ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	21.257m	10.975ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.340m	4.191ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.182m	4.994ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.679m	4.594ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.431m	5.259ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.216m	4.022ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.351m	4.693ms	3	3	100.00
		chip_sw_ast_clk_outputs	19.750m	7.508ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	15.637m	13.980ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.679m	4.594ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.431m	5.259ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	16.766m	4.690ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.967m	6.368ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.036h	19.026ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	5.236m	2.699ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	18.074m	5.767ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.798m	3.647ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.326m	5.509ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.206m	3.136ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.765m	4.452ms	3	3	100.00
		chip_sw_clkmgr_jitter	4.024m	2.713ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.230m	3.349ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	18.856m	5.571ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	19.868m	7.487ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.189h	24.086ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	4.957m	2.970ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.930m	2.981ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	7.691m	4.330ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	5.534m	3.269ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	12.630m	5.413ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.356m	22.379ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	1.118h	23.179ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	19.750m	7.508ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	12.346m	4.643ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	8.529m	3.704ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	36.120m	8.958ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	31.712m	7.013ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	9.499m	4.787ms	3	3	100.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	15.631m	10.868ms	3	3	100.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	6.235m	3.157ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.932m	7.511ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	37.009m	24.980ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.553m	3.717ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	39.630s	10.360us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	12.773m	4.184ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	37.009m	24.980ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	37.009m	24.980ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	55.562m	20.263ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	55.562m	20.263ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	11.316m	5.189ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	12.305m	19.101ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	1.145h	15.996ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.829m	2.438ms	3	3	100.00
		chip_sw_edn_entropy_reqs	22.507m	5.762ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.829m	2.438ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	31.712m	7.013ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	3.377m	2.804ms	3	3	100.00
V2	chip_sw_flash_init	chip_sw_flash_init	43.349m	22.657ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	21.097m	6.005ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	21.967m	6.368ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	19.426m	4.399ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	16.766m	4.690ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	1.403h	44.583ms	1	3	33.33
V2	chip_sw_flash_scramble	chip_sw_flash_init	43.349m	22.657ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	7.169m	3.423ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	9.926m	5.216ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.418m	5.771ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	1.403h	44.583ms	1	3	33.33
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	9.418m	5.771ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.418m	5.771ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	9.418m	5.771ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	9.418m	5.771ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	9.373m	10.906ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	22.789m	5.701ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	14.326m	4.977ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	14.326m	4.977ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	6.824m	3.347ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.798m	3.647ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	5.936m	3.441ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	20.223m	5.588ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	18.356m	5.445ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	15.876m	6.150ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	12.106m	4.123ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	9.926m	5.216ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	11.326m	5.509ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	10.122m	3.790ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	11.268m	4.148ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.344h	17.905ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	5.921m	2.926ms	3	3	100.00
		chip_sw_kmac_mode_kmac	6.888m	2.915ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	7.206m	3.136ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	9.926m	5.216ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	5.419m	2.542ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.655m	2.779ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	3.831m	2.573ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	11.812m	4.666ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	24.220m	14.672ms	5	5	100.00
		chip_tap_straps_rma	22.918m	12.627ms	5	5	100.00
		chip_tap_straps_prod	17.150m	10.125ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.484m	2.782ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	8.832m	4.093ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	9.418m	5.771ms	3	3	100.00
		chip_sw_flash_rma_unlocked	1.403h	44.583ms	1	3	33.33
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.572m	9.978ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.388m	8.757ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.244m	7.848ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.167m	7.541ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
		chip_sw_keymgr_key_derivation	9.926m	5.216ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	12.971m	9.682ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	16.645m	9.165ms	3	3	100.00
		chip_prim_tl_access	9.373m	10.906ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	15.637m	13.980ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	12.340m	4.191ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	14.182m	4.994ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	11.679m	4.594ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	12.431m	5.259ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	13.216m	4.022ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	13.351m	4.693ms	3	3	100.00
		chip_tap_straps_dev	24.220m	14.672ms	5	5	100.00
		chip_tap_straps_rma	22.918m	12.627ms	5	5	100.00
		chip_tap_straps_prod	17.150m	10.125ms	5	5	100.00
		chip_rv_dm_lc_disabled	8.428m	13.497ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.255m	2.358ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.754m	3.406ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.226m	3.668ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	5.120m	3.092ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	40.321m	31.460ms	3	3	100.00
		chip_rv_dm_lc_disabled	8.428m	13.497ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.764h	133.164ms	1	3	33.33
		chip_sw_lc_walkthrough_prod			0	3	0.00
		chip_sw_lc_walkthrough_prodend	19.869m	15.250ms	3	3	100.00
		chip_sw_lc_walkthrough_rma			0	3	0.00
		chip_sw_lc_walkthrough_testunlocks	40.321m	31.460ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	5.230m	6.060ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	5.504m	4.534ms	3	3	100.00
		rom_volatile_raw_unlock	36.180m	12.611ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	43.349m	22.657ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.231m	3.387ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.926m	5.216ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.930m	4.486ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.155m	2.535ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	43.349m	22.657ms	3	3	100.00
		chip_sw_otbn_mem_scramble	9.231m	3.387ms	3	3	100.00
		chip_sw_keymgr_key_derivation	9.926m	5.216ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	12.930m	4.486ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	5.155m	2.535ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	10.372m	5.217ms	3	3	100.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	6.484m	2.782ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	15.572m	9.978ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	21.388m	8.757ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	23.244m	7.848ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.167m	7.541ms	3	3	100.00
		chip_sw_lc_ctrl_transition	20.838m	10.389ms	15	15	100.00
		chip_prim_tl_access	9.373m	10.906ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	9.373m	10.906ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	9.937m	8.153ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	33.873m	21.225ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	9.300m	7.213ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	12.810m	18.350ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	9.694m	15.714ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	29.642m	22.807ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	27.237m	18.750ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	18.171m	9.614ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	24.427m	11.935ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.206m	5.750ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	9.937m	8.153ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	6.529m	3.155ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	58.697m	35.414ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	8.994m	6.615ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	11.115m	6.596ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	47.364m	23.289ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	19.932m	7.511ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	32.691m	13.054ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	47.345m	22.252ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	6.547m	3.468ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	12.971m	9.682ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	12.971m	9.682ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	32.691m	13.054ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	47.364m	23.289ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.206m	5.750ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	7.918m	5.125ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	8.104m	5.227ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	15.186m	7.765ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	9.149m	3.790ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	32.912m	13.903ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.904m	2.440ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	36.927m	8.631ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	24.876m	6.086ms	3	3	100.00
		chip_plic_all_irqs_10	11.918m	3.515ms	3	3	100.00
		chip_plic_all_irqs_20	13.452m	4.858ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	4.234m	2.849ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	4.487m	3.524ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	40.589m	8.886ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.351m	7.535ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	9.286m	4.206ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.594m	3.246ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	7.277m	2.461ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	12.930m	4.486ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	12.765m	4.452ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	11.442m	6.588ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	15.172m	9.036ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	16.645m	9.165ms	3	3	100.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
		chip_sw_data_integrity_escalation	14.951m	6.606ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	4.615m	2.940ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	3.417m	3.380ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup			0	0	--
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	8.775m	4.480ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host			0	0	--
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.739h	31.331ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	45.476m	12.380ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.103m	3.493ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	11.812m	4.666ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.584m	3.010ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	32.912m	13.903ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	7.370m	4.472ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	9.723m	4.148ms	89	90	98.89
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	21.872m	11.337ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	36.120m	8.958ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	36.927m	8.631ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.638h	255.404ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	45.445m	19.972ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	27.353m	13.829ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	8.104m	5.227ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	12.511m	4.292ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	8.977m	5.218ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	22.918m	12.627ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	8.428m	13.497ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2593	2655	97.66
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	6.564m	2.941ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark	2.740h	50.243ms	1	1	100.00
V3	chip_sw_power_max_load	chip_sw_power_virus	16.874m	5.090ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	1.857m	2.024ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.933m	1.955ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.946m	2.047ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	44.104m	30.640ms	0	1	0.00
		rom_e2e_jtag_inject_dev	42.390m	41.145ms	0	1	0.00
		rom_e2e_jtag_inject_rma	1.189h	40.540ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	43.785m	9.498ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.877m	2.747ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.590m	2.590ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	20.204m	5.384ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	35.697m	10.324ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	12.790m	3.444ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	21.546m	5.730ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.048m	2.577ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	9.586m	6.127ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	9.423m	5.406ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	9.662m	3.905ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	32.691m	13.054ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.135m	5.353ms	99	100	99.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.630m	5.950ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.227h	18.464ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	1.857m	2.024ms	0	1	0.00
		rom_e2e_jtag_debug_dev	1.933m	1.955ms	0	1	0.00
		rom_e2e_jtag_debug_rma	1.946m	2.047ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	10.724m	5.512ms	3	3	100.00
V3		TOTAL			33	48	68.75
	Unmapped tests	chip_sival_flash_info_access	10.011m	4.096ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.602m	5.602ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.046h	16.748ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	22.212m	6.006ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	15.853m	4.880ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	10.508m	5.751ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	4.244m	2.308ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	5.489m	2.275ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2875	2956	97.26

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	18	94.74
V2	288	274	249	86.46
V2S	1	1	1	100.00
V3	91	22	13	14.29

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.37	95.45	94.67	95.51	--	95.45	97.57	99.58

Failure Buckets

Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

Test chip_sw_flash_ctrl_write_clear has 3 failures.

0.chip_sw_flash_ctrl_write_clear.95030917937952289085944680366138929275323055640544956798695616098383845059481
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:27:40) Loading:
  (16:27:40) Loading:
  (16:27:40) Loading: 4 packages loaded
  (16:27:41) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:27:41) WARNING: Target pattern parsing failed.
  (16:27:41) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:27:41) INFO: Elapsed time: 24.729s
  (16:27:41) INFO: 0 processes.
  (16:27:41) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.chip_sw_flash_ctrl_write_clear.105959723602055194506032683385497155647049304986867467539917995603742029038888
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

  (16:38:48) Loading:
  (16:38:49) Loading:
  (16:38:49) Loading: 4 packages loaded
  (16:38:49) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:38:49) WARNING: Target pattern parsing failed.
  (16:38:49) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
  (16:38:49) INFO: Elapsed time: 33.740s
  (16:38:49) INFO: 0 processes.
  (16:38:49) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_meas.108507819241064025023045019261450074255194506465062410024688313396939462890514
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:28:59) Loading:
  (16:29:00) Loading:
  (16:29:00) Loading: 4 packages loaded
  (16:29:00) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:29:00) WARNING: Target pattern parsing failed.
  (16:29:00) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:29:00) INFO: Elapsed time: 22.043s
  (16:29:00) INFO: 0 processes.
  (16:29:00) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_meas.52101467321243818945464113015127533163986732416161574847185382991529916814047
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

  (16:39:37) Loading:
  (16:39:38) Loading:
  (16:39:38) Loading: 4 packages loaded
  (16:39:38) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:39:38) WARNING: Target pattern parsing failed.
  (16:39:38) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:39:38) INFO: Elapsed time: 18.994s
  (16:39:38) INFO: 0 processes.
  (16:39:38) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_no_meas.78121608613761546252209717353274411721663600925716448951866929025863609756397
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:31:38) Loading:
  (16:31:39) Loading:
  (16:31:39) Loading: 4 packages loaded
  (16:31:40) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:31:40) WARNING: Target pattern parsing failed.
  (16:31:40) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:31:40) INFO: Elapsed time: 104.618s
  (16:31:40) INFO: 0 processes.
  (16:31:40) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_no_meas.8899191973338077223128124703515159057308781355728396264958502518206223625921
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

  (16:39:34) Loading:
  (16:39:35) Loading:
  (16:39:35) Loading: 4 packages loaded
  (16:39:35) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:39:35) WARNING: Target pattern parsing failed.
  (16:39:35) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:39:35) INFO: Elapsed time: 21.157s
  (16:39:35) INFO: 0 processes.
  (16:39:35) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

0.rom_e2e_keymgr_init_rom_ext_invalid_meas.25325075769630367863903018484477171120368183909099750102131410648918217119137
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:29:14) Loading:
  (16:29:15) Loading:
  (16:29:15) Loading: 4 packages loaded
  (16:29:15) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:29:15) WARNING: Target pattern parsing failed.
  (16:29:15) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:29:15) INFO: Elapsed time: 23.410s
  (16:29:15) INFO: 0 processes.
  (16:29:15) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_keymgr_init_rom_ext_invalid_meas.23573309265523929303396980923751433696678867330713882148488795314931569465912
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

  (16:39:31) Loading:
  (16:39:31) Loading:
  (16:39:31) Loading: 4 packages loaded
  (16:39:32) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:39:32) WARNING: Target pattern parsing failed.
  (16:39:32) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
  (16:39:32) INFO: Elapsed time: 20.501s
  (16:39:32) INFO: 0 processes.
  (16:39:32) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.102353193772050493209254272993263251576843475695643463073851611276367259979909
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:29:12) Loading:
  (16:29:13) Loading:
  (16:29:13) Loading: 4 packages loaded
  (16:29:13) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:29:13) WARNING: Target pattern parsing failed.
  (16:29:13) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:29:13) INFO: Elapsed time: 19.969s
  (16:29:13) INFO: 0 processes.
  (16:29:13) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.72419186846684719296291881041459373215020421132046376361130461307335809275716
Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

  (16:40:05) Loading:
  (16:40:06) Loading:
  (16:40:06) Loading: 4 packages loaded
  (16:40:06) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:40:06) WARNING: Target pattern parsing failed.
  (16:40:06) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
  (16:40:06) INFO: Elapsed time: 18.071s
  (16:40:06) INFO: 0 processes.
  (16:40:06) FAILED: Build did NOT complete successfully (5 packages loaded)
  make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1

... and 1 more failures.

... and 9 more tests.

Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 19 failures:
- Test chip_sw_uart_tx_rx_bootstrap has 1 failures.
  - 0.chip_sw_uart_tx_rx_bootstrap.81420274932204400282491462982486475252241888275205013187458668507001563056170
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_uart_tx_rx_bootstrap/latest/run.log
```
  Job ID: smart:17c396ed-e9e6-47bb-9620-a904091f04f2
```
- Test chip_sw_lc_walkthrough_prod has 3 failures.
  - 0.chip_sw_lc_walkthrough_prod.35004025553260964313333421706777310207540999450363778698062411466571520285651
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:e1f7a109-0862-4943-9418-139a6fe0f321
```
  - 1.chip_sw_lc_walkthrough_prod.104618614388402041076534810697834104525917655814494942601591767110731786442846
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_prod/latest/run.log
```
  Job ID: smart:122c13fa-4e53-4dfb-9fb3-b9db9c1fdaed
```
  - ... and 1 more failures.
- Test chip_sw_lc_walkthrough_rma has 3 failures.
  - 0.chip_sw_lc_walkthrough_rma.52764951322296725518036317154032085227928245109503923991823972540485750445710
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:874365db-4d46-4f23-8af8-8c866efa03df
```
  - 1.chip_sw_lc_walkthrough_rma.70629436594532478210547067214642595679453075991687613613711323138105187897086
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_walkthrough_rma/latest/run.log
```
  Job ID: smart:5d2f0681-b821-4fb4-937c-b668c67e9f73
```
  - ... and 1 more failures.
- Test chip_sw_rv_timer_systick_test has 3 failures.
  - 0.chip_sw_rv_timer_systick_test.101796578025283193501901256292321913196088289360419964971899716880025038989929
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:e351f259-9739-416a-9d04-27b8f800be63
```
  - 1.chip_sw_rv_timer_systick_test.52220041349872017219269478314762547919649131122784658479227580832542556030389
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log
```
  Job ID: smart:51440481-85f5-4d7e-894b-c2a6eadab155
```
  - ... and 1 more failures.
- Test chip_sw_ast_clk_rst_inputs has 3 failures.
  - 0.chip_sw_ast_clk_rst_inputs.39886422306278207823263049095370732080827004156637961657206411428433565859271
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:096186bb-b820-4e88-8aca-24fa2949026e
```
  - 1.chip_sw_ast_clk_rst_inputs.110356309068539059410567656124384566671019243237047344052269859787878534338097
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log
```
  Job ID: smart:a6d4d640-1751-46a7-9f12-77da36ac5f2c
```
  - ... and 1 more failures.
- ... and 4 more tests.
UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:
- Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.
  - 0.chip_sw_pwrmgr_normal_sleep_por_reset.47376989493159118460185011600480197519316033645016719723837494852743428082094
    Line 792, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 15714.149237 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 15714.149237 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.
  - 1.chip_sw_pwrmgr_deep_sleep_por_reset.25070043834675930131373231933229046908090497376249169550857023413640496085090
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 18350.333597 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 18350.333597 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
```
  - 2.chip_sw_pwrmgr_deep_sleep_por_reset.56983055309357394247524407021690802369615813141403757269089577750643746379851
    Line 774, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log
```
  UVM_ERROR @ 17719.708997 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
  
  UVM_INFO @ 17719.708997 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:
- Test chip_sw_sysrst_ctrl_outputs has 3 failures.
  - 0.chip_sw_sysrst_ctrl_outputs.93619917132542775596476365044041969994183641894049914201915562408455114352363
    Line 761, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 1.chip_sw_sysrst_ctrl_outputs.50910931595934005801639561319264777746884786685785027329258630408995039177891
    Line 766, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log
```
  UVM_FATAL @  10.200001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
  UVM_INFO @  10.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - ... and 1 more failures.
UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:
- Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_debug_test_unlocked0.1720660404437863738735269299840582695540005479717857911390096145468093209953
    Line 729, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log
```
  UVM_FATAL @ 2023.730000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2023.730000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_dev has 1 failures.
  - 0.rom_e2e_jtag_debug_dev.61301193800008896140788807743972859397669203797024708701623579622963197845406
    Line 747, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log
```
  UVM_FATAL @ 1955.128000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 1955.128000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_debug_rma has 1 failures.
  - 0.rom_e2e_jtag_debug_rma.3882661280175601273730132352259373238621213248305826802219440372025819333450
    Line 743, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log
```
  UVM_FATAL @ 2046.782500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
  UVM_INFO @ 2046.782500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```

UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

Test rom_e2e_self_hash has 3 failures.

0.rom_e2e_self_hash.33802049806526762738151801011263004756428415781020289423362709173163256874739
Line 808, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 9497.791032 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 9497.791032 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

1.rom_e2e_self_hash.61704210494049713459091728509257280808454798009855952116078758712981542643035
Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

  UVM_ERROR @ 10115.772760 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
  UVM_INFO @ 10115.772760 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---

... and 1 more failures.

UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 2 failures:
- Test chip_sw_power_virus has 2 failures.
  - 0.chip_sw_power_virus.70523484907544699025614354702253551313446643894274976752635720185116441788901
    Line 988, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5090.408336 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5090.408336 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
  
  
```
  - 2.chip_sw_power_virus.42640237232987426945164732887614193509317144582007114940504149762253027243678
    Line 955, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log
```
  UVM_ERROR @ 5052.921069 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
  UVM_INFO @ 5052.921069 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 2 failures:
- Test rom_e2e_jtag_inject_dev has 1 failures.
  - 0.rom_e2e_jtag_inject_dev.93110535918126475353707622019042930726319739957404178533412480736944126285615
    Line 767, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log
```
  UVM_FATAL @ 41145.223621 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 41145.223621 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
- Test rom_e2e_jtag_inject_rma has 1 failures.
  - 0.rom_e2e_jtag_inject_rma.79216156219665964881838963486395164768341063363134934763094359096657602542071
    Line 788, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log
```
  UVM_FATAL @ 40540.033595 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
  UVM_INFO @ 40540.033595 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:
- Test chip_csr_aliasing has 1 failures.
  - 0.chip_csr_aliasing.19952747096948917930974612744726292642112171234835470832206648487122532662335
    Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_aliasing/latest/run.log
```
  Job ID: smart:bcc56a11-448e-4362-9005-b902ead5004c
```
UVM_ERROR @ * us: (csr_utils_pkg.sv:367) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (* [*] vs * [*]) trying to read csr/field jtag_dmi_ral.dmstatus has 1 failures:
- Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.
  - 0.rom_e2e_jtag_inject_test_unlocked0.61897682011904085107894405581985535129814990542035405972247009642727621739587
    Line 764, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log
```
  UVM_ERROR @ 30640.497413 us: (csr_utils_pkg.sv:367) [csr_utils::csr_rd] Check failed status == UVM_IS_OK (1 [0x1] vs 0 [0x0]) trying to read csr/field jtag_dmi_ral.dmstatus
  UVM_INFO @ 30640.497413 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 1 failures:
- Test chip_sw_all_escalation_resets has 1 failures.
  - 80.chip_sw_all_escalation_resets.61012910245729382124166642896217285994935025083266518860859526749436956709477
    Line 750, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/80.chip_sw_all_escalation_resets/latest/run.log
```
  UVM_ERROR @ 2360.538178 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
  UVM_INFO @ 2360.538178 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```
UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 1 failures:
- Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 1 failures.
  - 84.chip_sw_alert_handler_lpg_sleep_mode_alerts.28570862535088220208547938311300460075763421176830862526071446952743759423550
    Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/84.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log
```
  UVM_ERROR @ 3448.389066 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a12 MTVAL=40600800
  UVM_INFO @ 3448.389066 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
  --- UVM Report catcher Summary ---
```