Unified Coverage Report :: Module :: i2c

Module : i2c

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_i2c_0.1/rtl/i2c.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_i2c0	100.00			100.00
tb.dut.top_earlgrey.u_i2c1	100.00			100.00
tb.dut.top_earlgrey.u_i2c2	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_i2c0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.25	89.21		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.25	89.21		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_i2c2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.25	89.21		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : i2c

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	328	328	100.00
Total Bits 0->1	164	164	100.00
Total Bits 1->0	164	164	100.00

Ports	48	48	100.00
Port Bits	328	328	100.00
Port Bits 0->1	164	164	100.00
Port Bits 1->0	164	164	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_i.a_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	INPUT
tl_o.a_ready	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
tl_o.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T176,*T274	Yes	T265,T176,T274	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T114,T293	Yes	T55,T114,T293	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T116,T195,T113	Yes	T116,T195,T113	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T116,T195,T113	Yes	T116,T195,T113	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T114,T293	Yes	T55,T114,T293	OUTPUT
cio_scl_i	Yes	Yes	T274,T278,T281	Yes	T274,T278,T281	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T176,T274,T278	Yes	T176,T274,T278	OUTPUT
cio_sda_i	Yes	Yes	T274,T278,T281	Yes	T274,T278,T281	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T176,T274,T278	Yes	T176,T274,T278	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	OUTPUT
intr_rx_threshold_o	Yes	Yes	T265,T274,T278	Yes	T265,T274,T278	OUTPUT
intr_acq_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_nak_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_scl_interference_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_interference_o	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_unstable_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_cmd_complete_o	Yes	Yes	T265,T274,T278	Yes	T265,T274,T278	OUTPUT
intr_tx_stretch_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_tx_threshold_o	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	OUTPUT
intr_acq_full_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_unexp_stop_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_host_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c0

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	324	324	100.00
Total Bits 0->1	162	162	100.00
Total Bits 1->0	162	162	100.00

Ports	48	48	100.00
Port Bits	324	324	100.00
Port Bits 0->1	162	162	100.00
Port Bits 1->0	162	162	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[18:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_i.a_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	INPUT
tl_o.a_ready	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
tl_o.d_error	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T176,T274	Yes	T265,T176,T274	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T176,*T274	Yes	T265,T176,T274	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T114,T116	Yes	T55,T114,T116	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T116,T195,T76	Yes	T116,T195,T76	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T116,T195,T76	Yes	T116,T195,T76	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T114,T116	Yes	T55,T114,T116	OUTPUT
cio_scl_i	Yes	Yes	T274,T254,T290	Yes	T274,T254,T290	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T176,T274,T254	Yes	T176,T274,T254	OUTPUT
cio_sda_i	Yes	Yes	T274,T254,T290	Yes	T274,T254,T290	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T176,T274,T254	Yes	T176,T274,T254	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T265,T274,T272	Yes	T265,T274,T272	OUTPUT
intr_rx_threshold_o	Yes	Yes	T265,T274,T272	Yes	T265,T274,T272	OUTPUT
intr_acq_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_nak_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_scl_interference_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_interference_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_unstable_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_cmd_complete_o	Yes	Yes	T265,T274,T272	Yes	T265,T274,T272	OUTPUT
intr_tx_stretch_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_tx_threshold_o	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	OUTPUT
intr_acq_full_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_unexp_stop_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_host_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c1

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	326	326	100.00
Total Bits 0->1	163	163	100.00
Total Bits 1->0	163	163	100.00

Ports	48	48	100.00
Port Bits	326	326	100.00
Port Bits 0->1	163	163	100.00
Port Bits 1->0	163	163	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[15:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_i.a_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	INPUT
tl_o.a_ready	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
tl_o.d_error	Yes	Yes	T72,T74,T105	Yes	T72,T74,T105	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T75,T105	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T176,*T272	Yes	T265,T176,T272	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T114,T293	Yes	T55,T114,T293	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T195,T113,T76	Yes	T195,T113,T76	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T195,T113,T76	Yes	T195,T113,T76	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T114,T293	Yes	T55,T114,T293	OUTPUT
cio_scl_i	Yes	Yes	T291,T277,T368	Yes	T291,T277,T368	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T176,T277,T368	Yes	T176,T277,T368	OUTPUT
cio_sda_i	Yes	Yes	T291,T277,T368	Yes	T291,T277,T368	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T291,T277,T368	Yes	T291,T277,T368	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_rx_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_acq_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_nak_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_scl_interference_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_interference_o	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_unstable_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_cmd_complete_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_tx_stretch_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_tx_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_acq_full_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_unexp_stop_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_host_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_i2c2

	Total	Covered	Percent
Totals	48	48	100.00
Total Bits	326	326	100.00
Total Bits 0->1	163	163	100.00
Total Bits 1->0	163	163	100.00

Ports	48	48	100.00
Port Bits	326	326	100.00
Port Bits 0->1	163	163	100.00
Port Bits 1->0	163	163	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T265,T176,T278	Yes	T265,T176,T278	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T265,T176,T278	Yes	T265,T176,T278	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[6:0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_i.a_address[16:7]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[19]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:20]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_i.a_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	INPUT
tl_o.a_ready	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
tl_o.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T265,T176,T278	Yes	T265,T176,T278	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T114,T265,T263	Yes	T55,T114,T265	OUTPUT
tl_o.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T265,*T176,*T278	Yes	T265,T176,T278	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T55,T114,T265	Yes	T55,T114,T265	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T55,T114,T195	Yes	T55,T114,T195	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T195,T76,T77	Yes	T195,T76,T77	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T195,T76,T77	Yes	T195,T76,T77	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T55,T114,T195	Yes	T55,T114,T195	OUTPUT
cio_scl_i	Yes	Yes	T278,T281,T369	Yes	T278,T281,T369	INPUT
cio_scl_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_scl_en_o	Yes	Yes	T176,T278,T281	Yes	T176,T278,T281	OUTPUT
cio_sda_i	Yes	Yes	T278,T281,T369	Yes	T278,T281,T369	INPUT
cio_sda_o	Unreachable	Unreachable		Unreachable		OUTPUT
cio_sda_en_o	Yes	Yes	T176,T278,T281	Yes	T176,T278,T281	OUTPUT
intr_fmt_threshold_o	Yes	Yes	T265,T176,T278	Yes	T265,T176,T278	OUTPUT
intr_rx_threshold_o	Yes	Yes	T265,T278,T272	Yes	T265,T278,T272	OUTPUT
intr_acq_threshold_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_rx_overflow_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_nak_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_scl_interference_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_interference_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_stretch_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_sda_unstable_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_cmd_complete_o	Yes	Yes	T265,T278,T272	Yes	T265,T278,T272	OUTPUT
intr_tx_stretch_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_tx_threshold_o	Yes	Yes	T265,T176,T272	Yes	T265,T176,T272	OUTPUT
intr_acq_full_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_unexp_stop_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT
intr_host_timeout_o	Yes	Yes	T265,T272,T273	Yes	T265,T272,T273	OUTPUT

*Tests covering at least one bit in the range