Unified Coverage Report :: Module :: top_earlgrey

Module : top_earlgrey

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
83.00	89.21		59.80			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey	94.25	89.21		93.54			100.00

---

Module Instance : tb.dut.top_earlgrey

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.25	89.21		93.54			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
95.22	95.35	93.83	94.98		94.70	97.23

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
91.07	76.19	100.00	97.01				dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
clk_ctrl_and_main_pd_sva_if	100.00			100.00
u_adc_ctrl_aon	100.00			100.00
u_aes	100.00			100.00
u_alert_handler	99.92			99.92
u_aon_timer_aon	100.00			100.00
u_clkmgr_aon	100.00			100.00
u_csrng	99.72			99.72
u_dft_tap_breakout	100.00	100.00		100.00
u_edn0	99.50			99.50
u_edn1	99.58			99.58
u_entropy_src	99.18			99.18
u_flash_ctrl	99.96			99.96
u_gpio	100.00			100.00
u_hmac	100.00			100.00
u_i2c0	100.00			100.00
u_i2c1	100.00			100.00
u_i2c2	100.00			100.00
u_keymgr	89.72			89.72
u_kmac	99.94			99.94
u_lc_ctrl	88.57			88.57
u_otbn	100.00			100.00
u_otp_ctrl	81.89			81.89
u_pattgen	100.00			100.00
u_pinmux_aon	97.20	96.22	95.50	98.78		96.23	99.30
u_pwm_aon	100.00			100.00
u_pwrmgr_aon	100.00			100.00
u_rom_ctrl	99.96			99.96
u_rstmgr_aon	100.00			100.00
u_rv_core_ibex	96.56	97.60	95.36	98.89		98.13	92.81
u_rv_dm	100.00			100.00
u_rv_plic	94.81	93.89	90.99	100.00		92.76	96.43
u_rv_timer	100.00			100.00
u_sensor_ctrl_aon	93.71	92.00	89.50	93.39		93.65	100.00
u_spi_device	98.42			98.42
u_spi_host0	96.59			96.59
u_spi_host1	93.83			93.83
u_sram_ctrl_main	100.00			100.00
u_sram_ctrl_ret_aon	100.00			100.00
u_sysrst_ctrl_aon	100.00			100.00
u_uart0	100.00			100.00
u_uart1	100.00			100.00
u_uart2	100.00			100.00
u_uart3	100.00			100.00
u_usbdev	95.02			95.02
u_xbar_main	100.00			100.00
u_xbar_peri	100.00			100.00

Line Coverage for Module : top_earlgrey

	Line No.	Total	Covered	Percent
TOTAL		278	248	89.21
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	0	0.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	768	1	0	0.00
CONT_ASSIGN	769	1	0	0.00
CONT_ASSIGN	770	1	0	0.00
CONT_ASSIGN	771	1	0	0.00
CONT_ASSIGN	772	1	0	0.00
CONT_ASSIGN	773	1	0	0.00
CONT_ASSIGN	774	1	0	0.00
CONT_ASSIGN	788	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	810	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	842	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	852	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
CONT_ASSIGN	861	1	1	100.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	864	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	867	1	1	100.00
CONT_ASSIGN	869	1	0	0.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	872	1	0	0.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	881	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
CONT_ASSIGN	885	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	888	1	1	100.00
CONT_ASSIGN	890	1	1	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	894	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	899	1	1	100.00
CONT_ASSIGN	900	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	905	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	908	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	915	0	0
CONT_ASSIGN	917	0	0
CONT_ASSIGN	919	0	0
CONT_ASSIGN	921	0	0
CONT_ASSIGN	923	0	0
CONT_ASSIGN	925	0	0
CONT_ASSIGN	927	0	0
CONT_ASSIGN	929	0	0
CONT_ASSIGN	931	0	0
CONT_ASSIGN	933	0	0
CONT_ASSIGN	935	0	0
CONT_ASSIGN	937	0	0
CONT_ASSIGN	939	0	0
CONT_ASSIGN	941	0	0
CONT_ASSIGN	943	0	0
CONT_ASSIGN	945	0	0
CONT_ASSIGN	947	0	0
CONT_ASSIGN	949	0	0
CONT_ASSIGN	951	0	0
CONT_ASSIGN	953	0	0
CONT_ASSIGN	955	0	0
CONT_ASSIGN	957	0	0
CONT_ASSIGN	959	0	0
CONT_ASSIGN	961	0	0
CONT_ASSIGN	963	0	0
CONT_ASSIGN	965	0	0
CONT_ASSIGN	967	0	0
CONT_ASSIGN	969	0	0
CONT_ASSIGN	971	0	0
CONT_ASSIGN	973	0	0
CONT_ASSIGN	975	0	0
CONT_ASSIGN	977	0	0
CONT_ASSIGN	979	0	0
CONT_ASSIGN	981	0	0
CONT_ASSIGN	983	0	0
CONT_ASSIGN	985	0	0
CONT_ASSIGN	987	0	0
CONT_ASSIGN	989	0	0
CONT_ASSIGN	991	0	0
CONT_ASSIGN	993	0	0
CONT_ASSIGN	995	0	0
CONT_ASSIGN	997	0	0
CONT_ASSIGN	999	0	0
CONT_ASSIGN	1001	0	0
CONT_ASSIGN	1003	0	0
CONT_ASSIGN	1005	0	0
CONT_ASSIGN	1007	0	0
CONT_ASSIGN	2631	1	1	100.00
CONT_ASSIGN	3031	1	1	100.00
CONT_ASSIGN	3032	1	1	100.00
CONT_ASSIGN	3033	1	1	100.00
CONT_ASSIGN	3034	1	1	100.00
CONT_ASSIGN	3035	1	1	100.00
CONT_ASSIGN	3036	1	1	100.00
CONT_ASSIGN	3037	1	1	100.00
CONT_ASSIGN	3038	1	1	100.00
CONT_ASSIGN	3039	1	1	100.00
CONT_ASSIGN	3040	1	1	100.00
CONT_ASSIGN	3041	1	1	100.00
CONT_ASSIGN	3042	1	1	100.00
CONT_ASSIGN	3043	1	1	100.00
CONT_ASSIGN	3044	1	1	100.00
CONT_ASSIGN	3045	1	1	100.00
CONT_ASSIGN	3046	1	1	100.00
CONT_ASSIGN	3047	1	1	100.00
CONT_ASSIGN	3048	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3051	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3053	1	1	100.00
CONT_ASSIGN	3054	1	1	100.00
CONT_ASSIGN	3055	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3057	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3059	1	1	100.00
CONT_ASSIGN	3060	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
CONT_ASSIGN	3062	1	1	100.00
CONT_ASSIGN	3063	1	1	100.00
CONT_ASSIGN	3064	1	1	100.00
CONT_ASSIGN	3065	1	1	100.00
CONT_ASSIGN	3066	1	1	100.00
CONT_ASSIGN	3067	1	1	100.00
CONT_ASSIGN	3068	1	1	100.00
CONT_ASSIGN	3069	1	1	100.00
CONT_ASSIGN	3070	1	1	100.00
CONT_ASSIGN	3071	1	1	100.00
CONT_ASSIGN	3072	1	1	100.00
CONT_ASSIGN	3073	1	1	100.00
CONT_ASSIGN	3074	1	1	100.00
CONT_ASSIGN	3075	1	1	100.00
CONT_ASSIGN	3076	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3078	1	1	100.00
CONT_ASSIGN	3079	1	1	100.00
CONT_ASSIGN	3080	1	1	100.00
CONT_ASSIGN	3081	1	1	100.00
CONT_ASSIGN	3082	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3084	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3090	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3092	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3096	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3098	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3100	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3103	1	1	100.00
CONT_ASSIGN	3104	1	1	100.00
CONT_ASSIGN	3105	1	1	100.00
CONT_ASSIGN	3106	1	1	100.00
CONT_ASSIGN	3107	1	1	100.00
CONT_ASSIGN	3108	1	1	100.00
CONT_ASSIGN	3109	1	1	100.00
CONT_ASSIGN	3110	1	1	100.00
CONT_ASSIGN	3111	1	1	100.00
CONT_ASSIGN	3112	1	1	100.00
CONT_ASSIGN	3113	1	1	100.00
CONT_ASSIGN	3114	1	1	100.00
CONT_ASSIGN	3115	1	1	100.00
CONT_ASSIGN	3116	1	1	100.00
CONT_ASSIGN	3117	1	1	100.00
CONT_ASSIGN	3118	1	1	100.00
CONT_ASSIGN	3119	1	1	100.00
CONT_ASSIGN	3120	1	1	100.00
CONT_ASSIGN	3121	1	1	100.00
CONT_ASSIGN	3122	0	0
CONT_ASSIGN	3123	0	0
CONT_ASSIGN	3124	0	0
CONT_ASSIGN	3125	0	0
CONT_ASSIGN	3126	0	0
CONT_ASSIGN	3127	0	0
CONT_ASSIGN	3128	1	0	0.00
CONT_ASSIGN	3129	1	0	0.00
CONT_ASSIGN	3130	1	0	0.00
CONT_ASSIGN	3131	1	0	0.00
CONT_ASSIGN	3132	1	1	100.00
CONT_ASSIGN	3133	1	1	100.00
CONT_ASSIGN	3134	1	1	100.00
CONT_ASSIGN	3135	1	1	100.00
CONT_ASSIGN	3136	1	1	100.00
CONT_ASSIGN	3137	1	1	100.00
CONT_ASSIGN	3138	1	1	100.00
CONT_ASSIGN	3139	1	1	100.00
CONT_ASSIGN	3140	1	0	0.00
CONT_ASSIGN	3141	1	0	0.00
CONT_ASSIGN	3142	1	0	0.00
CONT_ASSIGN	3143	0	0
CONT_ASSIGN	3144	0	0
CONT_ASSIGN	3145	0	0
CONT_ASSIGN	3146	0	0
CONT_ASSIGN	3147	0	0
CONT_ASSIGN	3148	0	0
CONT_ASSIGN	3149	0	0
CONT_ASSIGN	3150	0	0
CONT_ASSIGN	3151	0	0
CONT_ASSIGN	3152	1	1	100.00
CONT_ASSIGN	3153	1	1	100.00
CONT_ASSIGN	3154	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3157	1	1	100.00
CONT_ASSIGN	3158	1	0	0.00
CONT_ASSIGN	3159	1	1	100.00
CONT_ASSIGN	3160	1	1	100.00
CONT_ASSIGN	3161	1	1	100.00
CONT_ASSIGN	3162	1	1	100.00
CONT_ASSIGN	3163	1	1	100.00
CONT_ASSIGN	3164	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3168	1	1	100.00
CONT_ASSIGN	3169	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3172	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3175	1	1	100.00
CONT_ASSIGN	3176	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3178	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3181	1	1	100.00
CONT_ASSIGN	3182	1	1	100.00
CONT_ASSIGN	3183	1	1	100.00
CONT_ASSIGN	3184	1	1	100.00
CONT_ASSIGN	3185	1	1	100.00
CONT_ASSIGN	3186	1	1	100.00
CONT_ASSIGN	3187	1	1	100.00
CONT_ASSIGN	3188	1	1	100.00
CONT_ASSIGN	3189	1	1	100.00
CONT_ASSIGN	3190	1	1	100.00
CONT_ASSIGN	3191	1	1	100.00
CONT_ASSIGN	3192	1	1	100.00
CONT_ASSIGN	3193	1	1	100.00
CONT_ASSIGN	3194	1	1	100.00
CONT_ASSIGN	3195	1	1	100.00
CONT_ASSIGN	3196	1	1	100.00
CONT_ASSIGN	3197	1	1	100.00
CONT_ASSIGN	3198	1	1	100.00
CONT_ASSIGN	3199	1	1	100.00
CONT_ASSIGN	3200	1	1	100.00
CONT_ASSIGN	3201	1	1	100.00
CONT_ASSIGN	3202	1	1	100.00
CONT_ASSIGN	3203	1	1	100.00
CONT_ASSIGN	3204	1	1	100.00
CONT_ASSIGN	3205	1	0	0.00
CONT_ASSIGN	3206	1	0	0.00
CONT_ASSIGN	3207	1	0	0.00
CONT_ASSIGN	3208	1	0	0.00
CONT_ASSIGN	3209	0	0
CONT_ASSIGN	3210	0	0
CONT_ASSIGN	3211	0	0
CONT_ASSIGN	3212	0	0
CONT_ASSIGN	3213	0	0
CONT_ASSIGN	3214	0	0
CONT_ASSIGN	3215	0	0
CONT_ASSIGN	3216	0	0
CONT_ASSIGN	3217	1	1	100.00
CONT_ASSIGN	3218	1	1	100.00
CONT_ASSIGN	3219	1	0	0.00
CONT_ASSIGN	3220	0	0
CONT_ASSIGN	3221	0	0
CONT_ASSIGN	3222	0	0
CONT_ASSIGN	3223	0	0
CONT_ASSIGN	3224	0	0
CONT_ASSIGN	3225	0	0
CONT_ASSIGN	3226	0	0
CONT_ASSIGN	3227	0	0
CONT_ASSIGN	3228	0	0
CONT_ASSIGN	3229	0	0
CONT_ASSIGN	3230	0	0
CONT_ASSIGN	3231	0	0
CONT_ASSIGN	3232	0	0
CONT_ASSIGN	3233	0	0
CONT_ASSIGN	3234	0	0
CONT_ASSIGN	3235	1	1	100.00
CONT_ASSIGN	3236	0	0
CONT_ASSIGN	3237	0	0
CONT_ASSIGN	3238	0	0
CONT_ASSIGN	3239	0	0
CONT_ASSIGN	3240	0	0
CONT_ASSIGN	3241	0	0
CONT_ASSIGN	3245	1	1	100.00
CONT_ASSIGN	3246	1	1	100.00
CONT_ASSIGN	3247	1	1	100.00
CONT_ASSIGN	3248	1	1	100.00
CONT_ASSIGN	3249	1	1	100.00
CONT_ASSIGN	3250	1	1	100.00
CONT_ASSIGN	3251	1	1	100.00
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3253	1	1	100.00
CONT_ASSIGN	3254	1	1	100.00
CONT_ASSIGN	3255	1	1	100.00
CONT_ASSIGN	3256	1	1	100.00
CONT_ASSIGN	3257	1	1	100.00
CONT_ASSIGN	3258	1	1	100.00
CONT_ASSIGN	3259	1	1	100.00
CONT_ASSIGN	3262	1	1	100.00
CONT_ASSIGN	3263	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3265	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3268	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3270	1	1	100.00
CONT_ASSIGN	3271	1	1	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3273	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3277	1	1	100.00
CONT_ASSIGN	3280	1	1	100.00
CONT_ASSIGN	3281	1	1	100.00
CONT_ASSIGN	3282	1	1	100.00
CONT_ASSIGN	3283	1	0	0.00
CONT_ASSIGN	3284	1	0	0.00
CONT_ASSIGN	3285	1	0	0.00
CONT_ASSIGN	3286	1	1	100.00
CONT_ASSIGN	3287	1	1	100.00
CONT_ASSIGN	3288	1	1	100.00
CONT_ASSIGN	3289	1	1	100.00
CONT_ASSIGN	3290	0	0
CONT_ASSIGN	3291	0	0
CONT_ASSIGN	3294	1	1	100.00
CONT_ASSIGN	3295	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
747	1	1
748	1	1
749	1	1
750	0	1
751	0	1
752	0	1
753	0	1
754	0	1
767	1	1
768	0	1
769	0	1
770	0	1
771	0	1
772	0	1
773	0	1
774	0	1
788	1	1
790	1	1
792	1	1
794	1	1
796	1	1
800	1	1
810	1	1
811	1	1
815	1	1
839	1	1
840	1	1
842	1	1
843	1	1
845	1	1
846	1	1
848	1	1
849	1	1
851	1	1
852	1	1
854	1	1
855	1	1
857	1	1
858	1	1
860	1	1
861	1	1
863	1	1
864	1	1
866	1	1
867	1	1
869	0	1
870	1	1
872	0	1
873	1	1
875	1	1
876	1	1
878	1	1
879	1	1
881	1	1
882	1	1
884	1	1
885	1	1
887	1	1
888	1	1
890	1	1
891	1	1
893	1	1
894	1	1
896	1	1
897	1	1
899	1	1
900	1	1
902	1	1
903	1	1
905	1	1
906	1	1
908	1	1
909	1	1
915		unreachable
917		unreachable
919		unreachable
921		unreachable
923		unreachable
925		unreachable
927		unreachable
929		unreachable
931		unreachable
933		unreachable
935		unreachable
937		unreachable
939		unreachable
941		unreachable
943		unreachable
945		unreachable
947		unreachable
949		unreachable
951		unreachable
953		unreachable
955		unreachable
957		unreachable
959		unreachable
961		unreachable
963		unreachable
965		unreachable
967		unreachable
969		unreachable
971		unreachable
973		unreachable
975		unreachable
977		unreachable
979		unreachable
981		unreachable
983		unreachable
985		unreachable
987		unreachable
989		unreachable
991		unreachable
993		unreachable
995		unreachable
997		unreachable
999		unreachable
1001		unreachable
1003		unreachable
1005		unreachable
1007		unreachable
2631	1	1
3031	1	1
3032	1	1
3033	1	1
3034	1	1
3035	1	1
3036	1	1
3037	1	1
3038	1	1
3039	1	1
3040	1	1
3041	1	1
3042	1	1
3043	1	1
3044	1	1
3045	1	1
3046	1	1
3047	1	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3100	1	1
3101	1	1
3102	1	1
3103	1	1
3104	1	1
3105	1	1
3106	1	1
3107	1	1
3108	1	1
3109	1	1
3110	1	1
3111	1	1
3112	1	1
3113	1	1
3114	1	1
3115	1	1
3116	1	1
3117	1	1
3118	1	1
3119	1	1
3120	1	1
3121	1	1
3122		unreachable
3123		unreachable
3124		unreachable
3125		unreachable
3126		unreachable
3127		unreachable
3128	0	1
3129	0	1
3130	0	1
3131	0	1
3132	1	1
3133	1	1
3134	1	1
3135	1	1
3136	1	1
3137	1	1
3138	1	1
3139	1	1
3140	0	1
3141	0	1
3142	0	1
3143		unreachable
3144		unreachable
3145		unreachable
3146		unreachable
3147		unreachable
3148		unreachable
3149		unreachable
3150		unreachable
3151		unreachable
3152	1	1
3153	1	1
3154	1	1
3155	1	1
3156	1	1
3157	1	1
3158	0	1
3159	1	1
3160	1	1
3161	1	1
3162	1	1
3163	1	1
3164	1	1
3167	1	1
3168	1	1
3169	1	1
3170	1	1
3171	1	1
3172	1	1
3173	1	1
3174	1	1
3175	1	1
3176	1	1
3177	1	1
3178	1	1
3179	1	1
3180	1	1
3181	1	1
3182	1	1
3183	1	1
3184	1	1
3185	1	1
3186	1	1
3187	1	1
3188	1	1
3189	1	1
3190	1	1
3191	1	1
3192	1	1
3193	1	1
3194	1	1
3195	1	1
3196	1	1
3197	1	1
3198	1	1
3199	1	1
3200	1	1
3201	1	1
3202	1	1
3203	1	1
3204	1	1
3205	0	1
3206	0	1
3207	0	1
3208	0	1
3209		unreachable
3210		unreachable
3211		unreachable
3212		unreachable
3213		unreachable
3214		unreachable
3215		unreachable
3216		unreachable
3217	1	1
3218	1	1
3219	0	1
3220		unreachable
3221		unreachable
3222		unreachable
3223		unreachable
3224		unreachable
3225		unreachable
3226		unreachable
3227		unreachable
3228		unreachable
3229		unreachable
3230		unreachable
3231		unreachable
3232		unreachable
3233		unreachable
3234		unreachable
3235	1	1
3236		unreachable
3237		unreachable
3238		unreachable
3239		unreachable
3240		unreachable
3241		unreachable
3245	1	1
3246	1	1
3247	1	1
3248	1	1
3249	1	1
3250	1	1
3251	1	1
3252	1	1
3253	1	1
3254	1	1
3255	1	1
3256	1	1
3257	1	1
3258	1	1
3259	1	1
3262	1	1
3263	1	1
3264	1	1
3265	1	1
3266	1	1
3267	1	1
3268	1	1
3269	1	1
3270	1	1
3271	1	1
3272	1	1
3273	1	1
3276	1	1
3277	1	1
3280	1	1
3281	1	1
3282	1	1
3283	0	1
3284	0	1
3285	0	1
3286	1	1
3287	1	1
3288	1	1
3289	1	1
3290		unreachable
3291		unreachable
3294	1	1
3295	1	1

---

Toggle Coverage for Module : top_earlgrey

	Total	Covered	Percent
Totals	788	425	53.93
Total Bits	2938	1757	59.80
Total Bits 0->1	1469	882	60.04
Total Bits 1->0	1469	875	59.56

Ports	788	425	53.93
Port Bits	2938	1757	59.80
Port Bits 0->1	1469	882	60.04
Port Bits 1->0	1469	875	59.56

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
mio_in_i[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
mio_out_o[46:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T7	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T28,T29,T30	Yes	T25,T26,T7	OUTPUT
dio_in_i[15:0]	Yes	Yes	T16,T18,T23	Yes	T16,T18,T23	INPUT
dio_out_o[11:0]	Yes	Yes	*T16,*T17,*T18	Yes	T17,T18,T19	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T18,T23,T24	Yes	T18,T23,T7	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].keep_en	No	No		No		OUTPUT
mio_attr_o[0].schmitt_en	No	No		No		OUTPUT
mio_attr_o[0].od_en	No	No		No		OUTPUT
mio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[1].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].keep_en	No	No		No		OUTPUT
mio_attr_o[1].schmitt_en	No	No		No		OUTPUT
mio_attr_o[1].od_en	No	No		No		OUTPUT
mio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[2].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[2].keep_en	No	No		No		OUTPUT
mio_attr_o[2].schmitt_en	No	No		No		OUTPUT
mio_attr_o[2].od_en	No	No		No		OUTPUT
mio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[3].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].keep_en	No	No		No		OUTPUT
mio_attr_o[3].schmitt_en	No	No		No		OUTPUT
mio_attr_o[3].od_en	No	No		No		OUTPUT
mio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[4].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].keep_en	No	No		No		OUTPUT
mio_attr_o[4].schmitt_en	No	No		No		OUTPUT
mio_attr_o[4].od_en	No	No		No		OUTPUT
mio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[5].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].keep_en	No	No		No		OUTPUT
mio_attr_o[5].schmitt_en	No	No		No		OUTPUT
mio_attr_o[5].od_en	No	No		No		OUTPUT
mio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[6].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].keep_en	No	No		No		OUTPUT
mio_attr_o[6].schmitt_en	No	No		No		OUTPUT
mio_attr_o[6].od_en	No	No		No		OUTPUT
mio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[7].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T31,T32,T33	Yes	T38,T39,T40	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T31,T32,T33	Yes	T38,T39,T40	OUTPUT
mio_attr_o[7].keep_en	No	No		No		OUTPUT
mio_attr_o[7].schmitt_en	No	No		No		OUTPUT
mio_attr_o[7].od_en	No	No		No		OUTPUT
mio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[8].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].keep_en	No	No		No		OUTPUT
mio_attr_o[8].schmitt_en	No	No		No		OUTPUT
mio_attr_o[8].od_en	No	No		No		OUTPUT
mio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[9].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[9].keep_en	No	No		No		OUTPUT
mio_attr_o[9].schmitt_en	No	No		No		OUTPUT
mio_attr_o[9].od_en	No	No		No		OUTPUT
mio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[10].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[10].keep_en	No	No		No		OUTPUT
mio_attr_o[10].schmitt_en	No	No		No		OUTPUT
mio_attr_o[10].od_en	No	No		No		OUTPUT
mio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[11].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].keep_en	No	No		No		OUTPUT
mio_attr_o[11].schmitt_en	No	No		No		OUTPUT
mio_attr_o[11].od_en	No	No		No		OUTPUT
mio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[12].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[12].keep_en	No	No		No		OUTPUT
mio_attr_o[12].schmitt_en	No	No		No		OUTPUT
mio_attr_o[12].od_en	No	No		No		OUTPUT
mio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[12].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[13].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[13].keep_en	No	No		No		OUTPUT
mio_attr_o[13].schmitt_en	No	No		No		OUTPUT
mio_attr_o[13].od_en	No	No		No		OUTPUT
mio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[13].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[14].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[14].keep_en	No	No		No		OUTPUT
mio_attr_o[14].schmitt_en	No	No		No		OUTPUT
mio_attr_o[14].od_en	No	No		No		OUTPUT
mio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[15].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[15].keep_en	No	No		No		OUTPUT
mio_attr_o[15].schmitt_en	No	No		No		OUTPUT
mio_attr_o[15].od_en	No	No		No		OUTPUT
mio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[16].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].keep_en	No	No		No		OUTPUT
mio_attr_o[16].schmitt_en	No	No		No		OUTPUT
mio_attr_o[16].od_en	No	No		No		OUTPUT
mio_attr_o[16].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[17].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].keep_en	No	No		No		OUTPUT
mio_attr_o[17].schmitt_en	No	No		No		OUTPUT
mio_attr_o[17].od_en	No	No		No		OUTPUT
mio_attr_o[17].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[18].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].keep_en	No	No		No		OUTPUT
mio_attr_o[18].schmitt_en	No	No		No		OUTPUT
mio_attr_o[18].od_en	No	No		No		OUTPUT
mio_attr_o[18].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[19].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].keep_en	No	No		No		OUTPUT
mio_attr_o[19].schmitt_en	No	No		No		OUTPUT
mio_attr_o[19].od_en	No	No		No		OUTPUT
mio_attr_o[19].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[20].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].keep_en	No	No		No		OUTPUT
mio_attr_o[20].schmitt_en	No	No		No		OUTPUT
mio_attr_o[20].od_en	No	No		No		OUTPUT
mio_attr_o[20].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[21].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].keep_en	No	No		No		OUTPUT
mio_attr_o[21].schmitt_en	No	No		No		OUTPUT
mio_attr_o[21].od_en	No	No		No		OUTPUT
mio_attr_o[21].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[22].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T41,T42,T43	Yes	T41,T44,T42	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T41,T42,T45	Yes	T41,T42,T45	OUTPUT
mio_attr_o[22].keep_en	No	No		No		OUTPUT
mio_attr_o[22].schmitt_en	No	No		No		OUTPUT
mio_attr_o[22].od_en	No	No		No		OUTPUT
mio_attr_o[22].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[22].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[23].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T41,T42,T43	Yes	T41,T44,T42	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].keep_en	No	No		No		OUTPUT
mio_attr_o[23].schmitt_en	No	No		No		OUTPUT
mio_attr_o[23].od_en	No	No		No		OUTPUT
mio_attr_o[23].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[24].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T41,T42,T43	Yes	T41,T44,T42	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].keep_en	No	No		No		OUTPUT
mio_attr_o[24].schmitt_en	No	No		No		OUTPUT
mio_attr_o[24].od_en	No	No		No		OUTPUT
mio_attr_o[24].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[25].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T34,T5,T6	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T34,T5,T6	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].keep_en	No	No		No		OUTPUT
mio_attr_o[25].schmitt_en	No	No		No		OUTPUT
mio_attr_o[25].od_en	No	No		No		OUTPUT
mio_attr_o[25].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[25].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[26].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].keep_en	No	No		No		OUTPUT
mio_attr_o[26].schmitt_en	No	No		No		OUTPUT
mio_attr_o[26].od_en	No	No		No		OUTPUT
mio_attr_o[26].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[27].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].keep_en	No	No		No		OUTPUT
mio_attr_o[27].schmitt_en	No	No		No		OUTPUT
mio_attr_o[27].od_en	No	No		No		OUTPUT
mio_attr_o[27].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[28].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].keep_en	No	No		No		OUTPUT
mio_attr_o[28].schmitt_en	No	No		No		OUTPUT
mio_attr_o[28].od_en	No	No		No		OUTPUT
mio_attr_o[28].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[29].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].keep_en	No	No		No		OUTPUT
mio_attr_o[29].schmitt_en	No	No		No		OUTPUT
mio_attr_o[29].od_en	No	No		No		OUTPUT
mio_attr_o[29].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[30].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].keep_en	No	No		No		OUTPUT
mio_attr_o[30].schmitt_en	No	No		No		OUTPUT
mio_attr_o[30].od_en	No	No		No		OUTPUT
mio_attr_o[30].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[31].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].keep_en	No	No		No		OUTPUT
mio_attr_o[31].schmitt_en	No	No		No		OUTPUT
mio_attr_o[31].od_en	No	No		No		OUTPUT
mio_attr_o[31].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[32].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].keep_en	No	No		No		OUTPUT
mio_attr_o[32].schmitt_en	No	No		No		OUTPUT
mio_attr_o[32].od_en	No	No		No		OUTPUT
mio_attr_o[32].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[33].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].keep_en	No	No		No		OUTPUT
mio_attr_o[33].schmitt_en	No	No		No		OUTPUT
mio_attr_o[33].od_en	No	No		No		OUTPUT
mio_attr_o[33].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[34].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].keep_en	No	No		No		OUTPUT
mio_attr_o[34].schmitt_en	No	No		No		OUTPUT
mio_attr_o[34].od_en	No	No		No		OUTPUT
mio_attr_o[34].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[35].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].keep_en	No	No		No		OUTPUT
mio_attr_o[35].schmitt_en	No	No		No		OUTPUT
mio_attr_o[35].od_en	No	No		No		OUTPUT
mio_attr_o[35].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[36].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].keep_en	No	No		No		OUTPUT
mio_attr_o[36].schmitt_en	No	No		No		OUTPUT
mio_attr_o[36].od_en	No	No		No		OUTPUT
mio_attr_o[36].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[37].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].keep_en	No	No		No		OUTPUT
mio_attr_o[37].schmitt_en	No	No		No		OUTPUT
mio_attr_o[37].od_en	No	No		No		OUTPUT
mio_attr_o[37].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[38].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].keep_en	No	No		No		OUTPUT
mio_attr_o[38].schmitt_en	No	No		No		OUTPUT
mio_attr_o[38].od_en	No	No		No		OUTPUT
mio_attr_o[38].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[39].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].keep_en	No	No		No		OUTPUT
mio_attr_o[39].schmitt_en	No	No		No		OUTPUT
mio_attr_o[39].od_en	No	No		No		OUTPUT
mio_attr_o[39].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[40].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].keep_en	No	No		No		OUTPUT
mio_attr_o[40].schmitt_en	No	No		No		OUTPUT
mio_attr_o[40].od_en	No	No		No		OUTPUT
mio_attr_o[40].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[41].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].keep_en	No	No		No		OUTPUT
mio_attr_o[41].schmitt_en	No	No		No		OUTPUT
mio_attr_o[41].od_en	No	No		No		OUTPUT
mio_attr_o[41].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[42].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].keep_en	No	No		No		OUTPUT
mio_attr_o[42].schmitt_en	No	No		No		OUTPUT
mio_attr_o[42].od_en	No	No		No		OUTPUT
mio_attr_o[42].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[43].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].keep_en	No	No		No		OUTPUT
mio_attr_o[43].schmitt_en	No	No		No		OUTPUT
mio_attr_o[43].od_en	No	No		No		OUTPUT
mio_attr_o[43].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[44].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].keep_en	No	No		No		OUTPUT
mio_attr_o[44].schmitt_en	No	No		No		OUTPUT
mio_attr_o[44].od_en	No	No		No		OUTPUT
mio_attr_o[44].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[45].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].keep_en	No	No		No		OUTPUT
mio_attr_o[45].schmitt_en	No	No		No		OUTPUT
mio_attr_o[45].od_en	No	No		No		OUTPUT
mio_attr_o[45].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].drive_strength[3:1]	No	No		No		OUTPUT
mio_attr_o[46].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].keep_en	No	No		No		OUTPUT
mio_attr_o[46].schmitt_en	No	No		No		OUTPUT
mio_attr_o[46].od_en	No	No		No		OUTPUT
mio_attr_o[46].slew_rate[1:0]	No	No		No		OUTPUT
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[0].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T34,*T5,*T6	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[1].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].keep_en	No	No		No		OUTPUT
dio_attr_o[1].schmitt_en	No	No		No		OUTPUT
dio_attr_o[1].od_en	No	No		No		OUTPUT
dio_attr_o[1].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T34,*T5,*T6	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[2].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[2].keep_en	No	No		No		OUTPUT
dio_attr_o[2].schmitt_en	No	No		No		OUTPUT
dio_attr_o[2].od_en	No	No		No		OUTPUT
dio_attr_o[2].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[2].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[3].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[3].keep_en	No	No		No		OUTPUT
dio_attr_o[3].schmitt_en	No	No		No		OUTPUT
dio_attr_o[3].od_en	No	No		No		OUTPUT
dio_attr_o[3].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[3].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[4].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[4].keep_en	No	No		No		OUTPUT
dio_attr_o[4].schmitt_en	No	No		No		OUTPUT
dio_attr_o[4].od_en	No	No		No		OUTPUT
dio_attr_o[4].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[4].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[5].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[5].keep_en	No	No		No		OUTPUT
dio_attr_o[5].schmitt_en	No	No		No		OUTPUT
dio_attr_o[5].od_en	No	No		No		OUTPUT
dio_attr_o[5].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T32,*T33,*T35	Yes	T32,T33,T35	OUTPUT
dio_attr_o[5].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[6].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].keep_en	No	No		No		OUTPUT
dio_attr_o[6].schmitt_en	No	No		No		OUTPUT
dio_attr_o[6].od_en	No	No		No		OUTPUT
dio_attr_o[6].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[7].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].keep_en	No	No		No		OUTPUT
dio_attr_o[7].schmitt_en	No	No		No		OUTPUT
dio_attr_o[7].od_en	No	No		No		OUTPUT
dio_attr_o[7].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[8].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].keep_en	No	No		No		OUTPUT
dio_attr_o[8].schmitt_en	No	No		No		OUTPUT
dio_attr_o[8].od_en	No	No		No		OUTPUT
dio_attr_o[8].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[9].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].keep_en	No	No		No		OUTPUT
dio_attr_o[9].schmitt_en	No	No		No		OUTPUT
dio_attr_o[9].od_en	No	No		No		OUTPUT
dio_attr_o[9].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[10].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].keep_en	No	No		No		OUTPUT
dio_attr_o[10].schmitt_en	No	No		No		OUTPUT
dio_attr_o[10].od_en	No	No		No		OUTPUT
dio_attr_o[10].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[11].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].keep_en	No	No		No		OUTPUT
dio_attr_o[11].schmitt_en	No	No		No		OUTPUT
dio_attr_o[11].od_en	No	No		No		OUTPUT
dio_attr_o[11].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[12].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[12].virt_od_en	No	No		No		OUTPUT
dio_attr_o[12].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[12].keep_en	No	No		No		OUTPUT
dio_attr_o[12].schmitt_en	No	No		No		OUTPUT
dio_attr_o[12].od_en	No	No		No		OUTPUT
dio_attr_o[12].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[13].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[13].virt_od_en	No	No		No		OUTPUT
dio_attr_o[13].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[13].keep_en	No	No		No		OUTPUT
dio_attr_o[13].schmitt_en	No	No		No		OUTPUT
dio_attr_o[13].od_en	No	No		No		OUTPUT
dio_attr_o[13].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:0]	No	No		No		OUTPUT
dio_attr_o[14].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[14].keep_en	No	No		No		OUTPUT
dio_attr_o[14].schmitt_en	No	No		No		OUTPUT
dio_attr_o[14].od_en	No	No		No		OUTPUT
dio_attr_o[14].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[14].drive_strength[3:1]	No	No		No		OUTPUT
dio_attr_o[15].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[15].keep_en	No	No		No		OUTPUT
dio_attr_o[15].schmitt_en	No	No		No		OUTPUT
dio_attr_o[15].od_en	No	No		No		OUTPUT
dio_attr_o[15].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[15].drive_strength[3:1]	No	No		No		OUTPUT
adc_req_o.pd	Yes	Yes	T119,T19,T138	Yes	T119,T19,T138	OUTPUT
adc_req_o.channel_sel[1:0]	Yes	Yes	T119,T19,T138	Yes	T119,T19,T138	OUTPUT
adc_rsp_i.data_valid	Yes	Yes	T119,T19,T138	Yes	T119,T19,T138	INPUT
adc_rsp_i.data[9:0]	Yes	Yes	T119,T19,T139	Yes	T119,T19,T139	INPUT
ast_edn_req_i.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_edn_rsp_o.edn_bus[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
ast_edn_rsp_o.edn_fips	Yes	Yes	T140,T141	Yes	T101,T142,T143	OUTPUT
ast_edn_rsp_o.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_lc_dft_en_o[3:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
obs_ctrl_i.obmen[3:0]	No	No		No		INPUT
obs_ctrl_i.obmsl[3:0]	No	No		No		INPUT
obs_ctrl_i.obgsl[3:0]	No	No		No		INPUT
ram_1p_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
ram_1p_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
ram_1p_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
ram_1p_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
rom_cfg_i.cfg[3:0]	No	No		No		INPUT
rom_cfg_i.cfg_en	No	No		No		INPUT
clk_main_jitter_en_o[3:0]	Yes	Yes	T144,T145,T99	Yes	T146,T147,T148	OUTPUT
io_clk_byp_req_o[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T58	OUTPUT
io_clk_byp_ack_i[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T58	INPUT
all_clk_byp_req_o[3:0]	Yes	Yes	T149,T150,T151	Yes	T149,T150,T151	OUTPUT
all_clk_byp_ack_i[3:0]	Yes	Yes	T149,T150,T151	Yes	T149,T150,T151	INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
div_step_down_req_i[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T58	INPUT
calib_rdy_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	Yes	Yes	T1,T2,T3	Yes	T5,T118,T119	INPUT
flash_power_ready_h_i	No	No		Yes	T1,T2,T3	INPUT
flash_test_mode_a_io[1:0]	No	No		Yes	T7,T8,T9	INOUT
flash_test_voltage_h_io	No	No		Yes	T7,T8,T9	INOUT
flash_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
es_rng_req_o.rng_enable	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	OUTPUT
es_rng_rsp_i.rng_b[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
es_rng_rsp_i.rng_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
es_rng_fips_o	Yes	Yes	T152,T153,T154	Yes	T34,T79,T108	OUTPUT
ast_tl_req_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	OUTPUT
ast_tl_req_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
ast_tl_req_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
ast_tl_req_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_rsp_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_error	Yes	Yes	T72,T75,T105	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_user.data_intg[6:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_data[31:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_source[5:0]	Yes	Yes	T72,*T73,T75	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_opcode[0]	Yes	Yes	*T72,*T74,*T75	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dft_strap_test_o.straps[1:0]	No	No		Yes	T63,T64,T65	OUTPUT
dft_strap_test_o.valid	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
usb_dp_pullup_en_o	Yes	Yes	T18,T19,T23	Yes	T17,T18,T19	OUTPUT
usb_dn_pullup_en_o	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
pwrmgr_ast_req_o.usb_clk_en	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.io_clk_en	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.core_clk_en	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.slow_clk_en	No	No		No		OUTPUT
pwrmgr_ast_req_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwrmgr_ast_req_o.main_pd_n	Yes	Yes	T5,T118,T119	Yes	T5,T118,T119	OUTPUT
pwrmgr_ast_rsp_i.main_pok	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.usb_clk_val	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.io_clk_val	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.core_clk_val	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.slow_clk_val	Yes	Yes	T149,T150,T151	Yes	T1,T2,T3	INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0]	No	No		No		INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1]	Yes	Yes	T1,T2,T3	Yes	T5,T118,T119	INPUT
otp_ext_voltage_h_io	No	No		Yes	T7,T8,T9	INOUT
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
por_n_i[1:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p	Yes	Yes	T155,T161,T162	Yes	T155,T161,T162	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0]	Yes	Yes	T80,T163,T164	Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
sck_monitor_o	Yes	Yes	T106,T11,T12	Yes	T106,T11,T12	OUTPUT
usbdev_usb_rx_d_i	Yes	Yes	T18,T23,T69	Yes	T18,T23,T69	INPUT
usbdev_usb_tx_d_o	Yes	Yes	T16,T17,T18	Yes	T17,T18,T19	OUTPUT
usbdev_usb_tx_se0_o	Yes	Yes	T18,T23,T24	Yes	T18,T23,T24	OUTPUT
usbdev_usb_tx_use_d_se0_o	Yes	Yes	T165,T166,T167	Yes	T165,T166,T167	OUTPUT
usbdev_usb_rx_enable_o	Yes	Yes	T71,T165,T166	Yes	T18,T23,T69	OUTPUT
usbdev_usb_ref_val_o	Yes	Yes	T18,T23,T168	Yes	T18,T23,T24	OUTPUT
usbdev_usb_ref_pulse_o	Yes	Yes	T18,T23,T24	Yes	T18,T23,T24	OUTPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clks_ast_o.clk_usb_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_otbn	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_kmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_hmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_aes	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c2_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c2_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c1_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c0_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_aon_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_aon_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host1_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host0_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_device_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_device_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0]	Yes	Yes	*T34,*T4,*T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[0]	Yes	Yes	*T34,*T4,*T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_lc_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div4_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div2_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div2_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_aon_n[1:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Module : top_earlgrey

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
scanmodeKnown	428003793	428003793	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	428003793	428003793	0	0
T1	143836	143836	0	0
T2	77136	77136	0	0
T3	354243	354243	0	0
T4	54458	54458	0	0
T5	327190	327190	0	0
T6	337980	337980	0	0
T13	363854	363854	0	0
T34	141940	141940	0	0
T79	693376	693376	0	0
T80	100678	100678	0	0

Line Coverage for Instance : tb.dut.top_earlgrey

	Line No.	Total	Covered	Percent
TOTAL		278	248	89.21
CONT_ASSIGN	747	1	1	100.00
CONT_ASSIGN	748	1	1	100.00
CONT_ASSIGN	749	1	1	100.00
CONT_ASSIGN	750	1	0	0.00
CONT_ASSIGN	751	1	0	0.00
CONT_ASSIGN	752	1	0	0.00
CONT_ASSIGN	753	1	0	0.00
CONT_ASSIGN	754	1	0	0.00
CONT_ASSIGN	767	1	1	100.00
CONT_ASSIGN	768	1	0	0.00
CONT_ASSIGN	769	1	0	0.00
CONT_ASSIGN	770	1	0	0.00
CONT_ASSIGN	771	1	0	0.00
CONT_ASSIGN	772	1	0	0.00
CONT_ASSIGN	773	1	0	0.00
CONT_ASSIGN	774	1	0	0.00
CONT_ASSIGN	788	1	1	100.00
CONT_ASSIGN	790	1	1	100.00
CONT_ASSIGN	792	1	1	100.00
CONT_ASSIGN	794	1	1	100.00
CONT_ASSIGN	796	1	1	100.00
CONT_ASSIGN	800	1	1	100.00
CONT_ASSIGN	810	1	1	100.00
CONT_ASSIGN	811	1	1	100.00
CONT_ASSIGN	815	1	1	100.00
CONT_ASSIGN	839	1	1	100.00
CONT_ASSIGN	840	1	1	100.00
CONT_ASSIGN	842	1	1	100.00
CONT_ASSIGN	843	1	1	100.00
CONT_ASSIGN	845	1	1	100.00
CONT_ASSIGN	846	1	1	100.00
CONT_ASSIGN	848	1	1	100.00
CONT_ASSIGN	849	1	1	100.00
CONT_ASSIGN	851	1	1	100.00
CONT_ASSIGN	852	1	1	100.00
CONT_ASSIGN	854	1	1	100.00
CONT_ASSIGN	855	1	1	100.00
CONT_ASSIGN	857	1	1	100.00
CONT_ASSIGN	858	1	1	100.00
CONT_ASSIGN	860	1	1	100.00
CONT_ASSIGN	861	1	1	100.00
CONT_ASSIGN	863	1	1	100.00
CONT_ASSIGN	864	1	1	100.00
CONT_ASSIGN	866	1	1	100.00
CONT_ASSIGN	867	1	1	100.00
CONT_ASSIGN	869	1	0	0.00
CONT_ASSIGN	870	1	1	100.00
CONT_ASSIGN	872	1	0	0.00
CONT_ASSIGN	873	1	1	100.00
CONT_ASSIGN	875	1	1	100.00
CONT_ASSIGN	876	1	1	100.00
CONT_ASSIGN	878	1	1	100.00
CONT_ASSIGN	879	1	1	100.00
CONT_ASSIGN	881	1	1	100.00
CONT_ASSIGN	882	1	1	100.00
CONT_ASSIGN	884	1	1	100.00
CONT_ASSIGN	885	1	1	100.00
CONT_ASSIGN	887	1	1	100.00
CONT_ASSIGN	888	1	1	100.00
CONT_ASSIGN	890	1	1	100.00
CONT_ASSIGN	891	1	1	100.00
CONT_ASSIGN	893	1	1	100.00
CONT_ASSIGN	894	1	1	100.00
CONT_ASSIGN	896	1	1	100.00
CONT_ASSIGN	897	1	1	100.00
CONT_ASSIGN	899	1	1	100.00
CONT_ASSIGN	900	1	1	100.00
CONT_ASSIGN	902	1	1	100.00
CONT_ASSIGN	903	1	1	100.00
CONT_ASSIGN	905	1	1	100.00
CONT_ASSIGN	906	1	1	100.00
CONT_ASSIGN	908	1	1	100.00
CONT_ASSIGN	909	1	1	100.00
CONT_ASSIGN	915	0	0
CONT_ASSIGN	917	0	0
CONT_ASSIGN	919	0	0
CONT_ASSIGN	921	0	0
CONT_ASSIGN	923	0	0
CONT_ASSIGN	925	0	0
CONT_ASSIGN	927	0	0
CONT_ASSIGN	929	0	0
CONT_ASSIGN	931	0	0
CONT_ASSIGN	933	0	0
CONT_ASSIGN	935	0	0
CONT_ASSIGN	937	0	0
CONT_ASSIGN	939	0	0
CONT_ASSIGN	941	0	0
CONT_ASSIGN	943	0	0
CONT_ASSIGN	945	0	0
CONT_ASSIGN	947	0	0
CONT_ASSIGN	949	0	0
CONT_ASSIGN	951	0	0
CONT_ASSIGN	953	0	0
CONT_ASSIGN	955	0	0
CONT_ASSIGN	957	0	0
CONT_ASSIGN	959	0	0
CONT_ASSIGN	961	0	0
CONT_ASSIGN	963	0	0
CONT_ASSIGN	965	0	0
CONT_ASSIGN	967	0	0
CONT_ASSIGN	969	0	0
CONT_ASSIGN	971	0	0
CONT_ASSIGN	973	0	0
CONT_ASSIGN	975	0	0
CONT_ASSIGN	977	0	0
CONT_ASSIGN	979	0	0
CONT_ASSIGN	981	0	0
CONT_ASSIGN	983	0	0
CONT_ASSIGN	985	0	0
CONT_ASSIGN	987	0	0
CONT_ASSIGN	989	0	0
CONT_ASSIGN	991	0	0
CONT_ASSIGN	993	0	0
CONT_ASSIGN	995	0	0
CONT_ASSIGN	997	0	0
CONT_ASSIGN	999	0	0
CONT_ASSIGN	1001	0	0
CONT_ASSIGN	1003	0	0
CONT_ASSIGN	1005	0	0
CONT_ASSIGN	1007	0	0
CONT_ASSIGN	2631	1	1	100.00
CONT_ASSIGN	3031	1	1	100.00
CONT_ASSIGN	3032	1	1	100.00
CONT_ASSIGN	3033	1	1	100.00
CONT_ASSIGN	3034	1	1	100.00
CONT_ASSIGN	3035	1	1	100.00
CONT_ASSIGN	3036	1	1	100.00
CONT_ASSIGN	3037	1	1	100.00
CONT_ASSIGN	3038	1	1	100.00
CONT_ASSIGN	3039	1	1	100.00
CONT_ASSIGN	3040	1	1	100.00
CONT_ASSIGN	3041	1	1	100.00
CONT_ASSIGN	3042	1	1	100.00
CONT_ASSIGN	3043	1	1	100.00
CONT_ASSIGN	3044	1	1	100.00
CONT_ASSIGN	3045	1	1	100.00
CONT_ASSIGN	3046	1	1	100.00
CONT_ASSIGN	3047	1	1	100.00
CONT_ASSIGN	3048	1	1	100.00
CONT_ASSIGN	3049	1	1	100.00
CONT_ASSIGN	3050	1	1	100.00
CONT_ASSIGN	3051	1	1	100.00
CONT_ASSIGN	3052	1	1	100.00
CONT_ASSIGN	3053	1	1	100.00
CONT_ASSIGN	3054	1	1	100.00
CONT_ASSIGN	3055	1	1	100.00
CONT_ASSIGN	3056	1	1	100.00
CONT_ASSIGN	3057	1	1	100.00
CONT_ASSIGN	3058	1	1	100.00
CONT_ASSIGN	3059	1	1	100.00
CONT_ASSIGN	3060	1	1	100.00
CONT_ASSIGN	3061	1	1	100.00
CONT_ASSIGN	3062	1	1	100.00
CONT_ASSIGN	3063	1	1	100.00
CONT_ASSIGN	3064	1	1	100.00
CONT_ASSIGN	3065	1	1	100.00
CONT_ASSIGN	3066	1	1	100.00
CONT_ASSIGN	3067	1	1	100.00
CONT_ASSIGN	3068	1	1	100.00
CONT_ASSIGN	3069	1	1	100.00
CONT_ASSIGN	3070	1	1	100.00
CONT_ASSIGN	3071	1	1	100.00
CONT_ASSIGN	3072	1	1	100.00
CONT_ASSIGN	3073	1	1	100.00
CONT_ASSIGN	3074	1	1	100.00
CONT_ASSIGN	3075	1	1	100.00
CONT_ASSIGN	3076	1	1	100.00
CONT_ASSIGN	3077	1	1	100.00
CONT_ASSIGN	3078	1	1	100.00
CONT_ASSIGN	3079	1	1	100.00
CONT_ASSIGN	3080	1	1	100.00
CONT_ASSIGN	3081	1	1	100.00
CONT_ASSIGN	3082	1	1	100.00
CONT_ASSIGN	3083	1	1	100.00
CONT_ASSIGN	3084	1	1	100.00
CONT_ASSIGN	3085	1	1	100.00
CONT_ASSIGN	3086	1	1	100.00
CONT_ASSIGN	3087	1	1	100.00
CONT_ASSIGN	3090	1	1	100.00
CONT_ASSIGN	3091	1	1	100.00
CONT_ASSIGN	3092	1	1	100.00
CONT_ASSIGN	3093	1	1	100.00
CONT_ASSIGN	3094	1	1	100.00
CONT_ASSIGN	3095	1	1	100.00
CONT_ASSIGN	3096	1	1	100.00
CONT_ASSIGN	3097	1	1	100.00
CONT_ASSIGN	3098	1	1	100.00
CONT_ASSIGN	3099	1	1	100.00
CONT_ASSIGN	3100	1	1	100.00
CONT_ASSIGN	3101	1	1	100.00
CONT_ASSIGN	3102	1	1	100.00
CONT_ASSIGN	3103	1	1	100.00
CONT_ASSIGN	3104	1	1	100.00
CONT_ASSIGN	3105	1	1	100.00
CONT_ASSIGN	3106	1	1	100.00
CONT_ASSIGN	3107	1	1	100.00
CONT_ASSIGN	3108	1	1	100.00
CONT_ASSIGN	3109	1	1	100.00
CONT_ASSIGN	3110	1	1	100.00
CONT_ASSIGN	3111	1	1	100.00
CONT_ASSIGN	3112	1	1	100.00
CONT_ASSIGN	3113	1	1	100.00
CONT_ASSIGN	3114	1	1	100.00
CONT_ASSIGN	3115	1	1	100.00
CONT_ASSIGN	3116	1	1	100.00
CONT_ASSIGN	3117	1	1	100.00
CONT_ASSIGN	3118	1	1	100.00
CONT_ASSIGN	3119	1	1	100.00
CONT_ASSIGN	3120	1	1	100.00
CONT_ASSIGN	3121	1	1	100.00
CONT_ASSIGN	3122	0	0
CONT_ASSIGN	3123	0	0
CONT_ASSIGN	3124	0	0
CONT_ASSIGN	3125	0	0
CONT_ASSIGN	3126	0	0
CONT_ASSIGN	3127	0	0
CONT_ASSIGN	3128	1	0	0.00
CONT_ASSIGN	3129	1	0	0.00
CONT_ASSIGN	3130	1	0	0.00
CONT_ASSIGN	3131	1	0	0.00
CONT_ASSIGN	3132	1	1	100.00
CONT_ASSIGN	3133	1	1	100.00
CONT_ASSIGN	3134	1	1	100.00
CONT_ASSIGN	3135	1	1	100.00
CONT_ASSIGN	3136	1	1	100.00
CONT_ASSIGN	3137	1	1	100.00
CONT_ASSIGN	3138	1	1	100.00
CONT_ASSIGN	3139	1	1	100.00
CONT_ASSIGN	3140	1	0	0.00
CONT_ASSIGN	3141	1	0	0.00
CONT_ASSIGN	3142	1	0	0.00
CONT_ASSIGN	3143	0	0
CONT_ASSIGN	3144	0	0
CONT_ASSIGN	3145	0	0
CONT_ASSIGN	3146	0	0
CONT_ASSIGN	3147	0	0
CONT_ASSIGN	3148	0	0
CONT_ASSIGN	3149	0	0
CONT_ASSIGN	3150	0	0
CONT_ASSIGN	3151	0	0
CONT_ASSIGN	3152	1	1	100.00
CONT_ASSIGN	3153	1	1	100.00
CONT_ASSIGN	3154	1	1	100.00
CONT_ASSIGN	3155	1	1	100.00
CONT_ASSIGN	3156	1	1	100.00
CONT_ASSIGN	3157	1	1	100.00
CONT_ASSIGN	3158	1	0	0.00
CONT_ASSIGN	3159	1	1	100.00
CONT_ASSIGN	3160	1	1	100.00
CONT_ASSIGN	3161	1	1	100.00
CONT_ASSIGN	3162	1	1	100.00
CONT_ASSIGN	3163	1	1	100.00
CONT_ASSIGN	3164	1	1	100.00
CONT_ASSIGN	3167	1	1	100.00
CONT_ASSIGN	3168	1	1	100.00
CONT_ASSIGN	3169	1	1	100.00
CONT_ASSIGN	3170	1	1	100.00
CONT_ASSIGN	3171	1	1	100.00
CONT_ASSIGN	3172	1	1	100.00
CONT_ASSIGN	3173	1	1	100.00
CONT_ASSIGN	3174	1	1	100.00
CONT_ASSIGN	3175	1	1	100.00
CONT_ASSIGN	3176	1	1	100.00
CONT_ASSIGN	3177	1	1	100.00
CONT_ASSIGN	3178	1	1	100.00
CONT_ASSIGN	3179	1	1	100.00
CONT_ASSIGN	3180	1	1	100.00
CONT_ASSIGN	3181	1	1	100.00
CONT_ASSIGN	3182	1	1	100.00
CONT_ASSIGN	3183	1	1	100.00
CONT_ASSIGN	3184	1	1	100.00
CONT_ASSIGN	3185	1	1	100.00
CONT_ASSIGN	3186	1	1	100.00
CONT_ASSIGN	3187	1	1	100.00
CONT_ASSIGN	3188	1	1	100.00
CONT_ASSIGN	3189	1	1	100.00
CONT_ASSIGN	3190	1	1	100.00
CONT_ASSIGN	3191	1	1	100.00
CONT_ASSIGN	3192	1	1	100.00
CONT_ASSIGN	3193	1	1	100.00
CONT_ASSIGN	3194	1	1	100.00
CONT_ASSIGN	3195	1	1	100.00
CONT_ASSIGN	3196	1	1	100.00
CONT_ASSIGN	3197	1	1	100.00
CONT_ASSIGN	3198	1	1	100.00
CONT_ASSIGN	3199	1	1	100.00
CONT_ASSIGN	3200	1	1	100.00
CONT_ASSIGN	3201	1	1	100.00
CONT_ASSIGN	3202	1	1	100.00
CONT_ASSIGN	3203	1	1	100.00
CONT_ASSIGN	3204	1	1	100.00
CONT_ASSIGN	3205	1	0	0.00
CONT_ASSIGN	3206	1	0	0.00
CONT_ASSIGN	3207	1	0	0.00
CONT_ASSIGN	3208	1	0	0.00
CONT_ASSIGN	3209	0	0
CONT_ASSIGN	3210	0	0
CONT_ASSIGN	3211	0	0
CONT_ASSIGN	3212	0	0
CONT_ASSIGN	3213	0	0
CONT_ASSIGN	3214	0	0
CONT_ASSIGN	3215	0	0
CONT_ASSIGN	3216	0	0
CONT_ASSIGN	3217	1	1	100.00
CONT_ASSIGN	3218	1	1	100.00
CONT_ASSIGN	3219	1	0	0.00
CONT_ASSIGN	3220	0	0
CONT_ASSIGN	3221	0	0
CONT_ASSIGN	3222	0	0
CONT_ASSIGN	3223	0	0
CONT_ASSIGN	3224	0	0
CONT_ASSIGN	3225	0	0
CONT_ASSIGN	3226	0	0
CONT_ASSIGN	3227	0	0
CONT_ASSIGN	3228	0	0
CONT_ASSIGN	3229	0	0
CONT_ASSIGN	3230	0	0
CONT_ASSIGN	3231	0	0
CONT_ASSIGN	3232	0	0
CONT_ASSIGN	3233	0	0
CONT_ASSIGN	3234	0	0
CONT_ASSIGN	3235	1	1	100.00
CONT_ASSIGN	3236	0	0
CONT_ASSIGN	3237	0	0
CONT_ASSIGN	3238	0	0
CONT_ASSIGN	3239	0	0
CONT_ASSIGN	3240	0	0
CONT_ASSIGN	3241	0	0
CONT_ASSIGN	3245	1	1	100.00
CONT_ASSIGN	3246	1	1	100.00
CONT_ASSIGN	3247	1	1	100.00
CONT_ASSIGN	3248	1	1	100.00
CONT_ASSIGN	3249	1	1	100.00
CONT_ASSIGN	3250	1	1	100.00
CONT_ASSIGN	3251	1	1	100.00
CONT_ASSIGN	3252	1	1	100.00
CONT_ASSIGN	3253	1	1	100.00
CONT_ASSIGN	3254	1	1	100.00
CONT_ASSIGN	3255	1	1	100.00
CONT_ASSIGN	3256	1	1	100.00
CONT_ASSIGN	3257	1	1	100.00
CONT_ASSIGN	3258	1	1	100.00
CONT_ASSIGN	3259	1	1	100.00
CONT_ASSIGN	3262	1	1	100.00
CONT_ASSIGN	3263	1	1	100.00
CONT_ASSIGN	3264	1	1	100.00
CONT_ASSIGN	3265	1	1	100.00
CONT_ASSIGN	3266	1	1	100.00
CONT_ASSIGN	3267	1	1	100.00
CONT_ASSIGN	3268	1	1	100.00
CONT_ASSIGN	3269	1	1	100.00
CONT_ASSIGN	3270	1	1	100.00
CONT_ASSIGN	3271	1	1	100.00
CONT_ASSIGN	3272	1	1	100.00
CONT_ASSIGN	3273	1	1	100.00
CONT_ASSIGN	3276	1	1	100.00
CONT_ASSIGN	3277	1	1	100.00
CONT_ASSIGN	3280	1	1	100.00
CONT_ASSIGN	3281	1	1	100.00
CONT_ASSIGN	3282	1	1	100.00
CONT_ASSIGN	3283	1	0	0.00
CONT_ASSIGN	3284	1	0	0.00
CONT_ASSIGN	3285	1	0	0.00
CONT_ASSIGN	3286	1	1	100.00
CONT_ASSIGN	3287	1	1	100.00
CONT_ASSIGN	3288	1	1	100.00
CONT_ASSIGN	3289	1	1	100.00
CONT_ASSIGN	3290	0	0
CONT_ASSIGN	3291	0	0
CONT_ASSIGN	3294	1	1	100.00
CONT_ASSIGN	3295	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' or '../src/lowrisc_systems_top_earlgrey_0.1/rtl/autogen/top_earlgrey.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
747	1	1
748	1	1
749	1	1
750	0	1
751	0	1
752	0	1
753	0	1
754	0	1
767	1	1
768	0	1
769	0	1
770	0	1
771	0	1
772	0	1
773	0	1
774	0	1
788	1	1
790	1	1
792	1	1
794	1	1
796	1	1
800	1	1
810	1	1
811	1	1
815	1	1
839	1	1
840	1	1
842	1	1
843	1	1
845	1	1
846	1	1
848	1	1
849	1	1
851	1	1
852	1	1
854	1	1
855	1	1
857	1	1
858	1	1
860	1	1
861	1	1
863	1	1
864	1	1
866	1	1
867	1	1
869	0	1
870	1	1
872	0	1
873	1	1
875	1	1
876	1	1
878	1	1
879	1	1
881	1	1
882	1	1
884	1	1
885	1	1
887	1	1
888	1	1
890	1	1
891	1	1
893	1	1
894	1	1
896	1	1
897	1	1
899	1	1
900	1	1
902	1	1
903	1	1
905	1	1
906	1	1
908	1	1
909	1	1
915		unreachable
917		unreachable
919		unreachable
921		unreachable
923		unreachable
925		unreachable
927		unreachable
929		unreachable
931		unreachable
933		unreachable
935		unreachable
937		unreachable
939		unreachable
941		unreachable
943		unreachable
945		unreachable
947		unreachable
949		unreachable
951		unreachable
953		unreachable
955		unreachable
957		unreachable
959		unreachable
961		unreachable
963		unreachable
965		unreachable
967		unreachable
969		unreachable
971		unreachable
973		unreachable
975		unreachable
977		unreachable
979		unreachable
981		unreachable
983		unreachable
985		unreachable
987		unreachable
989		unreachable
991		unreachable
993		unreachable
995		unreachable
997		unreachable
999		unreachable
1001		unreachable
1003		unreachable
1005		unreachable
1007		unreachable
2631	1	1
3031	1	1
3032	1	1
3033	1	1
3034	1	1
3035	1	1
3036	1	1
3037	1	1
3038	1	1
3039	1	1
3040	1	1
3041	1	1
3042	1	1
3043	1	1
3044	1	1
3045	1	1
3046	1	1
3047	1	1
3048	1	1
3049	1	1
3050	1	1
3051	1	1
3052	1	1
3053	1	1
3054	1	1
3055	1	1
3056	1	1
3057	1	1
3058	1	1
3059	1	1
3060	1	1
3061	1	1
3062	1	1
3063	1	1
3064	1	1
3065	1	1
3066	1	1
3067	1	1
3068	1	1
3069	1	1
3070	1	1
3071	1	1
3072	1	1
3073	1	1
3074	1	1
3075	1	1
3076	1	1
3077	1	1
3078	1	1
3079	1	1
3080	1	1
3081	1	1
3082	1	1
3083	1	1
3084	1	1
3085	1	1
3086	1	1
3087	1	1
3090	1	1
3091	1	1
3092	1	1
3093	1	1
3094	1	1
3095	1	1
3096	1	1
3097	1	1
3098	1	1
3099	1	1
3100	1	1
3101	1	1
3102	1	1
3103	1	1
3104	1	1
3105	1	1
3106	1	1
3107	1	1
3108	1	1
3109	1	1
3110	1	1
3111	1	1
3112	1	1
3113	1	1
3114	1	1
3115	1	1
3116	1	1
3117	1	1
3118	1	1
3119	1	1
3120	1	1
3121	1	1
3122		unreachable
3123		unreachable
3124		unreachable
3125		unreachable
3126		unreachable
3127		unreachable
3128	0	1
3129	0	1
3130	0	1
3131	0	1
3132	1	1
3133	1	1
3134	1	1
3135	1	1
3136	1	1
3137	1	1
3138	1	1
3139	1	1
3140	0	1
3141	0	1
3142	0	1
3143		unreachable
3144		unreachable
3145		unreachable
3146		unreachable
3147		unreachable
3148		unreachable
3149		unreachable
3150		unreachable
3151		unreachable
3152	1	1
3153	1	1
3154	1	1
3155	1	1
3156	1	1
3157	1	1
3158	0	1
3159	1	1
3160	1	1
3161	1	1
3162	1	1
3163	1	1
3164	1	1
3167	1	1
3168	1	1
3169	1	1
3170	1	1
3171	1	1
3172	1	1
3173	1	1
3174	1	1
3175	1	1
3176	1	1
3177	1	1
3178	1	1
3179	1	1
3180	1	1
3181	1	1
3182	1	1
3183	1	1
3184	1	1
3185	1	1
3186	1	1
3187	1	1
3188	1	1
3189	1	1
3190	1	1
3191	1	1
3192	1	1
3193	1	1
3194	1	1
3195	1	1
3196	1	1
3197	1	1
3198	1	1
3199	1	1
3200	1	1
3201	1	1
3202	1	1
3203	1	1
3204	1	1
3205	0	1
3206	0	1
3207	0	1
3208	0	1
3209		unreachable
3210		unreachable
3211		unreachable
3212		unreachable
3213		unreachable
3214		unreachable
3215		unreachable
3216		unreachable
3217	1	1
3218	1	1
3219	0	1
3220		unreachable
3221		unreachable
3222		unreachable
3223		unreachable
3224		unreachable
3225		unreachable
3226		unreachable
3227		unreachable
3228		unreachable
3229		unreachable
3230		unreachable
3231		unreachable
3232		unreachable
3233		unreachable
3234		unreachable
3235	1	1
3236		unreachable
3237		unreachable
3238		unreachable
3239		unreachable
3240		unreachable
3241		unreachable
3245	1	1
3246	1	1
3247	1	1
3248	1	1
3249	1	1
3250	1	1
3251	1	1
3252	1	1
3253	1	1
3254	1	1
3255	1	1
3256	1	1
3257	1	1
3258	1	1
3259	1	1
3262	1	1
3263	1	1
3264	1	1
3265	1	1
3266	1	1
3267	1	1
3268	1	1
3269	1	1
3270	1	1
3271	1	1
3272	1	1
3273	1	1
3276	1	1
3277	1	1
3280	1	1
3281	1	1
3282	1	1
3283	0	1
3284	0	1
3285	0	1
3286	1	1
3287	1	1
3288	1	1
3289	1	1
3290		unreachable
3291		unreachable
3294	1	1
3295	1	1

---

Toggle Coverage for Instance : tb.dut.top_earlgrey

	Total	Covered	Percent
Totals	526	486	92.40
Total Bits	1874	1753	93.54
Total Bits 0->1	937	878	93.70
Total Bits 1->0	937	875	93.38

Ports	526	486	92.40
Port Bits	1874	1753	93.54
Port Bits 0->1	937	878	93.70
Port Bits 1->0	937	875	93.38

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
mio_in_i[46:0]	Yes	Yes	T13,T14,T15	Yes	T13,T14,T15	INPUT
mio_out_o[46:0]	Yes	Yes	T25,T26,T27	Yes	T25,T26,T7	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T28,T29,T30	Yes	T25,T26,T7	OUTPUT
dio_in_i[15:0]	Yes	Yes	T16,T18,T23	Yes	T16,T18,T23	INPUT
dio_out_o[11:0]	Yes	Yes	*T16,*T17,*T18	Yes	T17,T18,T19	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T10,T11,T12	Yes	T10,T11,T12	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T18,T23,T24	Yes	T18,T23,T7	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T31,T32,T33	Yes	T38,T39,T40	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T31,T32,T33	Yes	T38,T39,T40	OUTPUT
mio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
mio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
mio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[16].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[17].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[18].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[19].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[20].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[21].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T41,T42,T43	Yes	T41,T44,T42	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T41,T42,T45	Yes	T41,T42,T45	OUTPUT
mio_attr_o[22].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[22].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T41,T42,T43	Yes	T41,T44,T42	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[23].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T41,T42,T43	Yes	T41,T44,T42	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[24].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T34,T5,T6	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T34,T5,T6	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[25].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[26].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[27].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[28].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[29].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[30].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[31].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[32].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[33].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[34].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[35].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[36].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[37].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[38].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[39].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[40].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[41].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[42].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[43].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[44].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[45].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
mio_attr_o[46].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[0].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T34,*T5,*T6	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T34,*T5,*T6	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T11,T12	OUTPUT
dio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T32,*T33,*T35	Yes	T32,T33,T35	OUTPUT
dio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[12].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[13].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].pull_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].invert	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T31,T32,T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T31,T32,T33	Yes	T10,T36,T37	OUTPUT
dio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T31,*T32,*T33	Yes	T31,T32,T33	OUTPUT
dio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
adc_req_o.pd	Yes	Yes	T119,T19,T138	Yes	T119,T19,T138	OUTPUT
adc_req_o.channel_sel[1:0]	Yes	Yes	T119,T19,T138	Yes	T119,T19,T138	OUTPUT
adc_rsp_i.data_valid	Yes	Yes	T119,T19,T138	Yes	T119,T19,T138	INPUT
adc_rsp_i.data[9:0]	Yes	Yes	T119,T19,T139	Yes	T119,T19,T139	INPUT
ast_edn_req_i.edn_req	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_edn_rsp_o.edn_bus[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
ast_edn_rsp_o.edn_fips	Yes	Yes	T140,T141	Yes	T101,T142,T143	OUTPUT
ast_edn_rsp_o.edn_ack	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_lc_dft_en_o[3:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
obs_ctrl_i.obmen[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obmsl[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
obs_ctrl_i.obgsl[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
ram_1p_cfg_i.rf_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.rf_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
ram_1p_cfg_i.ram_cfg.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
spi_ram_2p_cfg_i.b_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_lcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.b_ram_fcfg.cfg_en	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg[3:0]	No	No		No		INPUT
spi_ram_2p_cfg_i.a_ram_fcfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.rf_cfg.cfg_en	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg[3:0]	No	No		No		INPUT
usb_ram_1p_cfg_i.ram_cfg.cfg_en	No	No		No		INPUT
rom_cfg_i.cfg[3:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
rom_cfg_i.cfg_en[0:0]	Excluded	Excluded		Excluded		INPUT	[LOW_RISK] Covered in formal conn: hw/top_earlgrey/formal/conn_csvs/ast_mem_cfg.csv
clk_main_jitter_en_o[3:0]	Yes	Yes	T144,T145,T99	Yes	T146,T147,T148	OUTPUT
io_clk_byp_req_o[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T58	OUTPUT
io_clk_byp_ack_i[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T58	INPUT
all_clk_byp_req_o[3:0]	Yes	Yes	T149,T150,T151	Yes	T149,T150,T151	OUTPUT
all_clk_byp_ack_i[3:0]	Yes	Yes	T149,T150,T151	Yes	T149,T150,T151	INPUT
hi_speed_sel_o[3:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
div_step_down_req_i[3:0]	Yes	Yes	T4,T6,T59	Yes	T4,T6,T58	INPUT
calib_rdy_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
flash_bist_enable_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
flash_power_down_h_i	Yes	Yes	T1,T2,T3	Yes	T5,T118,T119	INPUT
flash_power_ready_h_i	No	No		Yes	T1,T2,T3	INPUT
flash_test_mode_a_io[1:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_test_voltage_h_io[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and flash. Must be covered in vendor closed source DV.
flash_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
es_rng_req_o.rng_enable	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	OUTPUT
es_rng_rsp_i.rng_b[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
es_rng_rsp_i.rng_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
es_rng_fips_o	Yes	Yes	T152,T153,T154	Yes	T34,T79,T108	OUTPUT
ast_tl_req_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_req_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	OUTPUT
ast_tl_req_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
ast_tl_req_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
ast_tl_req_o.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
ast_tl_req_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
ast_tl_rsp_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_error	Yes	Yes	T72,T75,T105	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_user.data_intg[6:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
ast_tl_rsp_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_data[31:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
ast_tl_rsp_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_source[5:0]	Yes	Yes	T72,*T73,T75	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_opcode[0]	Yes	Yes	*T72,*T74,*T75	Yes	T72,T74,T75	INPUT
ast_tl_rsp_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
ast_tl_rsp_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dft_strap_test_o.straps[1:0]	No	No		Yes	T63,T64,T65	OUTPUT
dft_strap_test_o.valid	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
usb_dp_pullup_en_o	Yes	Yes	T18,T19,T23	Yes	T17,T18,T19	OUTPUT
usb_dn_pullup_en_o	Yes	Yes	T69,T70,T71	Yes	T69,T70,T71	OUTPUT
pwrmgr_ast_req_o.usb_clk_en	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.io_clk_en	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.core_clk_en	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	OUTPUT
pwrmgr_ast_req_o.slow_clk_en	No	No		No		OUTPUT
pwrmgr_ast_req_o.pwr_clamp	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwrmgr_ast_req_o.pwr_clamp_env	Yes	Yes	T1,T2,T3	Yes	T4,T5,T6	OUTPUT
pwrmgr_ast_req_o.main_pd_n	Yes	Yes	T5,T118,T119	Yes	T5,T118,T119	OUTPUT
pwrmgr_ast_rsp_i.main_pok	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.usb_clk_val	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.io_clk_val	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.core_clk_val	Yes	Yes	T1,T4,T5	Yes	T1,T2,T3	INPUT
pwrmgr_ast_rsp_i.slow_clk_val	Yes	Yes	T149,T150,T151	Yes	T1,T2,T3	INPUT
otp_ctrl_otp_ast_pwr_seq_o.pwr_seq[1:0]	No	No		No		OUTPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[0]	No	No		No		INPUT
otp_ctrl_otp_ast_pwr_seq_h_i.pwr_seq_h[1]	Yes	Yes	T1,T2,T3	Yes	T5,T118,T119	INPUT
otp_ext_voltage_h_io[0:0]	Excluded	Excluded		Excluded		INOUT	[LOW_RISK] Covered via connectivity. Cannot be covered in open source DV due to behavioral models of AST and OTP. Must be covered in vendor closed source DV.
otp_obs_o[7:0]	Unreachable	Unreachable		Unreachable		OUTPUT
por_n_i[1:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	INPUT
fpga_info_i[31:0]	Unreachable	Unreachable		Unreachable		INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].n	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	INPUT
sensor_ctrl_ast_alert_req_i.alerts[0].p	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[1].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[2].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[3].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[4].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[5].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[6].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[7].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[8].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[9].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_req_i.alerts[10].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	INPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].n	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[0].p	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[1].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[2].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[3].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[4].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[5].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[6].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[7].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[8].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[9].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_trig[10].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].n	Yes	Yes	T155,T156,T157	Yes	T155,T156,T157	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[0].p	Yes	Yes	T155,T161,T162	Yes	T155,T161,T162	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[1].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[2].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[3].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].n	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[4].p	Yes	Yes	T156,T158,T160	Yes	T156,T158,T160	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[5].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[6].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[7].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[8].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[9].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].n	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_alert_rsp_o.alerts_ack[10].p	Yes	Yes	T156,T158,T159	Yes	T156,T158,T159	OUTPUT
sensor_ctrl_ast_status_i.io_pok[1:0]	Yes	Yes	T80,T163,T164	Yes	T1,T2,T3	INPUT
ast2pinmux_i[8:0]	Unreachable	Unreachable		Unreachable		INPUT
ast_init_done_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
sck_monitor_o	Yes	Yes	T106,T11,T12	Yes	T106,T11,T12	OUTPUT
usbdev_usb_rx_d_i	Yes	Yes	T18,T23,T69	Yes	T18,T23,T69	INPUT
usbdev_usb_tx_d_o	Yes	Yes	T16,T17,T18	Yes	T17,T18,T19	OUTPUT
usbdev_usb_tx_se0_o	Yes	Yes	T18,T23,T24	Yes	T18,T23,T24	OUTPUT
usbdev_usb_tx_use_d_se0_o	Yes	Yes	T165,T166,T167	Yes	T165,T166,T167	OUTPUT
usbdev_usb_rx_enable_o	Yes	Yes	T71,T165,T166	Yes	T18,T23,T69	OUTPUT
usbdev_usb_ref_val_o	Yes	Yes	T18,T23,T168	Yes	T18,T23,T24	OUTPUT
usbdev_usb_ref_pulse_o	Yes	Yes	T18,T23,T24	Yes	T18,T23,T24	OUTPUT
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_io_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clks_ast_o.clk_usb_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_infra	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_otbn	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_kmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_hmac	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_aes	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_timers	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_peri	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_secure	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div2_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_usb_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_main_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_aon_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
clks_ast_o.clk_io_div4_powerup	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c2_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c2_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c1_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_i2c0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_i2c0_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_aon_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_aon_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_usb_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_usb_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host1_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host1_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_host0_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_host0_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_spi_device_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_spi_device_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[0]	Yes	Yes	*T34,*T4,*T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_sys_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[0]	No	No		No		OUTPUT
rsts_ast_o.rst_sys_n[1]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_usb_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div4_shadowed_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_div2_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_io_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[0]	Yes	Yes	*T34,*T4,*T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_aon_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_lc_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_lc_shadowed_n[1:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_usb_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div4_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div4_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_div2_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_div2_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_io_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_io_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_n[0]	Yes	Yes	*T4,*T5,*T6	Yes	T1,T2,T3	OUTPUT
rsts_ast_o.rst_por_n[1]	No	No		No		OUTPUT
rsts_ast_o.rst_por_aon_n[1:0]	Yes	Yes	T4,T5,T6	Yes	T1,T2,T3	OUTPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
scan_en_i	Unreachable	Unreachable		Unreachable		INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range

---

Assert Coverage for Instance : tb.dut.top_earlgrey

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	1	1	100.00	1	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	1	1	100.00	1	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
scanmodeKnown	428003793	428003793	0	0

scanmodeKnown

Name	Attempts	Real Successes	Failures	Incomplete
Total	428003793	428003793	0	0
T1	143836	143836	0	0
T2	77136	77136	0	0
T3	354243	354243	0	0
T4	54458	54458	0	0
T5	327190	327190	0	0
T6	337980	337980	0	0
T13	363854	363854	0	0
T34	141940	141940	0	0
T79	693376	693376	0	0
T80	100678	100678	0	0