Unified Coverage Report :: Module :: xbar_main

Module : xbar_main

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_top_earlgrey_xbar_main_0.1/rtl/autogen/xbar_main.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_xbar_main	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_xbar_main

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.25	89.21		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : xbar_main

	Total	Covered	Percent
Totals	550	550	100.00
Total Bits	6824	6824	100.00
Total Bits 0->1	3412	3412	100.00
Total Bits 1->0	3412	3412	100.00

Ports	550	550	100.00
Port Bits	6824	6824	100.00
Port Bits 0->1	3412	3412	100.00
Port Bits 1->0	3412	3412	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_main_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_fixed_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_usb_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host0_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_spi_host1_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_main_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
rst_fixed_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
rst_usb_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
rst_spi_host0_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
rst_spi_host1_ni	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.d_ready	Yes	Yes	T72,T73,T75	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.data_intg[6:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_user.instr_type[3:0]	Yes	Yes	T75,T221,T222	Yes	T75,T221,T222	INPUT
tl_rv_core_ibex__corei_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_data[31:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_mask[3:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__corei_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__corei_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__corei_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_error	Yes	Yes	T61,T198,T134	Yes	T61,T198,T134	OUTPUT
tl_rv_core_ibex__corei_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_user.rsp_intg[6:0]	Yes	Yes	T61,T198,T134	Yes	T61,T198,T134	OUTPUT
tl_rv_core_ibex__corei_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__corei_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__corei_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__corei_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_i.d_ready	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_rv_core_ibex__cored_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_user.instr_type[3:0]	Yes	Yes	T75,T105,T223	Yes	T75,T105,T223	INPUT
tl_rv_core_ibex__cored_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cored_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cored_i.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cored_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_error	Yes	Yes	T60,T61,T62	Yes	T60,T61,T62	OUTPUT
tl_rv_core_ibex__cored_o.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cored_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cored_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cored_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_i.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.data_intg[6:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_rv_dm__sba_i.a_user.cmd_intg[6:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.instr_type[3:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_data[31:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_rv_dm__sba_i.a_mask[3:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_rv_dm__sba_i.a_address[31:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__sba_i.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__sba_i.a_valid	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	INPUT
tl_rv_dm__sba_o.a_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__sba_o.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_user.data_intg[6:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_user.rsp_intg[6:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_data[31:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[5:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__sba_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_opcode[0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	OUTPUT
tl_rv_dm__sba_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__sba_o.d_valid	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
tl_rv_dm__regs_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__regs_o.a_user.data_intg[6:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_user.instr_type[3:0]	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_data[31:0]	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_mask[3:0]	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_source[5:0]	Yes	Yes	*T20,T72,*T74	Yes	T20,T72,T74	OUTPUT
tl_rv_dm__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__regs_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_rv_dm__regs_o.a_valid	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	OUTPUT
tl_rv_dm__regs_i.a_ready	Yes	Yes	T20,T72,T73	Yes	T20,T72,T73	INPUT
tl_rv_dm__regs_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_dm__regs_i.d_user.data_intg[6:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_dm__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	INPUT
tl_rv_dm__regs_i.d_data[31:0]	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	INPUT
tl_rv_dm__regs_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_dm__regs_i.d_source[5:0]	Yes	Yes	*T20,T72,T74	Yes	T20,T72,T74	INPUT
tl_rv_dm__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_dm__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_opcode[0]	Yes	Yes	*T20,*T72,*T74	Yes	T20,T72,T74	INPUT
tl_rv_dm__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__regs_i.d_valid	Yes	Yes	T20,T72,T74	Yes	T20,T72,T74	INPUT
tl_rv_dm__mem_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rv_dm__mem_o.a_user.data_intg[6:0]	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	OUTPUT
tl_rv_dm__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	OUTPUT
tl_rv_dm__mem_o.a_user.instr_type[3:0]	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	OUTPUT
tl_rv_dm__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_data[31:0]	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	OUTPUT
tl_rv_dm__mem_o.a_mask[3:0]	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	OUTPUT
tl_rv_dm__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_source[5:0]	Yes	Yes	*T193,*T194,*T227	Yes	T193,T194,T227	OUTPUT
tl_rv_dm__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_dm__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_dm__mem_o.a_valid	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	OUTPUT
tl_rv_dm__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_dm__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
tl_rv_dm__mem_i.d_user.data_intg[6:0]	Yes	Yes	T193,T194,T227	Yes	T193,T194,T227	INPUT
tl_rv_dm__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	INPUT
tl_rv_dm__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
tl_rv_dm__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_source[5:0]	Yes	Yes	*T193,*T194,*T227	Yes	T193,T194,T227	INPUT
tl_rv_dm__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_dm__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T34,T4,T5	INPUT
tl_rv_dm__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_dm__mem_i.d_valid	Yes	Yes	T20,T193,T194	Yes	T20,T193,T194	INPUT
tl_rom_ctrl__rom_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.data_intg[6:0]	Yes	Yes	T41,T44,T42	Yes	T41,T44,T42	OUTPUT
tl_rom_ctrl__rom_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_data[31:0]	Yes	Yes	T41,T42,T66	Yes	T41,T42,T66	OUTPUT
tl_rom_ctrl__rom_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__rom_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__rom_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__rom_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__rom_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__rom_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__rom_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rom_ctrl__regs_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_rom_ctrl__regs_o.a_user.data_intg[6:0]	Yes	Yes	T55,T20,T56	Yes	T55,T20,T56	OUTPUT
tl_rom_ctrl__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T20,T239	Yes	T55,T20,T239	OUTPUT
tl_rom_ctrl__regs_o.a_user.instr_type[3:0]	Yes	Yes	T55,T20,T239	Yes	T55,T20,T239	OUTPUT
tl_rom_ctrl__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_data[31:0]	Yes	Yes	T55,T20,T56	Yes	T55,T20,T56	OUTPUT
tl_rom_ctrl__regs_o.a_mask[3:0]	Yes	Yes	T55,T20,T239	Yes	T55,T20,T239	OUTPUT
tl_rom_ctrl__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_source[5:0]	Yes	Yes	*T20,T72,T73	Yes	T20,T72,T73	OUTPUT
tl_rom_ctrl__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_size[1:0]	Yes	Yes	T72,T73,T75	Yes	T72,T73,T75	OUTPUT
tl_rom_ctrl__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rom_ctrl__regs_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rom_ctrl__regs_o.a_valid	Yes	Yes	T55,T20,T239	Yes	T55,T20,T239	OUTPUT
tl_rom_ctrl__regs_i.a_ready	Yes	Yes	T55,T20,T239	Yes	T55,T20,T239	INPUT
tl_rom_ctrl__regs_i.d_error	Yes	Yes	T72,T73,T75	Yes	T72,T73,T75	INPUT
tl_rom_ctrl__regs_i.d_user.data_intg[6:0]	Yes	Yes	T239,T349,T350	Yes	T239,T349,T350	INPUT
tl_rom_ctrl__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T72,T73	Yes	T55,T20,T56	INPUT
tl_rom_ctrl__regs_i.d_data[31:0]	Yes	Yes	T20,T239,T349	Yes	T55,T20,T239	INPUT
tl_rom_ctrl__regs_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rom_ctrl__regs_i.d_source[5:0]	Yes	Yes	*T20,T72,T73	Yes	T20,T72,T73	INPUT
tl_rom_ctrl__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_size[1:0]	Yes	Yes	T72,T73,T75	Yes	T72,T73,T75	INPUT
tl_rom_ctrl__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_opcode[0]	Yes	Yes	*T20,*T239,*T349	Yes	T20,T239,T349	INPUT
tl_rom_ctrl__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rom_ctrl__regs_i.d_valid	Yes	Yes	T55,T20,T239	Yes	T55,T20,T239	INPUT
tl_peri_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	OUTPUT
tl_peri_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_peri_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_peri_o.a_opcode[2:0]	Yes	Yes	T20,T66,T67	Yes	T20,T66,T67	OUTPUT
tl_peri_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_peri_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_error	Yes	Yes	T62,T293,T236	Yes	T62,T293,T236	INPUT
tl_peri_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_source[5:0]	Yes	Yes	*T20,*T66,*T67	Yes	T20,T66,T67	INPUT
tl_peri_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_peri_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_peri_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_peri_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_spi_host0_o.d_ready	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_o.a_user.data_intg[6:0]	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_o.a_user.instr_type[3:0]	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_data[31:0]	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_o.a_mask[3:0]	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	OUTPUT
tl_spi_host0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_spi_host0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host0_o.a_opcode[2:0]	Yes	Yes	T12,T173,T84	Yes	T12,T173,T84	OUTPUT
tl_spi_host0_o.a_valid	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	OUTPUT
tl_spi_host0_i.a_ready	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	INPUT
tl_spi_host0_i.d_error	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
tl_spi_host0_i.d_user.data_intg[6:0]	Yes	Yes	T20,T10,T11	Yes	T20,T10,T11	INPUT
tl_spi_host0_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T114,T10	Yes	T55,T20,T114	INPUT
tl_spi_host0_i.d_data[31:0]	Yes	Yes	T20,T10,T11	Yes	T20,T10,T11	INPUT
tl_spi_host0_i.d_sink	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
tl_spi_host0_i.d_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	INPUT
tl_spi_host0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_size[1:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
tl_spi_host0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_opcode[0]	Yes	Yes	*T20,*T10,*T11	Yes	T20,T10,T11	INPUT
tl_spi_host0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host0_i.d_valid	Yes	Yes	T55,T20,T114	Yes	T55,T20,T114	INPUT
tl_spi_host1_o.d_ready	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_o.a_user.data_intg[6:0]	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_o.a_user.instr_type[3:0]	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_data[31:0]	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_o.a_mask[3:0]	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_source[5:0]	Yes	Yes	*T20,*T176,T72	Yes	T20,T176,T72	OUTPUT
tl_spi_host1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_spi_host1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_spi_host1_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_spi_host1_o.a_valid	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	OUTPUT
tl_spi_host1_i.a_ready	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	INPUT
tl_spi_host1_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_spi_host1_i.d_user.data_intg[6:0]	Yes	Yes	T20,T176,T109	Yes	T20,T176,T109	INPUT
tl_spi_host1_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T176,T109	Yes	T55,T20,T176	INPUT
tl_spi_host1_i.d_data[31:0]	Yes	Yes	T20,T176,T109	Yes	T20,T176,T109	INPUT
tl_spi_host1_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_spi_host1_i.d_source[5:0]	Yes	Yes	*T20,*T176,T72	Yes	T20,T176,T72	INPUT
tl_spi_host1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_spi_host1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_opcode[0]	Yes	Yes	*T20,*T176,*T109	Yes	T20,T176,T109	INPUT
tl_spi_host1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_spi_host1_i.d_valid	Yes	Yes	T55,T20,T176	Yes	T55,T20,T176	INPUT
tl_usbdev_o.d_ready	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_o.a_user.data_intg[6:0]	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_o.a_user.instr_type[3:0]	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_data[31:0]	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_o.a_mask[3:0]	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	OUTPUT
tl_usbdev_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_size[1:0]	Yes	Yes	T72,T73,T75	Yes	T72,T73,T75	OUTPUT
tl_usbdev_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_usbdev_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_usbdev_o.a_valid	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	OUTPUT
tl_usbdev_i.a_ready	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	INPUT
tl_usbdev_i.d_error	Yes	Yes	T72,T73,T75	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_user.data_intg[6:0]	Yes	Yes	T20,T264,T328	Yes	T20,T264,T328	INPUT
tl_usbdev_i.d_user.rsp_intg[6:0]	Yes	Yes	T20,T264,T328	Yes	T20,T264,T328	INPUT
tl_usbdev_i.d_data[31:0]	Yes	Yes	T55,T20,T17	Yes	T20,T17,T264	INPUT
tl_usbdev_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_usbdev_i.d_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	INPUT
tl_usbdev_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_size[1:0]	Yes	Yes	T72,T73,T75	Yes	T72,T73,T75	INPUT
tl_usbdev_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_opcode[0]	Yes	Yes	*T55,*T20,*T17	Yes	T20,T17,T264	INPUT
tl_usbdev_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_usbdev_i.d_valid	Yes	Yes	T55,T20,T17	Yes	T55,T20,T17	INPUT
tl_flash_ctrl__core_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__core_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__core_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_flash_ctrl__core_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__core_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_error	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
tl_flash_ctrl__core_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T34,T5,T6	INPUT
tl_flash_ctrl__core_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T74,T75	INPUT
tl_flash_ctrl__core_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__core_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_flash_ctrl__core_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__core_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__core_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__prim_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__prim_o.a_user.data_intg[6:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.cmd_intg[6:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.instr_type[3:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_data[31:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_o.a_mask[3:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_source[5:0]	Yes	Yes	*T176,*T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__prim_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_flash_ctrl__prim_o.a_valid	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	OUTPUT
tl_flash_ctrl__prim_i.a_ready	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__prim_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T75,T105	INPUT
tl_flash_ctrl__prim_i.d_user.data_intg[6:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__prim_i.d_user.rsp_intg[6:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__prim_i.d_data[31:0]	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__prim_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_source[5:0]	Yes	Yes	*T176,*T199,T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__prim_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_flash_ctrl__prim_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_opcode[0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__prim_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__prim_i.d_valid	Yes	Yes	T176,T199,T72	Yes	T176,T199,T72	INPUT
tl_flash_ctrl__mem_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_data[31:0]	Yes	Yes	T1,T3,T34	Yes	T1,T3,T34	OUTPUT
tl_flash_ctrl__mem_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_flash_ctrl__mem_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_flash_ctrl__mem_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_flash_ctrl__mem_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_error	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
tl_flash_ctrl__mem_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_flash_ctrl__mem_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_opcode[0]	Yes	Yes	*T72,*T73,*T74	Yes	T72,T73,T74	INPUT
tl_flash_ctrl__mem_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_flash_ctrl__mem_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_hmac_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_hmac_o.a_user.data_intg[6:0]	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	OUTPUT
tl_hmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	OUTPUT
tl_hmac_o.a_user.instr_type[3:0]	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	OUTPUT
tl_hmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_data[31:0]	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	OUTPUT
tl_hmac_o.a_mask[3:0]	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	OUTPUT
tl_hmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_hmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_hmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_hmac_o.a_opcode[2:0]	Yes	Yes	T710,T287,T288	Yes	T710,T287,T288	OUTPUT
tl_hmac_o.a_valid	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	OUTPUT
tl_hmac_i.a_ready	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	INPUT
tl_hmac_i.d_error	Yes	Yes	T74,T75,T105	Yes	T74,T75,T105	INPUT
tl_hmac_i.d_user.data_intg[6:0]	Yes	Yes	T41,T44,T42	Yes	T41,T44,T42	INPUT
tl_hmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T41,T44,T42	Yes	T41,T44,T42	INPUT
tl_hmac_i.d_data[31:0]	Yes	Yes	T55,T41,T44	Yes	T41,T44,T42	INPUT
tl_hmac_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_hmac_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_hmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_hmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_opcode[0]	Yes	Yes	*T55,*T41,*T44	Yes	T41,T44,T42	INPUT
tl_hmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_hmac_i.d_valid	Yes	Yes	T55,T41,T44	Yes	T55,T41,T44	INPUT
tl_kmac_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_kmac_o.a_user.data_intg[6:0]	Yes	Yes	T55,T356,T128	Yes	T55,T356,T128	OUTPUT
tl_kmac_o.a_user.cmd_intg[6:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_kmac_o.a_user.instr_type[3:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_kmac_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_data[31:0]	Yes	Yes	T55,T356,T128	Yes	T55,T356,T128	OUTPUT
tl_kmac_o.a_mask[3:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_kmac_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_kmac_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_kmac_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_kmac_o.a_opcode[2:0]	Yes	Yes	T356,T362,T363	Yes	T356,T362,T363	OUTPUT
tl_kmac_o.a_valid	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_kmac_i.a_ready	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	INPUT
tl_kmac_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_kmac_i.d_user.data_intg[6:0]	Yes	Yes	T34,T108,T356	Yes	T34,T108,T356	INPUT
tl_kmac_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T108,T356	Yes	T34,T108,T356	INPUT
tl_kmac_i.d_data[31:0]	Yes	Yes	T34,T55,T108	Yes	T356,T128,T362	INPUT
tl_kmac_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_kmac_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_kmac_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_kmac_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_opcode[0]	Yes	Yes	*T34,*T55,*T108	Yes	T356,T362,T363	INPUT
tl_kmac_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_kmac_i.d_valid	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	INPUT
tl_aes_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_aes_o.a_user.data_intg[6:0]	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	OUTPUT
tl_aes_o.a_user.cmd_intg[6:0]	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	OUTPUT
tl_aes_o.a_user.instr_type[3:0]	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	OUTPUT
tl_aes_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_data[31:0]	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	OUTPUT
tl_aes_o.a_mask[3:0]	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	OUTPUT
tl_aes_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_source[5:0]	Yes	Yes	*T72,*T75,*T105	Yes	T72,T75,T105	OUTPUT
tl_aes_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_aes_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_aes_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_aes_o.a_valid	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	OUTPUT
tl_aes_i.a_ready	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	INPUT
tl_aes_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_aes_i.d_user.data_intg[6:0]	Yes	Yes	T262,T212,T145	Yes	T262,T212,T145	INPUT
tl_aes_i.d_user.rsp_intg[6:0]	Yes	Yes	T262,T212,T145	Yes	T55,T262,T212	INPUT
tl_aes_i.d_data[31:0]	Yes	Yes	T262,T145,T154	Yes	T55,T262,T212	INPUT
tl_aes_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_aes_i.d_source[5:0]	Yes	Yes	*T72,*T75,*T105	Yes	T72,T75,T105	INPUT
tl_aes_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_aes_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_opcode[0]	Yes	Yes	*T262,*T212,*T145	Yes	T262,T212,T145	INPUT
tl_aes_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_aes_i.d_valid	Yes	Yes	T55,T262,T212	Yes	T55,T262,T212	INPUT
tl_entropy_src_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_entropy_src_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_entropy_src_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_entropy_src_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_entropy_src_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_entropy_src_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_entropy_src_i.d_user.data_intg[6:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T108	INPUT
tl_entropy_src_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_data[31:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_entropy_src_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_entropy_src_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_entropy_src_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_entropy_src_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_opcode[0]	Yes	Yes	*T34,*T79,*T108	Yes	T34,T79,T108	INPUT
tl_entropy_src_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_entropy_src_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_data[31:0]	Yes	Yes	T34,T79,T250	Yes	T34,T79,T250	OUTPUT
tl_csrng_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_csrng_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_csrng_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_csrng_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_csrng_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_csrng_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_error	Yes	Yes	T72,T75,T105	Yes	T72,T74,T75	INPUT
tl_csrng_i.d_user.data_intg[6:0]	Yes	Yes	T34,T79,T250	Yes	T34,T79,T250	INPUT
tl_csrng_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_data[31:0]	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	INPUT
tl_csrng_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_csrng_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_csrng_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_csrng_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_opcode[0]	Yes	Yes	*T34,*T79,*T250	Yes	T34,T79,T250	INPUT
tl_csrng_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_csrng_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.data_intg[6:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn0_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_data[31:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn0_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_edn0_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_edn0_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn0_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_edn0_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_edn0_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_edn0_i.d_user.data_intg[6:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T108	INPUT
tl_edn0_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_data[31:0]	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	INPUT
tl_edn0_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_edn0_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_edn0_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_edn0_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_opcode[0]	Yes	Yes	*T34,*T79,*T108	Yes	T34,T79,T108	INPUT
tl_edn0_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn0_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_edn1_o.d_ready	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	OUTPUT
tl_edn1_o.a_user.data_intg[6:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn1_o.a_user.cmd_intg[6:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn1_o.a_user.instr_type[3:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn1_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_data[31:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn1_o.a_mask[3:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn1_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_edn1_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_edn1_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_edn1_o.a_valid	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_edn1_i.a_ready	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	INPUT
tl_edn1_i.d_error	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_user.data_intg[6:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T108	INPUT
tl_edn1_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T55	INPUT
tl_edn1_i.d_data[31:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T55	INPUT
tl_edn1_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_edn1_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_size[1:0]	Yes	Yes	T72,T73,T75	Yes	T72,T73,T74	INPUT
tl_edn1_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_opcode[0]	Yes	Yes	*T34,*T79,*T108	Yes	T34,T79,T108	INPUT
tl_edn1_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_edn1_i.d_valid	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	INPUT
tl_rv_plic_o.d_ready	Yes	Yes	T1,T3,T34	Yes	T1,T2,T3	OUTPUT
tl_rv_plic_o.a_user.data_intg[6:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_rv_plic_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_rv_plic_o.a_user.instr_type[3:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_rv_plic_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_data[31:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_rv_plic_o.a_mask[3:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_rv_plic_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	OUTPUT
tl_rv_plic_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_rv_plic_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_plic_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_rv_plic_o.a_valid	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	OUTPUT
tl_rv_plic_i.a_ready	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
tl_rv_plic_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_plic_i.d_user.data_intg[6:0]	Yes	Yes	T3,T13,T60	Yes	T3,T13,T60	INPUT
tl_rv_plic_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
tl_rv_plic_i.d_data[31:0]	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
tl_rv_plic_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_plic_i.d_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	INPUT
tl_rv_plic_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_rv_plic_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_opcode[0]	Yes	Yes	*T1,*T3,*T13	Yes	T1,T3,T13	INPUT
tl_rv_plic_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_plic_i.d_valid	Yes	Yes	T1,T3,T13	Yes	T1,T3,T13	INPUT
tl_otbn_o.d_ready	Yes	Yes	T34,T4,T79	Yes	T1,T2,T3	OUTPUT
tl_otbn_o.a_user.data_intg[6:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_otbn_o.a_user.cmd_intg[6:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_otbn_o.a_user.instr_type[3:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_otbn_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_data[31:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_otbn_o.a_mask[3:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_otbn_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_source[5:0]	Yes	Yes	*T66,*T67,*T357	Yes	T66,T67,T357	OUTPUT
tl_otbn_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_otbn_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_otbn_o.a_opcode[2:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	OUTPUT
tl_otbn_o.a_valid	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	OUTPUT
tl_otbn_i.a_ready	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	INPUT
tl_otbn_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_otbn_i.d_user.data_intg[6:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T108	INPUT
tl_otbn_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T79,T108	Yes	T34,T79,T108	INPUT
tl_otbn_i.d_data[31:0]	Yes	Yes	T34,T79,T55	Yes	T34,T79,T108	INPUT
tl_otbn_i.d_sink	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
tl_otbn_i.d_source[5:0]	Yes	Yes	*T66,*T67,*T357	Yes	T66,T67,T357	INPUT
tl_otbn_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_otbn_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_opcode[0]	Yes	Yes	*T34,*T79,*T55	Yes	T34,T79,T108	INPUT
tl_otbn_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_otbn_i.d_valid	Yes	Yes	T34,T79,T55	Yes	T34,T79,T55	INPUT
tl_keymgr_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_keymgr_o.a_user.data_intg[6:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_keymgr_o.a_user.cmd_intg[6:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_keymgr_o.a_user.instr_type[3:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_keymgr_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_data[31:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_keymgr_o.a_mask[3:0]	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_keymgr_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	OUTPUT
tl_keymgr_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_size[1:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	OUTPUT
tl_keymgr_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_keymgr_o.a_opcode[2:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	OUTPUT
tl_keymgr_o.a_valid	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	OUTPUT
tl_keymgr_i.a_ready	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	INPUT
tl_keymgr_i.d_error	Yes	Yes	T72,T75,T105	Yes	T72,T74,T75	INPUT
tl_keymgr_i.d_user.data_intg[6:0]	Yes	Yes	T34,T108,T128	Yes	T34,T108,T128	INPUT
tl_keymgr_i.d_user.rsp_intg[6:0]	Yes	Yes	T34,T108,T128	Yes	T34,T55,T108	INPUT
tl_keymgr_i.d_data[31:0]	Yes	Yes	T34,T108,T128	Yes	T34,T55,T108	INPUT
tl_keymgr_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T75,T105	INPUT
tl_keymgr_i.d_source[5:0]	Yes	Yes	*T176,*T199,*T72	Yes	T176,T199,T72	INPUT
tl_keymgr_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_size[1:0]	Yes	Yes	T72,T75,T105	Yes	T72,T75,T105	INPUT
tl_keymgr_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_opcode[0]	Yes	Yes	*T34,*T108,*T128	Yes	T34,T108,T128	INPUT
tl_keymgr_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_keymgr_i.d_valid	Yes	Yes	T34,T55,T108	Yes	T34,T55,T108	INPUT
tl_rv_core_ibex__cfg_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_source[5:0]	Yes	Yes	*T20,*T72,*T73	Yes	T20,T72,T73	OUTPUT
tl_rv_core_ibex__cfg_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_rv_core_ibex__cfg_o.a_opcode[2:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_rv_core_ibex__cfg_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_rv_core_ibex__cfg_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_error	Yes	Yes	T20,T72,T73	Yes	T20,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_user.data_intg[6:0]	Yes	Yes	T1,T80,T60	Yes	T1,T80,T60	INPUT
tl_rv_core_ibex__cfg_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_data[31:0]	Yes	Yes	T1,T80,T60	Yes	T1,T80,T60	INPUT
tl_rv_core_ibex__cfg_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T75	INPUT
tl_rv_core_ibex__cfg_i.d_source[5:0]	Yes	Yes	*T20,*T72,*T73	Yes	T20,T72,T73	INPUT
tl_rv_core_ibex__cfg_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_rv_core_ibex__cfg_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_rv_core_ibex__cfg_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_rv_core_ibex__cfg_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__regs_o.d_ready	Yes	Yes	T34,T4,T5	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.data_intg[6:0]	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.cmd_intg[6:0]	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.instr_type[3:0]	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	OUTPUT
tl_sram_ctrl_main__regs_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_data[31:0]	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	OUTPUT
tl_sram_ctrl_main__regs_o.a_mask[3:0]	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	OUTPUT
tl_sram_ctrl_main__regs_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_source[5:0]	Yes	Yes	*T20,*T176,*T72	Yes	T20,T176,T72	OUTPUT
tl_sram_ctrl_main__regs_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__regs_o.a_opcode[2:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	OUTPUT
tl_sram_ctrl_main__regs_o.a_valid	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	OUTPUT
tl_sram_ctrl_main__regs_i.a_ready	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	INPUT
tl_sram_ctrl_main__regs_i.d_error	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_user.data_intg[6:0]	Yes	Yes	T20,T176,T72	Yes	T20,T176,T72	INPUT
tl_sram_ctrl_main__regs_i.d_user.rsp_intg[6:0]	Yes	Yes	T133,T132,T20	Yes	T133,T55,T132	INPUT
tl_sram_ctrl_main__regs_i.d_data[31:0]	Yes	Yes	T133,T132,T20	Yes	T133,T55,T132	INPUT
tl_sram_ctrl_main__regs_i.d_sink	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_source[5:0]	Yes	Yes	*T20,*T176,T72	Yes	T20,T176,T72	INPUT
tl_sram_ctrl_main__regs_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_size[1:0]	Yes	Yes	T72,T74,T75	Yes	T72,T74,T75	INPUT
tl_sram_ctrl_main__regs_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_opcode[0]	Yes	Yes	*T133,*T132,*T20	Yes	T133,T132,T20	INPUT
tl_sram_ctrl_main__regs_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__regs_i.d_valid	Yes	Yes	T133,T55,T132	Yes	T133,T55,T132	INPUT
tl_sram_ctrl_main__ram_o.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_address[31:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	OUTPUT
tl_sram_ctrl_main__ram_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_sram_ctrl_main__ram_o.a_opcode[2:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_o.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_sram_ctrl_main__ram_i.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_error	Yes	Yes	T1,T2,T3	Yes	T34,T4,T5	INPUT
tl_sram_ctrl_main__ram_i.d_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_user.rsp_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_sink	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_source[5:0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_size[1:0]	Yes	Yes	T72,T73,T74	Yes	T72,T73,T74	INPUT
tl_sram_ctrl_main__ram_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_sram_ctrl_main__ram_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
tl_sram_ctrl_main__ram_i.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT

*Tests covering at least one bit in the range