Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : pwrmgr
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_pwrmgr_component_0.1/rtl/pwrmgr.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_pwrmgr_aon 100.00 100.00


Module Instance : tb.dut.top_earlgrey.u_pwrmgr_aon

Instance :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Instance's subtree :
SCORELINECONDTOGGLEFSMBRANCHASSERT
100.00 100.00


Parent :
SCORELINECONDTOGGLEFSMBRANCHASSERTNAME
94.25 89.21 93.54 100.00 top_earlgrey


Subtrees :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
no children

Since this is the module's only instance, the coverage report is the same as for the module.
Toggle Coverage for Module : pwrmgr
TotalCoveredPercent
Totals 83 83 100.00
Total Bits 460 460 100.00
Total Bits 0->1 230 230 100.00
Total Bits 1->0 230 230 100.00

Ports 83 83 100.00
Port Bits 460 460 100.00
Port Bits 0->1 230 230 100.00
Port Bits 1->0 230 230 100.00

Port Details
NameToggleToggle 1->0TestsToggle 0->1TestsDirection
clk_slow_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
clk_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_slow_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
rst_main_ni Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
clk_lc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_lc_ni Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
clk_esc_i Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
rst_esc_ni Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
tl_i.d_ready Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.data_intg[6:0] Yes Yes T1,T5,T60 Yes T1,T5,T60 INPUT
tl_i.a_user.cmd_intg[6:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.instr_type[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_user.rsvd[4:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_data[31:0] Yes Yes T1,T5,T60 Yes T1,T5,T60 INPUT
tl_i.a_mask[3:0] Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
tl_i.a_address[6:0] Yes Yes *T72,*T73,*T74 Yes T72,T73,T74 INPUT
tl_i.a_address[21:7] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[22] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[29:23] Unreachable Unreachable Unreachable INPUT
tl_i.a_address[30] Yes Yes *T1,*T2,*T3 Yes T1,T2,T3 INPUT
tl_i.a_address[31] Unreachable Unreachable Unreachable INPUT
tl_i.a_source[5:0] Yes Yes *T20,*T66,*T67 Yes T20,T66,T67 INPUT
tl_i.a_source[7:6] Unreachable Unreachable Unreachable INPUT
tl_i.a_size[1:0] Yes Yes T72,T73,T74 Yes T72,T73,T74 INPUT
tl_i.a_param[2:0] Unreachable Unreachable Unreachable INPUT
tl_i.a_opcode[2:0] Yes Yes T20,T66,T67 Yes T20,T66,T67 INPUT
tl_i.a_valid Yes Yes T1,T5,T60 Yes T1,T5,T60 INPUT
tl_o.a_ready Yes Yes T1,T5,T60 Yes T1,T5,T60 OUTPUT
tl_o.d_error Yes Yes T72,T75,T105 Yes T72,T75,T105 OUTPUT
tl_o.d_user.data_intg[6:0] Yes Yes T1,T5,T60 Yes T1,T5,T60 OUTPUT
tl_o.d_user.rsp_intg[6:0] Yes Yes T1,T5,T60 Yes T1,T5,T60 OUTPUT
tl_o.d_data[31:0] Yes Yes T1,T5,T60 Yes T1,T5,T60 OUTPUT
tl_o.d_sink Yes Yes T72,T75,T105 Yes T72,T74,T75 OUTPUT
tl_o.d_source[5:0] Yes Yes *T20,*T72,*T75 Yes T20,T72,T74 OUTPUT
tl_o.d_source[7:6] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_size[1:0] Yes Yes T72,T74,T75 Yes T72,T74,T75 OUTPUT
tl_o.d_param[2:0] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_opcode[0] Yes Yes *T1,*T5,*T60 Yes T1,T5,T60 OUTPUT
tl_o.d_opcode[2:1] Unreachable Unreachable Unreachable OUTPUT
tl_o.d_valid Yes Yes T1,T5,T60 Yes T1,T5,T60 OUTPUT
alert_rx_i[0].ack_n Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
alert_rx_i[0].ack_p Yes Yes T60,T55,T226 Yes T60,T55,T226 INPUT
alert_rx_i[0].ping_n Yes Yes T116,T76,T77 Yes T116,T76,T77 INPUT
alert_rx_i[0].ping_p Yes Yes T116,T76,T77 Yes T116,T76,T77 INPUT
alert_tx_o[0].alert_n Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
alert_tx_o[0].alert_p Yes Yes T60,T55,T226 Yes T60,T55,T226 OUTPUT
pwr_ast_i.main_pok Yes Yes T4,T5,T6 Yes T1,T2,T3 INPUT
pwr_ast_i.usb_clk_val Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
pwr_ast_i.io_clk_val Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
pwr_ast_i.core_clk_val Yes Yes T1,T4,T5 Yes T1,T2,T3 INPUT
pwr_ast_i.slow_clk_val Yes Yes T149,T150,T151 Yes T1,T2,T3 INPUT
pwr_ast_o.usb_clk_en Yes Yes T1,T4,T5 Yes T1,T2,T3 OUTPUT
pwr_ast_o.io_clk_en Yes Yes T1,T4,T5 Yes T1,T2,T3 OUTPUT
pwr_ast_o.core_clk_en Yes Yes T1,T4,T5 Yes T1,T2,T3 OUTPUT
pwr_ast_o.slow_clk_en Unreachable Unreachable Unreachable OUTPUT
pwr_ast_o.pwr_clamp Yes Yes T1,T2,T3 Yes T4,T5,T6 OUTPUT
pwr_ast_o.pwr_clamp_env Yes Yes T1,T2,T3 Yes T4,T5,T6 OUTPUT
pwr_ast_o.main_pd_n Yes Yes T5,T118,T119 Yes T5,T118,T119 OUTPUT
pwr_rst_i.rst_sys_src_n[1:0] Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
pwr_rst_i.rst_lc_src_n[1:0] Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
pwr_rst_o.reset_cause[1:0] Yes Yes T1,T2,T3 Yes T1,T34,T4 OUTPUT
pwr_rst_o.rstreqs[4:0] Yes Yes T5,T60,T118 Yes T5,T60,T118 OUTPUT
pwr_rst_o.rst_sys_req[1:0] Yes Yes T1,T2,T3 Yes T34,T4,T5 OUTPUT
pwr_rst_o.rst_lc_req[1:0] Yes Yes T1,T2,T3 Yes T34,T4,T5 OUTPUT
pwr_clk_o.usb_ip_clk_en Yes Yes T1,T34,T4 Yes T1,T2,T3 OUTPUT
pwr_clk_o.io_ip_clk_en Yes Yes T1,T34,T4 Yes T1,T2,T3 OUTPUT
pwr_clk_o.main_ip_clk_en Yes Yes T1,T34,T4 Yes T1,T2,T3 OUTPUT
pwr_clk_i.usb_status Yes Yes T1,T34,T4 Yes T1,T2,T3 INPUT
pwr_clk_i.io_status Yes Yes T1,T34,T4 Yes T1,T2,T3 INPUT
pwr_clk_i.main_status Yes Yes T1,T34,T4 Yes T1,T2,T3 INPUT
pwr_otp_i.otp_idle Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
pwr_otp_i.otp_done Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
pwr_otp_o.otp_init Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_lc_i.lc_idle Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
pwr_lc_i.lc_done Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
pwr_lc_o.lc_init Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
pwr_flash_i.flash_idle Yes Yes T34,T108,T58 Yes T34,T108,T58 INPUT
pwr_cpu_i.core_sleeping Yes Yes T1,T2,T3 Yes T1,T2,T3 INPUT
fetch_en_o[3:0] Yes Yes T1,T34,T4 Yes T1,T2,T3 OUTPUT
lc_hw_debug_en_i[3:0] Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
lc_dft_en_i[3:0] Yes Yes T34,T4,T5 Yes T1,T2,T3 INPUT
wakeups_i[5:0] Yes Yes T5,T60,T118 Yes T5,T60,T118 INPUT
rstreqs_i[1:0] Yes Yes T5,T60,T118 Yes T5,T60,T118 INPUT
ndmreset_req_i Yes Yes T47,T193,T194 Yes T47,T193,T194 INPUT
strap_o Yes Yes T1,T2,T3 Yes T1,T2,T3 OUTPUT
low_power_o Yes Yes T1,T2,T3 Yes T1,T4,T5 OUTPUT
rom_ctrl_i.good[3:0] Yes Yes T1,T2,T3 Yes T34,T4,T5 INPUT
rom_ctrl_i.done[3:0] Yes Yes T1,T2,T3 Yes T34,T4,T5 INPUT
sw_rst_req_i[3:0] Yes Yes T34,T60,T133 Yes T34,T60,T133 INPUT
esc_rst_tx_i.esc_n Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
esc_rst_tx_i.esc_p Yes Yes T60,T61,T62 Yes T60,T61,T62 INPUT
esc_rst_rx_o.resp_n Yes Yes T60,T61,T62 Yes T60,T61,T62 OUTPUT
esc_rst_rx_o.resp_p Yes Yes T60,T61,T62 Yes T60,T61,T62 OUTPUT
intr_wakeup_o Yes Yes T1,T284,T155 Yes T1,T284,T155 OUTPUT

*Tests covering at least one bit in the range
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