CHIP Simulation Results

Sunday March 03 2024 20:02:47 UTC

GitHub Revision: 0cdf265eaa

Branch: os_regression

Testplan

Simulator: VCS

Build randomization enabled with --build-seed 82530437672810453765703374940713112405319051694331588453064008042331386550559

Test Results

Stage	Name	Tests	Max Job Runtime	Simulated Time	Passing	Total	Pass Rate
V1	chip_sw_example_tests	chip_sw_example_flash	5.164m	3.153ms	3	3	100.00
		chip_sw_example_rom	1.969m	2.865ms	3	3	100.00
		chip_sw_example_manufacturer	4.606m	2.708ms	3	3	100.00
		chip_sw_example_concurrency	4.484m	3.089ms	3	3	100.00
		chip_sw_uart_smoketest_signed	35.541m	9.145ms	3	3	100.00
V1	csr_hw_reset	chip_csr_hw_reset	6.526m	6.778ms	5	5	100.00
V1	csr_rw	chip_csr_rw	11.429m	6.179ms	20	20	100.00
V1	csr_bit_bash	chip_csr_bit_bash	17.784m	11.024ms	5	5	100.00
V1	csr_aliasing	chip_csr_aliasing	2.915h	69.091ms	4	5	80.00
V1	csr_mem_rw_with_rand_reset	chip_csr_mem_rw_with_rand_reset	1.905m	2.405ms	0	20	0.00
V1	regwen_csr_and_corresponding_lockable_csr	chip_csr_aliasing	2.915h	69.091ms	4	5	80.00
		chip_csr_rw	11.429m	6.179ms	20	20	100.00
V1	xbar_smoke	xbar_smoke	10.670s	264.613us	100	100	100.00
V1	chip_sw_gpio_out	chip_sw_gpio	7.591m	4.044ms	3	3	100.00
V1	chip_sw_gpio_in	chip_sw_gpio	7.591m	4.044ms	3	3	100.00
V1	chip_sw_gpio_irq	chip_sw_gpio	7.591m	4.044ms	3	3	100.00
V1	chip_sw_uart_tx_rx	chip_sw_uart_tx_rx	18.715m	6.432ms	5	5	100.00
V1	chip_sw_uart_rx_overflow	chip_sw_uart_tx_rx	18.715m	6.432ms	5	5	100.00
		chip_sw_uart_tx_rx_idx1	17.787m	5.969ms	5	5	100.00
		chip_sw_uart_tx_rx_idx2	18.811m	5.130ms	5	5	100.00
		chip_sw_uart_tx_rx_idx3	17.697m	4.963ms	5	5	100.00
V1	chip_sw_uart_baud_rate	chip_sw_uart_rand_baudrate	1.067h	23.210ms	20	20	100.00
V1	chip_sw_uart_tx_rx_alt_clk_freq	chip_sw_uart_tx_rx_alt_clk_freq	1.306h	23.700ms	5	5	100.00
		chip_sw_uart_tx_rx_alt_clk_freq_low_speed	47.048m	23.078ms	5	5	100.00
V1		TOTAL			202	223	90.58
V2	chip_pin_mux	chip_padctrl_attributes	4.976m	5.523ms	10	10	100.00
V2	chip_padctrl_attributes	chip_padctrl_attributes	4.976m	5.523ms	10	10	100.00
V2	chip_sw_sleep_pin_mio_dio_val	chip_sw_sleep_pin_mio_dio_val	5.142m	3.475ms	3	3	100.00
V2	chip_sw_sleep_pin_wake	chip_sw_sleep_pin_wake	6.089m	5.017ms	3	3	100.00
V2	chip_sw_sleep_pin_retention	chip_sw_sleep_pin_retention	5.309m	4.076ms	3	3	100.00
V2	chip_sw_tap_strap_sampling	chip_tap_straps_dev	15.132m	7.829ms	5	5	100.00
		chip_tap_straps_testunlock0	9.170m	6.106ms	5	5	100.00
		chip_tap_straps_rma	14.272m	8.189ms	5	5	100.00
		chip_tap_straps_prod	25.787m	12.374ms	5	5	100.00
V2	chip_sw_pattgen_ios	chip_sw_pattgen_ios	4.832m	3.298ms	3	3	100.00
V2	chip_sw_sleep_pwm_pulses	chip_sw_sleep_pwm_pulses	24.266m	9.411ms	3	3	100.00
V2	chip_sw_data_integrity	chip_sw_data_integrity_escalation	16.177m	5.134ms	6	6	100.00
V2	chip_sw_instruction_integrity	chip_sw_data_integrity_escalation	16.177m	5.134ms	6	6	100.00
V2	chip_sw_ast_clk_outputs	chip_sw_ast_clk_outputs	22.024m	6.645ms	3	3	100.00
V2	chip_sw_ast_clk_rst_inputs	chip_sw_ast_clk_rst_inputs			0	3	0.00
V2	chip_sw_ast_sys_clk_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.377m	4.110ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.373m	5.611ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.319h	18.205ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.074m	3.686ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.724m	5.470ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.860m	3.292ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.698m	4.137ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.396m	2.906ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.506m	4.555ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.344m	3.118ms	3	3	100.00
V2	chip_sw_ast_usb_clk_calib	chip_sw_usb_ast_clk_calib	5.197m	2.946ms	1	1	100.00
V2	chip_sw_ast_alerts	chip_sw_sensor_ctrl_alert	15.898m	7.878ms	5	5	100.00
V2	chip_sw_sensor_ctrl_ast_alerts	chip_sw_sensor_ctrl_alert	15.898m	7.878ms	5	5	100.00
		chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.808m	5.928ms	3	3	100.00
V2	chip_sw_sensor_ctrl_ast_status	chip_sw_sensor_ctrl_status	5.202m	2.334ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup	8.808m	5.928ms	3	3	100.00
V2	chip_sw_smoketest	chip_sw_flash_scrambling_smoketest	4.451m	3.014ms	3	3	100.00
		chip_sw_aes_smoketest	5.283m	3.255ms	3	3	100.00
		chip_sw_aon_timer_smoketest	4.706m	3.704ms	3	3	100.00
		chip_sw_clkmgr_smoketest	4.863m	2.850ms	3	3	100.00
		chip_sw_csrng_smoketest	4.605m	2.542ms	3	3	100.00
		chip_sw_entropy_src_smoketest	7.532m	3.445ms	3	3	100.00
		chip_sw_gpio_smoketest	5.200m	3.478ms	3	3	100.00
		chip_sw_hmac_smoketest	8.270m	3.306ms	3	3	100.00
		chip_sw_kmac_smoketest	5.897m	3.503ms	3	3	100.00
		chip_sw_otbn_smoketest	37.771m	8.646ms	3	3	100.00
		chip_sw_otp_ctrl_smoketest	5.679m	3.188ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.673m	4.609ms	3	3	100.00
		chip_sw_pwrmgr_usbdev_smoketest	7.292m	4.326ms	3	3	100.00
		chip_sw_rv_plic_smoketest	4.939m	2.283ms	3	3	100.00
		chip_sw_rv_timer_smoketest	5.126m	3.580ms	3	3	100.00
		chip_sw_rstmgr_smoketest	4.645m	2.726ms	3	3	100.00
		chip_sw_sram_ctrl_smoketest	4.713m	2.571ms	3	3	100.00
		chip_sw_uart_smoketest	4.388m	2.983ms	3	3	100.00
V2	chip_sw_rom_functests	rom_keymgr_functest	11.470m	4.860ms	3	3	100.00
V2	chip_sw_signed	chip_sw_uart_smoketest_signed	35.541m	9.145ms	3	3	100.00
V2	chip_sw_boot	chip_sw_uart_tx_rx_bootstrap	3.798h	78.153ms	3	3	100.00
V2	chip_sw_secure_boot	rom_e2e_smoke	38.181m	9.235ms	3	3	100.00
V2	chip_sw_rom_raw_unlock	rom_raw_unlock	37.829m	14.904ms	3	3	100.00
V2	chip_sw_power_idle_load	chip_sw_power_idle_load	12.725m	3.860ms	3	3	100.00
V2	chip_sw_power_sleep_load	chip_sw_power_sleep_load	11.504m	10.825ms	3	3	100.00
V2	chip_sw_exit_test_unlocked_bootstrap	chip_sw_exit_test_unlocked_bootstrap	2.997h	58.083ms	3	3	100.00
V2	chip_sw_inject_scramble_seed	chip_sw_inject_scramble_seed	3.573h	65.333ms	3	3	100.00
V2	tl_d_oob_addr_access	chip_tl_errors	8.241m	4.967ms	30	30	100.00
V2	tl_d_illegal_access	chip_tl_errors	8.241m	4.967ms	30	30	100.00
V2	tl_d_outstanding_access	chip_csr_aliasing	2.915h	69.091ms	4	5	80.00
		chip_same_csr_outstanding	1.245h	30.379ms	20	20	100.00
		chip_csr_hw_reset	6.526m	6.778ms	5	5	100.00
		chip_csr_rw	11.429m	6.179ms	20	20	100.00
V2	tl_d_partial_access	chip_csr_aliasing	2.915h	69.091ms	4	5	80.00
		chip_same_csr_outstanding	1.245h	30.379ms	20	20	100.00
		chip_csr_hw_reset	6.526m	6.778ms	5	5	100.00
		chip_csr_rw	11.429m	6.179ms	20	20	100.00
V2	xbar_base_random_sequence	xbar_random	1.535m	2.381ms	100	100	100.00
V2	xbar_random_delay	xbar_smoke_zero_delays	7.280s	64.772us	100	100	100.00
		xbar_smoke_large_delays	1.986m	10.962ms	100	100	100.00
		xbar_smoke_slow_rsp	2.159m	7.421ms	100	100	100.00
		xbar_random_zero_delays	55.400s	616.417us	100	100	100.00
		xbar_random_large_delays	23.408m	110.514ms	100	100	100.00
		xbar_random_slow_rsp	21.190m	71.792ms	100	100	100.00
V2	xbar_unmapped_address	xbar_unmapped_addr	1.086m	1.429ms	100	100	100.00
		xbar_error_and_unmapped_addr	57.510s	1.309ms	100	100	100.00
V2	xbar_error_cases	xbar_error_random	1.680m	2.628ms	100	100	100.00
		xbar_error_and_unmapped_addr	57.510s	1.309ms	100	100	100.00
V2	xbar_all_access_same_device	xbar_access_same_device	2.341m	3.436ms	100	100	100.00
		xbar_access_same_device_slow_rsp	51.434m	166.794ms	100	100	100.00
V2	xbar_all_hosts_use_same_source_id	xbar_same_source	1.506m	2.674ms	100	100	100.00
V2	xbar_stress_all	xbar_stress_all	15.091m	23.871ms	100	100	100.00
		xbar_stress_all_with_error	12.943m	20.615ms	100	100	100.00
V2	xbar_stress_with_reset	xbar_stress_all_with_rand_reset	20.373m	23.619ms	100	100	100.00
		xbar_stress_all_with_reset_error	14.899m	19.578ms	100	100	100.00
V2	rom_e2e_smoke	rom_e2e_smoke	38.181m	9.235ms	3	3	100.00
V2	rom_e2e_shutdown_output	rom_e2e_shutdown_output	55.193m	22.205ms	3	3	100.00
V2	rom_e2e_shutdown_exception_c	rom_e2e_shutdown_exception_c	35.150m	8.908ms	3	3	100.00
V2	rom_e2e_boot_policy_valid	rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0	28.070m	7.318ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_dev	35.262m	8.704ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod	32.527m	8.176ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_prod_end	31.848m	9.060ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_good_rma	36.104m	9.069ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0	28.360m	7.087ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_dev	38.710m	8.479ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod	34.930m	8.884ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_prod_end	32.774m	8.597ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_good_b_bad_rma	34.628m	9.580ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0	43.291m	9.722ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_dev	48.955m	11.736ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod	48.203m	12.364ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_prod_end	54.362m	11.908ms	1	1	100.00
		rom_e2e_boot_policy_valid_a_bad_b_good_rma	1.021h	12.562ms	1	1	100.00
V2	rom_e2e_sigverify_always	rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0	41.380m	10.533ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_dev	52.886m	12.464ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod	53.205m	11.989ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_prod_end	57.793m	11.543ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_bad_rma	54.167m	12.122ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0	30.968m	6.915ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_dev	39.402m	8.264ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod	33.101m	7.931ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_prod_end	32.706m	9.200ms	1	1	100.00
		rom_e2e_sigverify_always_a_bad_b_nothing_rma	32.926m	8.664ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0	28.882m	7.824ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_dev	30.172m	8.599ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod	36.876m	8.798ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_prod_end	33.268m	8.300ms	1	1	100.00
		rom_e2e_sigverify_always_a_nothing_b_bad_rma	33.404m	9.116ms	1	1	100.00
V2	rom_e2e_sigverify_mod_exp	rom_e2e_sigverify_mod_exp_test_unlocked0_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_test_unlocked0_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_dev_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_prod_end_sw			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_otbn			0	3	0.00
		rom_e2e_sigverify_mod_exp_rma_sw			0	3	0.00
V2	rom_e2e_asm_init	rom_e2e_asm_init_test_unlocked0	27.771m	6.312ms	3	3	100.00
		rom_e2e_asm_init_dev	38.172m	9.300ms	3	3	100.00
		rom_e2e_asm_init_prod	37.229m	9.166ms	3	3	100.00
		rom_e2e_asm_init_prod_end	39.479m	9.097ms	3	3	100.00
		rom_e2e_asm_init_rma	35.809m	8.546ms	3	3	100.00
V2	rom_e2e_keymgr_init	rom_e2e_keymgr_init_rom_ext_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_no_meas			0	3	0.00
		rom_e2e_keymgr_init_rom_ext_invalid_meas			0	3	0.00
V2	rom_e2e_static_critical	rom_e2e_static_critical	42.535m	10.927ms	3	3	100.00
V2	chip_sw_aes_enc	chip_sw_aes_enc	6.907m	3.357ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.074m	3.686ms	3	3	100.00
V2	chip_sw_aes_multi_block	chip_sw_aes_multi_block			0	0	--
V2	chip_sw_aes_interrupt_encryption	chip_sw_aes_interrupt_encryption			0	0	--
V2	chip_sw_aes_entropy	chip_sw_aes_entropy	5.261m	3.189ms	3	3	100.00
V2	chip_sw_aes_prng_reseed	chip_sw_aes_prng_reseed			0	0	--
V2	chip_sw_aes_force_prng_reseed	chip_sw_aes_force_prng_reseed			0	0	--
V2	chip_sw_aes_idle	chip_sw_aes_idle	5.582m	2.901ms	3	3	100.00
V2	chip_sw_aes_sideload	chip_sw_keymgr_sideload_aes	9.274m	5.615ms	3	3	100.00
V2	chip_sw_adc_ctrl_debug_cable_irq	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.280m	17.642ms	3	3	100.00
V2	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.280m	17.642ms	3	3	100.00
V2	chip_sw_aon_timer_wakeup_irq	chip_sw_aon_timer_irq	8.678m	4.207ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wakeup	chip_sw_pwrmgr_smoketest	9.673m	4.609ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bark_irq	chip_sw_aon_timer_irq	8.678m	4.207ms	3	3	100.00
V2	chip_sw_aon_timer_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.977m	9.157ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_bite_reset	chip_sw_aon_timer_wdog_bite_reset	15.977m	9.157ms	3	3	100.00
V2	chip_sw_aon_timer_sleep_wdog_sleep_pause	chip_sw_aon_timer_sleep_wdog_sleep_pause	10.441m	7.233ms	5	5	100.00
V2	chip_sw_aon_timer_wdog_lc_escalate	chip_sw_aon_timer_wdog_lc_escalate	13.318m	5.087ms	3	3	100.00
V2	chip_sw_clkmgr_idle_trans	chip_sw_otbn_randomness	18.331m	6.030ms	3	3	100.00
		chip_sw_aes_idle	5.582m	2.901ms	3	3	100.00
		chip_sw_hmac_enc_idle	4.673m	2.544ms	3	3	100.00
		chip_sw_kmac_idle	4.538m	3.534ms	3	3	100.00
V2	chip_sw_clkmgr_off_trans	chip_sw_clkmgr_off_aes_trans	7.955m	3.818ms	3	3	100.00
		chip_sw_clkmgr_off_hmac_trans	9.179m	4.953ms	3	3	100.00
		chip_sw_clkmgr_off_kmac_trans	11.014m	5.407ms	3	3	100.00
		chip_sw_clkmgr_off_otbn_trans	7.866m	3.908ms	3	3	100.00
V2	chip_sw_clkmgr_off_peri	chip_sw_clkmgr_off_peri	27.072m	13.165ms	3	3	100.00
V2	chip_sw_clkmgr_div	chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.702m	3.631ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.354m	4.304ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.753m	4.394ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.970m	4.645ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.492m	4.191ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.147m	4.943ms	3	3	100.00
		chip_sw_ast_clk_outputs	22.024m	6.645ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_lc	chip_sw_clkmgr_external_clk_src_for_lc	18.672m	10.750ms	3	3	100.00
V2	chip_sw_clkmgr_external_clk_src_for_sw	chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.753m	4.394ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.970m	4.645ms	3	3	100.00
V2	chip_sw_clkmgr_jitter	chip_sw_flash_ctrl_ops_jitter_en	12.377m	4.110ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.373m	5.611ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en	1.319h	18.205ms	3	3	100.00
		chip_sw_aes_enc_jitter_en	6.074m	3.686ms	3	3	100.00
		chip_sw_edn_entropy_reqs_jitter	20.724m	5.470ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.860m	3.292ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.698m	4.137ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.396m	2.906ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.506m	4.555ms	3	3	100.00
		chip_sw_clkmgr_jitter	3.344m	3.118ms	3	3	100.00
V2	chip_sw_clkmgr_extended_range	chip_sw_clkmgr_jitter_reduced_freq	4.395m	3.333ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en_reduced_freq	12.887m	5.299ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en_reduced_freq	21.532m	7.409ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq	1.174h	25.430ms	3	3	100.00
		chip_sw_aes_enc_jitter_en_reduced_freq	6.392m	3.605ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en_reduced_freq	5.693m	3.154ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en_reduced_freq	8.776m	4.815ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en_reduced_freq	6.576m	3.867ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq	10.506m	5.583ms	3	3	100.00
		chip_sw_flash_init_reduced_freq	38.408m	22.542ms	3	3	100.00
		chip_sw_csrng_edn_concurrency_reduced_freq	52.098m	16.047ms	3	3	100.00
V2	chip_sw_clkmgr_deep_sleep_frequency	chip_sw_ast_clk_outputs	22.024m	6.645ms	3	3	100.00
V2	chip_sw_clkmgr_sleep_frequency	chip_sw_clkmgr_sleep_frequency	11.991m	4.449ms	3	3	100.00
V2	chip_sw_clkmgr_reset_frequency	chip_sw_clkmgr_reset_frequency	7.893m	4.067ms	3	3	100.00
V2	chip_sw_clkmgr_escalation_reset	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
V2	chip_sw_clkmgr_alert_handler_clock_enables	chip_sw_alert_handler_lpg_clkoff	32.337m	9.421ms	3	3	100.00
V2	chip_sw_csrng_edn_cmd	chip_sw_entropy_src_csrng	31.801m	7.474ms	3	3	100.00
V2	chip_sw_csrng_fuse_en_sw_app_read	chip_sw_csrng_fuse_en_sw_app_read_test	8.482m	10.010ms	0	3	0.00
V2	chip_sw_csrng_lc_hw_debug_en	chip_sw_csrng_lc_hw_debug_en_test	22.566m	20.010ms	0	3	0.00
V2	chip_sw_csrng_known_answer_tests	chip_sw_csrng_kat_test	3.974m	2.374ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.328m	7.157ms	3	3	100.00
		chip_sw_sysrst_ctrl_reset	27.452m	21.156ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_inputs	chip_sw_sysrst_ctrl_inputs	5.019m	2.857ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_outputs	chip_sw_sysrst_ctrl_outputs	42.080s	10.180us	0	3	0.00
V2	chip_sw_sysrst_ctrl_in_irq	chip_sw_sysrst_ctrl_in_irq	10.364m	4.812ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_wakeup	chip_sw_sysrst_ctrl_reset	27.452m	21.156ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_sleep_reset	chip_sw_sysrst_ctrl_reset	27.452m	21.156ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ec_rst_l	chip_sw_sysrst_ctrl_ec_rst_l	56.387m	20.478ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_flash_wp_l	chip_sw_sysrst_ctrl_ec_rst_l	56.387m	20.478ms	3	3	100.00
V2	chip_sw_sysrst_ctrl_ulp_z3_wakeup	chip_sw_sysrst_ctrl_ulp_z3_wakeup	8.997m	6.466ms	3	3	100.00
		chip_sw_adc_ctrl_sleep_debug_cable_wakeup	10.280m	17.642ms	3	3	100.00
V2	chip_sw_edn_entropy_reqs	chip_sw_csrng_edn_concurrency	47.719m	12.080ms	3	3	100.00
		chip_sw_entropy_src_ast_rng_req	4.620m	3.032ms	3	3	100.00
		chip_sw_edn_entropy_reqs	20.113m	5.127ms	3	3	100.00
V2	chip_sw_entropy_src_ast_rng_req	chip_sw_entropy_src_ast_rng_req	4.620m	3.032ms	3	3	100.00
V2	chip_sw_entropy_src_csrng	chip_sw_entropy_src_csrng	31.801m	7.474ms	3	3	100.00
V2	chip_sw_entropy_src_known_answer_tests	chip_sw_entropy_src_kat_test	4.954m	3.226ms	3	3	100.00
V2	chip_sw_entropy_src_fw_observe_many_contiguous	chip_sw_entropy_src_fw_observe_many_contiguous			0	0	--
V2	chip_sw_entropy_src_fw_extract_and_insert	chip_sw_entropy_src_fw_extract_and_insert			0	0	--
V2	chip_sw_flash_init	chip_sw_flash_init	38.991m	24.998ms	3	3	100.00
V2	chip_sw_flash_host_access	chip_sw_flash_ctrl_access	20.772m	5.725ms	3	3	100.00
		chip_sw_flash_ctrl_access_jitter_en	19.373m	5.611ms	3	3	100.00
V2	chip_sw_flash_ctrl_ops	chip_sw_flash_ctrl_ops	14.066m	4.037ms	3	3	100.00
		chip_sw_flash_ctrl_ops_jitter_en	12.377m	4.110ms	3	3	100.00
V2	chip_sw_flash_rma_unlocked	chip_sw_flash_rma_unlocked	12.837m	10.010ms	0	3	0.00
V2	chip_sw_flash_scramble	chip_sw_flash_init	38.991m	24.998ms	3	3	100.00
V2	chip_sw_flash_idle_low_power	chip_sw_flash_ctrl_idle_low_power	6.533m	3.316ms	3	3	100.00
V2	chip_sw_flash_keymgr_seeds	chip_sw_keymgr_key_derivation	10.481m	4.125ms	3	3	100.00
V2	chip_sw_flash_lc_creator_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	7.589m	4.078ms	3	3	100.00
V2	chip_sw_flash_creator_seed_wipe_on_rma	chip_sw_flash_rma_unlocked	12.837m	10.010ms	0	3	0.00
V2	chip_sw_flash_lc_owner_seed_sw_rw_en	chip_sw_flash_ctrl_lc_rw_en	7.589m	4.078ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_rd_en	chip_sw_flash_ctrl_lc_rw_en	7.589m	4.078ms	3	3	100.00
V2	chip_sw_flash_lc_iso_part_sw_wr_en	chip_sw_flash_ctrl_lc_rw_en	7.589m	4.078ms	3	3	100.00
V2	chip_sw_flash_lc_seed_hw_rd_en	chip_sw_flash_ctrl_lc_rw_en	7.589m	4.078ms	3	3	100.00
V2	chip_sw_flash_lc_escalate_en	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
V2	chip_sw_flash_prim_tl_access	chip_prim_tl_access	6.608m	9.683ms	3	3	100.00
V2	chip_sw_flash_ctrl_clock_freqs	chip_sw_flash_ctrl_clock_freqs	18.425m	5.695ms	3	3	100.00
V2	chip_sw_flash_ctrl_escalation_reset	chip_sw_flash_crash_alert	13.260m	6.385ms	3	3	100.00
V2	chip_sw_flash_ctrl_write_clear	chip_sw_flash_crash_alert	13.260m	6.385ms	3	3	100.00
V2	chip_sw_hmac_enc	chip_sw_hmac_enc	8.087m	3.494ms	3	3	100.00
		chip_sw_hmac_enc_jitter_en	5.860m	3.292ms	3	3	100.00
V2	chip_sw_hmac_idle	chip_sw_hmac_enc_idle	4.673m	2.544ms	3	3	100.00
V2	chip_sw_i2c_host_tx_rx	chip_sw_i2c_host_tx_rx	16.101m	5.201ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx1	15.470m	4.744ms	3	3	100.00
		chip_sw_i2c_host_tx_rx_idx2	14.948m	4.870ms	3	3	100.00
V2	chip_sw_i2c_device_tx_rx	chip_sw_i2c_device_tx_rx	9.884m	4.185ms	3	3	100.00
V2	chip_sw_keymgr_key_derivation	chip_sw_keymgr_key_derivation	10.481m	4.125ms	3	3	100.00
		chip_sw_keymgr_key_derivation_jitter_en	9.698m	4.137ms	3	3	100.00
V2	chip_sw_keymgr_sideload_kmac	chip_sw_keymgr_sideload_kmac	9.038m	5.607ms	3	3	100.00
V2	chip_sw_keymgr_sideload_aes	chip_sw_keymgr_sideload_aes	9.274m	5.615ms	3	3	100.00
V2	chip_sw_keymgr_sideload_otbn	chip_sw_keymgr_sideload_otbn	1.155h	15.765ms	3	3	100.00
V2	chip_sw_kmac_enc	chip_sw_kmac_mode_cshake	4.973m	2.884ms	3	3	100.00
		chip_sw_kmac_mode_kmac	5.833m	3.188ms	3	3	100.00
		chip_sw_kmac_mode_kmac_jitter_en	5.396m	2.906ms	3	3	100.00
V2	chip_sw_kmac_app_keymgr	chip_sw_keymgr_key_derivation	10.481m	4.125ms	3	3	100.00
V2	chip_sw_kmac_app_lc	chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
V2	chip_sw_kmac_app_rom	chip_sw_kmac_app_rom	4.587m	3.004ms	3	3	100.00
V2	chip_sw_kmac_entropy	chip_sw_kmac_entropy	5.288m	3.203ms	3	3	100.00
V2	chip_sw_kmac_idle	chip_sw_kmac_idle	4.538m	3.534ms	3	3	100.00
V2	chip_sw_lc_ctrl_alert_handler_escalation	chip_sw_alert_handler_escalation	10.113m	4.545ms	3	3	100.00
V2	chip_sw_lc_ctrl_jtag_access	chip_tap_straps_dev	15.132m	7.829ms	5	5	100.00
		chip_tap_straps_rma	14.272m	8.189ms	5	5	100.00
		chip_tap_straps_prod	25.787m	12.374ms	5	5	100.00
V2	chip_sw_lc_ctrl_otp_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.132m	3.455ms	3	3	100.00
V2	chip_sw_lc_ctrl_init	chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
V2	chip_sw_lc_ctrl_transitions	chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
V2	chip_sw_lc_ctrl_kmac_req	chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
V2	chip_sw_lc_ctrl_key_div	chip_sw_keymgr_key_derivation_prod	10.489m	4.828ms	3	3	100.00
V2	chip_sw_lc_ctrl_broadcast	chip_sw_flash_ctrl_lc_rw_en	7.589m	4.078ms	3	3	100.00
		chip_sw_flash_rma_unlocked	12.837m	10.010ms	0	3	0.00
		chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.574m	4.452ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.119m	7.226ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	21.946m	6.718ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.976m	7.636ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
		chip_sw_keymgr_key_derivation	10.481m	4.125ms	3	3	100.00
		chip_sw_rom_ctrl_integrity_check	8.725m	9.192ms	3	3	100.00
		chip_sw_sram_ctrl_execution_main	8.885m	10.021ms	0	3	0.00
		chip_prim_tl_access	6.608m	9.683ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_lc	18.672m	10.750ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0	13.702m	3.631ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0	11.354m	4.304ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_dev	10.753m	4.394ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_dev	13.970m	4.645ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_fast_rma	12.492m	4.191ms	3	3	100.00
		chip_sw_clkmgr_external_clk_src_for_sw_slow_rma	14.147m	4.943ms	3	3	100.00
		chip_tap_straps_dev	15.132m	7.829ms	5	5	100.00
		chip_tap_straps_rma	14.272m	8.189ms	5	5	100.00
		chip_tap_straps_prod	25.787m	12.374ms	5	5	100.00
		chip_rv_dm_lc_disabled	6.580m	13.666ms	3	3	100.00
V2	chip_lc_scrap	chip_sw_lc_ctrl_rma_to_scrap	2.564m	3.612ms	1	1	100.00
		chip_sw_lc_ctrl_raw_to_scrap	2.568m	2.923ms	1	1	100.00
		chip_sw_lc_ctrl_test_locked0_to_scrap	2.469m	3.966ms	1	1	100.00
		chip_sw_lc_ctrl_rand_to_scrap	4.152m	3.066ms	3	3	100.00
V2	chip_lc_test_locked	chip_sw_lc_walkthrough_testunlocks	37.566m	21.847ms	3	3	100.00
		chip_rv_dm_lc_disabled	6.580m	13.666ms	3	3	100.00
V2	chip_sw_lc_walkthrough	chip_sw_lc_walkthrough_dev	1.602h	47.068ms	3	3	100.00
		chip_sw_lc_walkthrough_prod	1.659h	47.771ms	3	3	100.00
		chip_sw_lc_walkthrough_prodend	19.890m	10.504ms	3	3	100.00
		chip_sw_lc_walkthrough_rma	1.646h	47.416ms	3	3	100.00
		chip_sw_lc_walkthrough_testunlocks	37.566m	21.847ms	3	3	100.00
V2	chip_sw_lc_ctrl_volatile_raw_unlock	chip_sw_lc_ctrl_volatile_raw_unlock	2.229m	2.722ms	3	3	100.00
		chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz	2.198m	2.699ms	3	3	100.00
		rom_volatile_raw_unlock	1.738m	2.824ms	3	3	100.00
V2	chip_otp_ctrl_init	chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
V2	chip_sw_otp_ctrl_keys	chip_sw_flash_init	38.991m	24.998ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.571m	4.205ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.481m	4.125ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.614m	5.402ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.557m	2.404ms	3	3	100.00
V2	chip_sw_otp_ctrl_entropy	chip_sw_flash_init	38.991m	24.998ms	3	3	100.00
		chip_sw_otbn_mem_scramble	10.571m	4.205ms	3	3	100.00
		chip_sw_keymgr_key_derivation	10.481m	4.125ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access	11.614m	5.402ms	3	3	100.00
		chip_sw_rv_core_ibex_icache_invalidate	4.557m	2.404ms	3	3	100.00
V2	chip_sw_otp_ctrl_program	chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
V2	chip_sw_otp_ctrl_program_error	chip_sw_lc_ctrl_program_error	24.385m	14.589ms	0	3	0.00
V2	chip_sw_otp_ctrl_hw_cfg0	chip_sw_lc_ctrl_otp_hw_cfg0	5.132m	3.455ms	3	3	100.00
V2	chip_sw_otp_ctrl_lc_signals	chip_sw_otp_ctrl_lc_signals_test_unlocked0	12.574m	4.452ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_dev	26.119m	7.226ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_prod	21.946m	6.718ms	3	3	100.00
		chip_sw_otp_ctrl_lc_signals_rma	23.976m	7.636ms	3	3	100.00
		chip_sw_lc_ctrl_transition	18.621m	10.115ms	15	15	100.00
		chip_prim_tl_access	6.608m	9.683ms	3	3	100.00
V2	chip_sw_otp_prim_tl_access	chip_prim_tl_access	6.608m	9.683ms	3	3	100.00
V2	chip_sw_pwrmgr_external_full_reset	chip_sw_pwrmgr_full_aon_reset	7.395m	8.902ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_wake_ups	chip_sw_pwrmgr_random_sleep_all_wake_ups	23.837m	21.177ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_wake_ups	chip_sw_pwrmgr_normal_sleep_all_wake_ups	7.385m	7.125ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_por_reset	chip_sw_pwrmgr_deep_sleep_por_reset	13.181m	9.452ms	1	3	33.33
V2	chip_sw_pwrmgr_normal_sleep_por_reset	chip_sw_pwrmgr_normal_sleep_por_reset	13.318m	17.566ms	2	3	66.67
V2	chip_sw_pwrmgr_deep_sleep_all_wake_ups	chip_sw_pwrmgr_deep_sleep_all_wake_ups	33.817m	20.598ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	chip_sw_pwrmgr_deep_sleep_all_reset_reqs	25.377m	15.794ms	3	3	100.00
		chip_sw_aon_timer_wdog_bite_reset	15.977m	9.157ms	3	3	100.00
V2	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	chip_sw_pwrmgr_normal_sleep_all_reset_reqs	25.922m	9.632ms	3	3	100.00
V2	chip_sw_pwrmgr_wdog_reset	chip_sw_pwrmgr_wdog_reset	11.384m	5.106ms	3	3	100.00
V2	chip_sw_pwrmgr_aon_power_glitch_reset	chip_sw_pwrmgr_full_aon_reset	7.395m	8.902ms	3	3	100.00
V2	chip_sw_pwrmgr_main_power_glitch_reset	chip_sw_pwrmgr_main_power_glitch_reset	9.503m	4.084ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_power_glitch_reset	chip_sw_pwrmgr_random_sleep_power_glitch_reset	54.536m	41.462ms	3	3	100.00
V2	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	chip_sw_pwrmgr_deep_sleep_power_glitch_reset	9.937m	6.153ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_power_glitch_reset	chip_sw_pwrmgr_sleep_power_glitch_reset	10.427m	4.749ms	3	3	100.00
V2	chip_sw_pwrmgr_random_sleep_all_reset_reqs	chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.330m	20.795ms	3	3	100.00
V2	chip_sw_pwrmgr_sysrst_ctrl_reset	chip_sw_pwrmgr_sysrst_ctrl_reset	17.328m	7.157ms	3	3	100.00
		chip_sw_pwrmgr_all_reset_reqs	31.099m	13.819ms	3	3	100.00
V2	chip_sw_pwrmgr_b2b_sleep_reset_req	chip_sw_pwrmgr_b2b_sleep_reset_req	46.040m	25.571ms	3	3	100.00
V2	chip_sw_pwrmgr_sleep_disabled	chip_sw_pwrmgr_sleep_disabled	4.662m	3.284ms	3	3	100.00
V2	chip_sw_pwrmgr_escalation_reset	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
V2	chip_sw_rom_access	chip_sw_rom_ctrl_integrity_check	8.725m	9.192ms	3	3	100.00
V2	chip_sw_rom_ctrl_integrity_check	chip_sw_rom_ctrl_integrity_check	8.725m	9.192ms	3	3	100.00
V2	chip_sw_rstmgr_non_sys_reset_info	chip_sw_pwrmgr_all_reset_reqs	31.099m	13.819ms	3	3	100.00
		chip_sw_pwrmgr_random_sleep_all_reset_reqs	45.330m	20.795ms	3	3	100.00
		chip_sw_pwrmgr_wdog_reset	11.384m	5.106ms	3	3	100.00
		chip_sw_pwrmgr_smoketest	9.673m	4.609ms	3	3	100.00
V2	chip_sw_rstmgr_sys_reset_info	chip_rv_dm_ndm_reset_req	7.599m	3.940ms	3	3	100.00
V2	chip_sw_rstmgr_cpu_info	chip_sw_rstmgr_cpu_info	11.951m	5.931ms	3	3	100.00
V2	chip_sw_rstmgr_sw_req_reset	chip_sw_rstmgr_sw_req	8.184m	5.177ms	3	3	100.00
V2	chip_sw_rstmgr_alert_info	chip_sw_rstmgr_alert_info	28.995m	13.515ms	3	3	100.00
V2	chip_sw_rstmgr_sw_rst	chip_sw_rstmgr_sw_rst	4.456m	3.494ms	3	3	100.00
V2	chip_sw_rstmgr_escalation_reset	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
V2	chip_sw_rstmgr_alert_handler_reset_enables	chip_sw_alert_handler_lpg_reset_toggle	34.018m	8.190ms	3	3	100.00
V2	chip_sw_plic_all_irqs	chip_plic_all_irqs_0	22.652m	6.091ms	3	3	100.00
		chip_plic_all_irqs_10	10.302m	3.906ms	3	3	100.00
		chip_plic_all_irqs_20	13.450m	5.061ms	3	3	100.00
V2	chip_sw_plic_sw_irq	chip_sw_plic_sw_irq	5.366m	3.450ms	3	3	100.00
V2	chip_sw_timer	chip_sw_rv_timer_irq	5.030m	2.581ms	3	3	100.00
V2	chip_sw_spi_device_flash_mode	rom_e2e_smoke	38.181m	9.235ms	3	3	100.00
V2	chip_sw_spi_device_pass_through	chip_sw_spi_device_pass_through	14.035m	7.705ms	3	3	100.00
V2	chip_sw_spi_device_pass_through_collision	chip_sw_spi_device_pass_through_collision	12.017m	4.551ms	3	3	100.00
V2	chip_sw_spi_device_tpm	chip_sw_spi_device_tpm	6.434m	3.510ms	3	3	100.00
V2	chip_sw_spi_host_tx_rx	chip_sw_spi_host_tx_rx	5.530m	3.000ms	3	3	100.00
V2	chip_sw_sram_scrambled_access	chip_sw_sram_ctrl_scrambled_access	11.614m	5.402ms	3	3	100.00
		chip_sw_sram_ctrl_scrambled_access_jitter_en	10.506m	4.555ms	3	3	100.00
V2	chip_sw_sleep_sram_ret_contents	chip_sw_sleep_sram_ret_contents_no_scramble	14.231m	8.121ms	3	3	100.00
		chip_sw_sleep_sram_ret_contents_scramble	12.125m	6.738ms	3	3	100.00
V2	chip_sw_sram_execution	chip_sw_sram_ctrl_execution_main	8.885m	10.021ms	0	3	0.00
V2	chip_sw_sram_lc_escalation	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
		chip_sw_data_integrity_escalation	16.177m	5.134ms	6	6	100.00
V2	chip_sw_usbdev_mem	chip_sw_usbdev_mem			0	0	--
V2	chip_sw_usbdev_vbus	chip_sw_usbdev_vbus	3.478m	2.671ms	1	1	100.00
V2	chip_sw_usbdev_pullup	chip_sw_usbdev_pullup	5.257m	3.608ms	1	1	100.00
V2	chip_sw_usbdev_aon_pullup	chip_sw_usbdev_aon_pullup	8.018m	3.908ms	1	1	100.00
V2	chip_sw_usbdev_sof	chip_sw_usbdev_sof			0	0	--
V2	chip_sw_usbdev_setup_rx	chip_sw_usbdev_setuprx	7.743m	4.257ms	1	1	100.00
V2	chip_sw_usbdev_config_host	chip_sw_usbdev_config_host	28.460m	8.571ms	1	1	100.00
V2	chip_sw_usbdev_pincfg	chip_sw_usbdev_pincfg	1.929h	30.942ms	1	1	100.00
V2	chip_sw_usbdev_tx_rx	chip_sw_usbdev_dpi	49.117m	11.890ms	1	1	100.00
V2	chip_sw_alert_handler_alerts	chip_sw_alert_test	6.126m	2.964ms	3	3	100.00
V2	chip_sw_alert_handler_escalations	chip_sw_alert_handler_escalation	10.113m	4.545ms	3	3	100.00
V2	chip_sw_alert_handler_escalation_nmi_reset	chip_sw_alert_handler_escalation_nmi_reset			0	0	--
V2	chip_sw_alert_handler_escalation_methods	chip_sw_alert_handler_escalation_methods			0	0	--
V2	chip_sw_all_escalation_resets	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
V2	chip_sw_alert_handler_irqs	chip_plic_all_irqs			0	0	--
V2	chip_sw_alert_handler_entropy	chip_sw_alert_handler_entropy	5.570m	2.902ms	3	3	100.00
V2	chip_sw_alert_handler_crashdump	chip_sw_rstmgr_alert_info	28.995m	13.515ms	3	3	100.00
V2	chip_sw_alert_handler_ping_timeout	chip_sw_alert_handler_ping_timeout	7.285m	3.980ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_sleep_mode_alerts	chip_sw_alert_handler_lpg_sleep_mode_alerts	10.345m	4.517ms	86	90	95.56
V2	chip_sw_alert_handler_lpg_sleep_mode_pings	chip_sw_alert_handler_lpg_sleep_mode_pings	26.841m	12.697ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_clock_off	chip_sw_alert_handler_lpg_clkoff	32.337m	9.421ms	3	3	100.00
V2	chip_sw_alert_handler_lpg_reset_toggle	chip_sw_alert_handler_lpg_reset_toggle	34.018m	8.190ms	3	3	100.00
V2	chip_sw_alert_handler_reverse_ping_in_deep_sleep	chip_sw_alert_handler_reverse_ping_in_deep_sleep	3.787h	256.111ms	3	3	100.00
V2	chip_jtag_csr_rw	chip_jtag_csr_rw	40.961m	21.055ms	3	3	100.00
V2	chip_jtag_mem_access	chip_jtag_mem_access	28.809m	13.048ms	3	3	100.00
V2	chip_rv_dm_ndm_reset_req	chip_rv_dm_ndm_reset_req	7.599m	3.940ms	3	3	100.00
V2	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	chip_sw_rv_dm_ndm_reset_req_when_cpu_halted	8.300m	4.446ms	3	3	100.00
V2	chip_rv_dm_access_after_wakeup	chip_sw_rv_dm_access_after_wakeup	7.240m	5.389ms	3	3	100.00
V2	chip_sw_rv_dm_jtag_tap_sel	chip_tap_straps_rma	14.272m	8.189ms	5	5	100.00
V2	chip_rv_dm_lc_disabled	chip_rv_dm_lc_disabled	6.580m	13.666ms	3	3	100.00
V2	chip_rv_dm_jtag	chip_rv_dm_jtag			0	0	--
V2	chip_rv_dm_dtm	chip_rv_dm_dtm			0	0	--
V2	chip_rv_dm_control_status	chip_rv_dm_control_status			0	0	--
V2		TOTAL			2588	2657	97.40
V2S	chip_sw_aes_masking_off	chip_sw_aes_masking_off	5.837m	3.537ms	3	3	100.00
V2S		TOTAL			3	3	100.00
V3	chip_sw_usb_suspend	chip_sw_usb_suspend			0	0	--
V3	chip_usb_wake_debug	chip_usb_wake_debug			0	0	--
V3	chip_sw_coremark	chip_sw_coremark			0	1	0.00
V3	chip_sw_power_max_load	chip_sw_power_virus	15.607m	4.313ms	0	3	0.00
V3	rom_e2e_debug	rom_e2e_jtag_debug_test_unlocked0	2.350m	2.882ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.176m	2.940ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.137m	2.451ms	0	1	0.00
V3	rom_e2e_jtag_inject	rom_e2e_jtag_inject_test_unlocked0	55.102m	41.320ms	0	1	0.00
		rom_e2e_jtag_inject_dev	57.281m	41.199ms	0	1	0.00
		rom_e2e_jtag_inject_rma	51.985m	41.166ms	0	1	0.00
V3	rom_bootstrap_rma	rom_bootstrap_rma			0	0	--
V3	rom_e2e_weak_straps	rom_e2e_weak_straps			0	0	--
V3	rom_e2e_self_hash	rom_e2e_self_hash	40.685m	9.746ms	0	3	0.00
V3	manuf_cp_unlock_raw	manuf_cp_unlock_raw			0	0	--
V3	manuf_scrap	manuf_scrap			0	0	--
V3	manuf_cp_yield_test	manuf_cp_yield_test			0	0	--
V3	manuf_cp_ast_test_execution	manuf_cp_ast_test_execution			0	0	--
V3	manuf_cp_device_info_flash_wr	manuf_cp_device_info_flash_wr			0	0	--
V3	manuf_cp_test_lock	manuf_cp_test_lock			0	0	--
V3	manuf_ft_exit_token	manuf_ft_exit_token			0	0	--
V3	manuf_ft_sku_individualization_preop	manuf_ft_sku_individualization_preop			0	0	--
V3	manuf_ft_sku_individualization	manuf_ft_sku_individualization			0	0	--
V3	manuf_ft_provision_rma_token_and_personalization	manuf_ft_provision_rma_token_and_personalization			0	0	--
V3	manuf_ft_load_transport_image	manuf_ft_load_transport_image			0	0	--
V3	manuf_ft_load_certificates	manuf_ft_load_certificates			0	0	--
V3	manuf_ft_eom	manuf_ft_eom			0	0	--
V3	manuf_rma_entry	manuf_rma_entry			0	0	--
V3	manuf_sram_program_crc_functest	manuf_sram_program_crc_functest			0	0	--
V3	chip_sw_adc_ctrl_normal	chip_sw_adc_ctrl_normal			0	0	--
V3	chip_sw_adc_ctrl_oneshot	chip_sw_adc_ctrl_oneshot			0	0	--
V3	chip_sw_clkmgr_jitter_cycle_measurements	chip_sw_clkmgr_jitter_frequency	7.963m	3.931ms	3	3	100.00
V3	chip_sw_edn_boot_mode	chip_sw_edn_boot_mode	9.140m	2.491ms	3	3	100.00
V3	chip_sw_edn_auto_mode	chip_sw_edn_auto_mode	16.626m	4.392ms	3	3	100.00
V3	chip_sw_edn_sw_mode	chip_sw_edn_sw_mode	37.313m	8.813ms	3	3	100.00
V3	chip_sw_edn_kat	chip_sw_edn_kat	11.517m	3.325ms	3	3	100.00
V3	chip_sw_entropy_src_bypass_mode_health_tests	chip_sw_entropy_src_bypass_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_fips_mode_health_tests	chip_sw_entropy_src_fips_mode_health_tests			0	0	--
V3	chip_sw_entropy_src_validation	chip_sw_entropy_src_validation			0	0	--
V3	chip_sw_flash_memory_protection	chip_sw_flash_ctrl_mem_protection	24.292m	6.414ms	3	3	100.00
V3	chip_sw_hmac_sha2_stress	chip_sw_hmac_sha2_stress			0	0	--
V3	chip_sw_hmac_stress	chip_sw_hmac_stress			0	0	--
V3	chip_sw_hmac_endianness	chip_sw_hmac_endianness			0	0	--
V3	chip_sw_hmac_secure_wipe	chip_sw_hmac_secure_wipe			0	0	--
V3	chip_sw_hmac_error_conditions	chip_sw_hmac_error_conditions			0	0	--
V3	chip_sw_i2c_speed	chip_sw_i2c_speed			0	0	--
V3	chip_sw_i2c_override	chip_sw_i2c_override			0	0	--
V3	chip_sw_i2c_clockstretching	chip_sw_i2c_clockstretching			0	0	--
V3	chip_sw_i2c_nack	chip_sw_i2c_nack			0	0	--
V3	chip_sw_i2c_repeatedstart	chip_sw_i2c_repeatedstart			0	0	--
V3	chip_sw_keymgr_sideload_kmac_error	chip_sw_keymgr_sideload_kmac_error			0	0	--
V3	chip_sw_keymgr_derive_attestation	chip_sw_keymgr_derive_attestation			0	0	--
V3	chip_sw_keymgr_derive_sealing	chip_sw_keymgr_derive_sealing			0	0	--
V3	chip_sw_kmac_sha3_stress	chip_sw_kmac_sha3_stress			0	0	--
V3	chip_sw_kmac_shake_stress	chip_sw_kmac_shake_stress			0	0	--
V3	chip_sw_kmac_cshake_stress	chip_sw_kmac_cshake_stress			0	0	--
V3	chip_sw_kmac_kmac_stress	chip_sw_kmac_kmac_stress			0	0	--
V3	chip_sw_kmac_kmac_key_sideload	chip_sw_kmac_kmac_key_sideload			0	0	--
V3	chip_sw_kmac_endianess	chip_sw_kmac_endianess			0	0	--
V3	chip_sw_kmac_entropy_stress	chip_sw_kmac_entropy_stress			0	0	--
V3	chip_sw_kmac_error_conditions	chip_sw_kmac_error_conditions			0	0	--
V3	chip_sw_lc_ctrl_kmac_error	chip_sw_lc_ctrl_kmac_error			0	0	--
V3	chip_sw_lc_ctrl_debug_access	chip_sw_lc_ctrl_debug_access			0	0	--
V3	chip_sw_otp_ctrl_vendor_test_csr_access	chip_sw_otp_ctrl_vendor_test_csr_access	3.775m	2.273ms	3	3	100.00
V3	chip_sw_otp_ctrl_escalation	chip_sw_otp_ctrl_escalation	11.120m	5.514ms	1	1	100.00
V3	otp_ctrl_calibration	otp_ctrl_calibration			0	0	--
V3	otp_ctrl_partition_access_locked	otp_ctrl_partition_access_locked			0	0	--
V3	otp_ctrl_check_timeout	otp_ctrl_check_timeout			0	0	--
V3	chip_sw_sensor_ctrl_deep_sleep_wake_up	chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up	11.161m	5.240ms	3	3	100.00
V3	chip_sw_pwrmgr_usb_clk_disabled_when_active	chip_sw_pwrmgr_usb_clk_disabled_when_active	7.426m	4.533ms	3	3	100.00
V3	chip_sw_all_resets	chip_sw_pwrmgr_all_reset_reqs	31.099m	13.819ms	3	3	100.00
V3	chip_sw_rom_ctrl_kmac_error	chip_sw_rom_ctrl_kmac_error			0	0	--
V3	chip_sw_rom_ctrl_digests	chip_sw_rom_ctrl_digests			0	0	--
V3	chip_sw_plic_alerts	chip_sw_all_escalation_resets	15.319m	5.337ms	98	100	98.00
V3	tick_configuration	chip_sw_rv_timer_systick_test			0	3	0.00
V3	counter_wrap	chip_sw_rv_timer_systick_test			0	3	0.00
V3	chip_sw_spi_device_pass_through_flash_model	chip_sw_spi_device_pass_through_flash_model			0	0	--
V3	chip_sw_spi_device_output_when_disabled_or_sleeping	chip_sw_spi_device_output_when_disabled_or_sleeping			0	0	--
V3	chip_sw_spi_host_pass_through	chip_sw_spi_host_pass_through			0	0	--
V3	chip_sw_spi_host_configuration	chip_sw_spi_host_configuration			0	0	--
V3	chip_sw_spi_host_events	chip_sw_spi_host_events			0	0	--
V3	chip_sw_sram_memset	chip_sw_sram_memset			0	0	--
V3	chip_sw_sram_subword_access	chip_sw_sram_subword_access			0	0	--
V3	chip_sw_uart_parity	chip_sw_uart_parity			0	0	--
V3	chip_sw_uart_line_loopback	chip_sw_uart_line_loopback			0	0	--
V3	chip_sw_uart_system_loopback	chip_sw_uart_system_loopback			0	0	--
V3	chip_sw_uart_line_break	chip_sw_uart_line_break			0	0	--
V3	chip_sw_uart_watermarks	chip_sw_uart_tx_rx	18.715m	6.432ms	5	5	100.00
V3	chip_sw_usbdev_stream	chip_sw_usbdev_stream	1.041h	18.714ms	1	1	100.00
V3	chip_sw_usbdev_iso	chip_sw_usbdev_iso			0	0	--
V3	chip_sw_usbdev_mixed	chip_sw_usbdev_mixed			0	0	--
V3	chip_sw_usbdev_suspend_resume	chip_sw_usbdev_suspend_resume			0	0	--
V3	chip_sw_usbdev_aon_wake_reset	chip_sw_usbdev_aon_wake_reset			0	0	--
V3	chip_sw_usbdev_aon_wake_disconnect	chip_sw_usbdev_aon_wake_disconnect			0	0	--
V3	chip_sw_usbdev_toggle_restore	chip_sw_usbdev_toggle_restore			0	0	--
V3	chip_rv_dm_perform_debug	rom_e2e_jtag_debug_test_unlocked0	2.350m	2.882ms	0	1	0.00
		rom_e2e_jtag_debug_dev	2.176m	2.940ms	0	1	0.00
		rom_e2e_jtag_debug_rma	2.137m	2.451ms	0	1	0.00
V3	chip_sw_rv_dm_access_after_hw_reset	chip_sw_rv_dm_access_after_escalation_reset	9.692m	4.840ms	3	3	100.00
V3		TOTAL			32	48	66.67
	Unmapped tests	chip_sival_flash_info_access	6.245m	3.610ms	3	3	100.00
		chip_sw_rstmgr_rst_cnsty_escalation	12.246m	5.890ms	3	3	100.00
		chip_sw_otbn_ecdsa_op_irq	1.155h	17.039ms	3	3	100.00
		chip_sw_rv_core_ibex_rnd	18.965m	5.326ms	3	3	100.00
		chip_sw_rv_core_ibex_nmi_irq	14.601m	5.290ms	3	3	100.00
		chip_sw_pwrmgr_sleep_wake_5_bug	8.776m	5.367ms	3	3	100.00
		chip_sw_rv_core_ibex_address_translation	5.458m	3.152ms	3	3	100.00
		chip_sw_rv_core_ibex_lockstep_glitch	2.619m	2.290ms	3	3	100.00
		chip_sw_flash_ctrl_write_clear			0	3	0.00
		TOTAL			2849	2958	96.32

Testplan Progress

Items	Total	Written	Passing	Progress
N.A.	9	9	8	88.89
V1	19	19	17	89.47
V2	290	276	252	86.90
V2S	1	1	1	100.00
V3	91	22	12	13.19

Coverage Results

Coverage Dashboard

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	GROUP
96.12	95.41	94.25	95.00	--	94.90	97.57	99.58

Failure Buckets

• Exit reason: Error: User command failed Job returned non-zero exit code has 42 failures:

  • Test chip_sw_flash_ctrl_write_clear has 3 failures.

    • 0.chip_sw_flash_ctrl_write_clear.93382793401934187768083206140078233658882440636181798017748429984489136692975
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_ctrl_write_clear/latest/run.log

        (15:36:33) Loading:
        (15:36:34) Loading:
        (15:36:34) Loading: 4 packages loaded
        (15:36:34) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:36:34) WARNING: Target pattern parsing failed.
        (15:36:34) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:36:34) INFO: Elapsed time: 21.519s
        (15:36:34) INFO: 0 processes.
        (15:36:34) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.chip_sw_flash_ctrl_write_clear.94441187359123539612487273253609149776081086294239499126821291988145025448555
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_ctrl_write_clear/latest/run.log

        (15:41:46) Loading:
        (15:41:47) Loading:
        (15:41:47) Loading: 4 packages loaded
        (15:41:47) ERROR: Skipping '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:41:47) WARNING: Target pattern parsing failed.
        (15:41:47) ERROR: no such target '//sw/device/tests/sim_dv:flash_ctrl_write_clear_test_sim_dv': target 'flash_ctrl_write_clear_test_sim_dv' not declared in package 'sw/device/tests/sim_dv' defined by /workspace/mnt/repo_top/sw/device/tests/sim_dv/BUILD (Tip: use `query "//sw/device/tests/sim_dv:*"` to see all the targets in that package)
        (15:41:47) INFO: Elapsed time: 57.551s
        (15:41:47) INFO: 0 processes.
        (15:41:47) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_meas.41795195398597669114394807137938540024305278864572774510307722967684834626717
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:36:11) Loading:
        (15:36:12) Loading:
        (15:36:12) Loading: 4 packages loaded
        (15:36:12) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:36:12) WARNING: Target pattern parsing failed.
        (15:36:12) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:36:12) INFO: Elapsed time: 18.380s
        (15:36:12) INFO: 0 processes.
        (15:36:12) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_meas.35199738055044443551522984948796878559487556705462534060615210583698203617175
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_meas/latest/run.log

        (15:44:18) Loading:
        (15:44:18) Loading:
        (15:44:18) Loading: 4 packages loaded
        (15:44:19) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:44:19) WARNING: Target pattern parsing failed.
        (15:44:19) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:44:19) INFO: Elapsed time: 44.621s
        (15:44:19) INFO: 0 processes.
        (15:44:19) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_no_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_no_meas.86652244999598391677243718969417968014811870666880669105242923979528412551526
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:36:06) Loading:
        (15:36:07) Loading:
        (15:36:07) Loading: 4 packages loaded
        (15:36:07) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:36:07) WARNING: Target pattern parsing failed.
        (15:36:07) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:36:07) INFO: Elapsed time: 17.277s
        (15:36:07) INFO: 0 processes.
        (15:36:07) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_no_meas.84643994789775718199981554554122638016337064386815649150562967879489561776305
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_no_meas/latest/run.log

        (15:44:52) Loading:
        (15:44:52) Loading:
        (15:44:52) Loading: 4 packages loaded
        (15:44:53) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:44:53) WARNING: Target pattern parsing failed.
        (15:44:53) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:44:53) INFO: Elapsed time: 40.380s
        (15:44:53) INFO: 0 processes.
        (15:44:53) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_keymgr_init_rom_ext_invalid_meas has 3 failures.

    • 0.rom_e2e_keymgr_init_rom_ext_invalid_meas.29610146648553051230239695879179592463399228442386300143656221826604202467462
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:36:08) Loading:
        (15:36:08) Loading:
        (15:36:08) Loading: 4 packages loaded
        (15:36:08) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:36:08) WARNING: Target pattern parsing failed.
        (15:36:08) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:36:09) INFO: Elapsed time: 18.123s
        (15:36:09) INFO: 0 processes.
        (15:36:09) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_keymgr_init_rom_ext_invalid_meas.57434606110565630101151554290707353688013480579444358432590398069858316154524
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_keymgr_init_rom_ext_invalid_meas/latest/run.log

        (15:44:58) Loading:
        (15:44:59) Loading:
        (15:44:59) Loading: 4 packages loaded
        (15:44:59) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:44:59) WARNING: Target pattern parsing failed.
        (15:44:59) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/keymgr:rom_e2e_keymgr_init_test_sim_dv': target 'rom_e2e_keymgr_init_test_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/keymgr' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/keymgr/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/keymgr:*"` to see all the targets in that package)
        (15:44:59) INFO: Elapsed time: 60.390s
        (15:44:59) INFO: 0 processes.
        (15:44:59) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • Test rom_e2e_sigverify_mod_exp_test_unlocked0_otbn has 3 failures.

    • 0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.74827390061133738966588537540182021658470641641930883827779323429735691964052
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (15:36:13) Loading:
        (15:36:14) Loading:
        (15:36:14) Loading: 4 packages loaded
        (15:36:14) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:36:14) WARNING: Target pattern parsing failed.
        (15:36:14) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:36:14) INFO: Elapsed time: 16.629s
        (15:36:14) INFO: 0 processes.
        (15:36:14) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • 1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn.59048185506414907391748930385039587704628775907557949483821903566566138902496
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_sigverify_mod_exp_test_unlocked0_otbn/latest/run.log

        (15:43:56) Loading:
        (15:43:57) Loading:
        (15:43:57) Loading: 4 packages loaded
        (15:43:57) ERROR: Skipping '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:43:57) WARNING: Target pattern parsing failed.
        (15:43:57) ERROR: no such target '//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:empty_test_sigverify_mod_exp_sim_dv': target 'empty_test_sigverify_mod_exp_sim_dv' not declared in package 'sw/device/silicon_creator/rom/e2e/sigverify_mod_exp' defined by /workspace/mnt/repo_top/sw/device/silicon_creator/rom/e2e/sigverify_mod_exp/BUILD (Tip: use `query "//sw/device/silicon_creator/rom/e2e/sigverify_mod_exp:*"` to see all the targets in that package)
        (15:43:57) INFO: Elapsed time: 20.248s
        (15:43:57) INFO: 0 processes.
        (15:43:57) FAILED: Build did NOT complete successfully (5 packages loaded)
        make: *** [/workspace/mnt/repo_top/hw/dv/tools/dvsim/sim.mk:73: sw_build] Error 1
      

    • ... and 1 more failures.

  • ... and 9 more tests.

• UVM_ERROR @ * us: (cip_base_vseq.sv:815) [chip_common_vseq] Check failed (!has_outstanding_access()) Waited * cycles to issue a reset with no outstanding accesses. has 20 failures:

  • Test chip_csr_mem_rw_with_rand_reset has 20 failures.

    • 0.chip_csr_mem_rw_with_rand_reset.112494188332467422690753490306080864243086795883487869730431710526625511756084
      Line 373, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2234.719163 us: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2234.719163 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_csr_mem_rw_with_rand_reset.78922530988501976408419251918416028773837507006823310824255497038252782298911
      Line 370, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_csr_mem_rw_with_rand_reset/latest/run.log

        UVM_ERROR @ 2351.612501 us: (cip_base_vseq.sv:815) [uvm_test_top.env.virtual_sequencer.chip_common_vseq] Check failed (!has_outstanding_access()) Waited 10000 cycles to issue a reset with no outstanding accesses.
        UVM_INFO @ 2351.612501 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 18 more failures.

• Job chip_earlgrey_asic-sim-vcs_run_default killed due to: Exit reason: User job exceeded runlimit: User job timed out has 8 failures:

  • Test chip_sw_rv_timer_systick_test has 3 failures.

    • 0.chip_sw_rv_timer_systick_test.90349646914308999711386676011971392984332473116997237719928877095043985646363
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:0acba00b-ffbf-45d1-b061-f66c53110deb
      

    • 1.chip_sw_rv_timer_systick_test.16498468493524970708517508600021435657027381096557246698350776624403507983252
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_rv_timer_systick_test/latest/run.log

        Job ID: smart:54a6f0f9-b5c6-4d22-9be9-3b4d547b0432
      

    • ... and 1 more failures.

  • Test chip_sw_coremark has 1 failures.

    • 0.chip_sw_coremark.69175220162199054613723110566523646257331090316013923828174934786949409468009
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_coremark/latest/run.log

        Job ID: smart:14e8b6b5-0a75-4a05-98a8-913ebdfed167
      

  • Test chip_sw_ast_clk_rst_inputs has 3 failures.

    • 0.chip_sw_ast_clk_rst_inputs.105944372620392694485535233810628273788433715371553151106303558258889747901090
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:4532a187-e885-4d56-a3fb-ac25ab58afbc
      

    • 1.chip_sw_ast_clk_rst_inputs.102512612520860676227170589754802300633754960185043562203200312169237413395089
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_ast_clk_rst_inputs/latest/run.log

        Job ID: smart:fbec69f3-9769-48fb-b5de-22fe06bb39aa
      

    • ... and 1 more failures.

  • Test chip_sw_power_virus has 1 failures.

    • 0.chip_sw_power_virus.34703685594295262840080695750568016070624287764113053646228640637141331724374
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_power_virus/latest/run.log

        Job ID: smart:fc84c1da-6403-4e3c-8a3c-28f883b66788
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=* MEPC=* MTVAL=* has 4 failures:

  • Test chip_sw_alert_handler_lpg_sleep_mode_alerts has 4 failures.

    • 27.chip_sw_alert_handler_lpg_sleep_mode_alerts.8051177953423150736251532221936584721179994830880095587883825965038087559024
      Line 781, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/27.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 3342.136856 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
        UVM_INFO @ 3342.136856 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 47.chip_sw_alert_handler_lpg_sleep_mode_alerts.86012849303900557507682821413063609238887253364861293091153533775073723742438
      Line 760, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/47.chip_sw_alert_handler_lpg_sleep_mode_alerts/latest/run.log

        UVM_ERROR @ 4397.056502 us: (sw_logger_if.sv:526) [alert_handler_lpg_sleep_mode_alerts_test_sim_dv(sw/device/lib/testing/test_framework/ottf_isrs.c:99)] FAULT: Load Access Fault. MCAUSE=00000005 MEPC=20003a36 MTVAL=40600800
        UVM_INFO @ 4397.056502 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 2 more failures.

• UVM_FATAL @ * us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [chip_sw_flash_rma_unlocked_vseq] wait timeout occurred! has 3 failures:

  • Test chip_sw_flash_rma_unlocked has 3 failures.

    • 0.chip_sw_flash_rma_unlocked.54328162328914493423923532446900505435570714001444128017720813959768777349323
      Line 789, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 10010.140001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
        UVM_INFO @ 10010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_flash_rma_unlocked.34283745981073809696337229486279977904469188760942058845874092062055891722220
      Line 714, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_flash_rma_unlocked/latest/run.log

        UVM_FATAL @ 10010.380001 us: (chip_sw_flash_rma_unlocked_vseq.sv:158) [uvm_test_top.env.virtual_sequencer.chip_sw_flash_rma_unlocked_vseq] wait timeout occurred!
        UVM_INFO @ 10010.380001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_pwrmgr_normal_sleep_por_reset has 1 failures.

    • 0.chip_sw_pwrmgr_normal_sleep_por_reset.56041427720420261675060639570812088299336926591727997281775814017710309303176
      Line 835, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_pwrmgr_normal_sleep_por_reset/latest/run.log

        UVM_ERROR @ 17565.600256 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 17565.600256 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test chip_sw_pwrmgr_deep_sleep_por_reset has 2 failures.

    • 1.chip_sw_pwrmgr_deep_sleep_por_reset.55989882617809555433000217725826591650356459806732409636976231446380410496794
      Line 854, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

        UVM_ERROR @ 17187.706229 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 17187.706229 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 2.chip_sw_pwrmgr_deep_sleep_por_reset.86134809867933481718770396324176907071978486419128955061752132542399011242529
      Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_pwrmgr_deep_sleep_por_reset/latest/run.log

        UVM_ERROR @ 17987.021620 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_sleep_por_reset_vseq] SW TEST TIMED OUT. STATE: SwTestStatusInTest, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 17987.021620 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat" has 3 failures:

  • Test chip_sw_sysrst_ctrl_outputs has 3 failures.

    • 0.chip_sw_sysrst_ctrl_outputs.83115638242781360742025835844000809545082441928928581827408167451681295614966
      Line 839, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.140001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sysrst_ctrl_outputs.83860825163521687005393598063026013193733175055339380857342655845716054920112
      Line 803, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sysrst_ctrl_outputs/latest/run.log

        UVM_FATAL @  10.180001 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "kTestPhase.dat"
        UVM_INFO @  10.180001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress has 3 failures:

  • Test chip_sw_csrng_lc_hw_debug_en_test has 3 failures.

    • 0.chip_sw_csrng_lc_hw_debug_en_test.6011984372075897632918749320764835520727830224073253236887008184219261631477
      Line 878, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log

        UVM_FATAL @ 20010.200001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
        UVM_INFO @ 20010.200001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_csrng_lc_hw_debug_en_test.42139545659295704690703268999502612372008323651186454884850336166358291712580
      Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_lc_hw_debug_en_test/latest/run.log

        UVM_FATAL @ 20010.140001 us: (chip_sw_csrng_lc_hw_debug_en_vseq.sv:56) [uvm_test_top.env.virtual_sequencer.chip_sw_csrng_lc_hw_debug_en_vseq] wait for lc transition in progress
        UVM_INFO @ 20010.140001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_entropy_src_fuse_vseq.sv:33) [chip_sw_entropy_src_fuse_vseq] *- has 3 failures:

  • Test chip_sw_csrng_fuse_en_sw_app_read_test has 3 failures.

    • 0.chip_sw_csrng_fuse_en_sw_app_read_test.38788094353962350108068731813836391459482274701588485990651105534831805819534
      Line 818, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_FATAL @ 10010.240001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
        UVM_INFO @ 10010.240001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_csrng_fuse_en_sw_app_read_test.61766869404181582084089361618834833732564620418158786648892096351231615167875
      Line 725, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_csrng_fuse_en_sw_app_read_test/latest/run.log

        UVM_FATAL @ 10010.300001 us: (chip_sw_entropy_src_fuse_vseq.sv:33) [uvm_test_top.env.virtual_sequencer.chip_sw_entropy_src_fuse_vseq] 1-
        UVM_INFO @ 10010.300001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred! has 3 failures:

  • Test chip_sw_sram_ctrl_execution_main has 3 failures.

    • 0.chip_sw_sram_ctrl_execution_main.3838863415053339669529757577500927249289983419856008715486178436428148215037
      Line 890, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_sram_ctrl_execution_main/latest/run.log

        UVM_FATAL @ 10020.640001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
        UVM_INFO @ 10020.640001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.chip_sw_sram_ctrl_execution_main.57205459428472519497332480058124342984168962626758925016095598518989161381837
      Line 802, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_sram_ctrl_execution_main/latest/run.log

        UVM_FATAL @ 10020.560001 us: (chip_sw_sram_ctrl_execution_main_vseq.sv:31) [uvm_test_top.env.virtual_sequencer.chip_sw_sram_ctrl_execution_main_vseq] wait timeout occurred!
        UVM_INFO @ 10020.560001 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_base_vseq.sv:303) virtual_sequencer [chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = * ns has 3 failures:

  • Test chip_sw_lc_ctrl_program_error has 3 failures.

    • 0.chip_sw_lc_ctrl_program_error.115297936102261435239313679072134891612180030047933096825622509466564225735216
      Line 791, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14977.435230 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14977.435230 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • 1.chip_sw_lc_ctrl_program_error.63216852285441184048610106127177971256062335289980018591613828644665495051048
      Line 780, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_lc_ctrl_program_error/latest/run.log

        UVM_ERROR @ 14589.270916 us: (chip_sw_base_vseq.sv:303) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.chip_sw_lc_ctrl_program_error_vseq] SW TEST TIMED OUT. STATE: SwTestStatusUnderReset, TIMEOUT = 12000000 ns
        
        UVM_INFO @ 14589.270916 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
      

    • ... and 1 more failures.

• UVM_FATAL @ * us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat" has 3 failures:

  • Test rom_e2e_jtag_debug_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_debug_test_unlocked0.111898636861477654429738998770267528032704057049242183989136663852608598889198
      Line 741, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_test_unlocked0/latest/run.log

        UVM_FATAL @ 2881.950000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2881.950000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_dev has 1 failures.

    • 0.rom_e2e_jtag_debug_dev.38674262434582830566286121106535860902505252357538947428284902633449962391764
      Line 706, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_dev/latest/run.log

        UVM_FATAL @ 2939.927000 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2939.927000 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_debug_rma has 1 failures.

    • 0.rom_e2e_jtag_debug_rma.81863772242573432624376170116560210586443948232034353501097382792438947730969
      Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_debug_rma/latest/run.log

        UVM_FATAL @ 2451.432500 us: (dv_utils_pkg.sv:269) [sw_symbol_get_addr_size] Check failed (ret) Failed to read line from "_rom_interrupt_vector_asm.dat"
        UVM_INFO @ 2451.432500 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_FATAL @ * us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred! has 3 failures:

  • Test rom_e2e_jtag_inject_test_unlocked0 has 1 failures.

    • 0.rom_e2e_jtag_inject_test_unlocked0.53575607440567590023806152754308551182894862538338693314417010201134157429560
      Line 777, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_test_unlocked0/latest/run.log

        UVM_FATAL @ 41319.548426 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 41319.548426 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_dev has 1 failures.

    • 0.rom_e2e_jtag_inject_dev.114344303493875893748855298334886529903479736675415167966446096281338228518010
      Line 796, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_dev/latest/run.log

        UVM_FATAL @ 41199.168167 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 41199.168167 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

  • Test rom_e2e_jtag_inject_rma has 1 failures.

    • 0.rom_e2e_jtag_inject_rma.45082123988576756097569825696712009096900045619812376189968848540201616735270
      Line 821, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_jtag_inject_rma/latest/run.log

        UVM_FATAL @ 41166.041244 us: (jtag_rv_debugger.sv:113) [debugger] timeout occurred!
        UVM_INFO @ 41166.041244 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: *x%xmatches (uint8_t *)kSimDvGoldenRomHash has 3 failures:

  • Test rom_e2e_self_hash has 3 failures.

    • 0.rom_e2e_self_hash.39307729567953985099326270657755557268686151674086273328421942121285783208553
      Line 755, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/0.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 9745.711160 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
        UVM_INFO @ 9745.711160 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 1.rom_e2e_self_hash.10013357329687513020769172694718930699241432641151558214777892879769812764224
      Line 759, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.rom_e2e_self_hash/latest/run.log

        UVM_ERROR @ 10013.343116 us: (sw_logger_if.sv:526) [rom_e2e_self_hash_sim_dv(sw/device/silicon_creator/rom/e2e/rom_e2e_self_hash_test.c:80)] CHECK-fail: (uint8_t *)output.dataM hash not self-checked for this device type: 0x%xmatches (uint8_t *)kSimDvGoldenRomHash
        UVM_INFO @ 10013.343116 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • ... and 1 more failures.

• UVM_ERROR @ * us: (chip_sw_power_virus_vseq.sv:166) [chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != *'b* (* [*] vs * [*]) has 2 failures:

  • Test chip_sw_power_virus has 2 failures.

    • 1.chip_sw_power_virus.53784157739911499537781765164031888008999226118189664169031631453947522949985
      Line 964, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/1.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 4312.829035 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 4312.829035 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 2.chip_sw_power_virus.113830460185054473920782332263113050222861787741251030717093403469221424151459
      Line 943, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/2.chip_sw_power_virus/latest/run.log

        UVM_ERROR @ 4661.505814 us: (chip_sw_power_virus_vseq.sv:166) [uvm_test_top.env.virtual_sequencer.chip_sw_power_virus_vseq] Check failed aes_ctrl_rnd_ctr != 4'b0000 (0 [0x0] vs 0 [0x0])
        UVM_INFO @ 4661.505814 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• UVM_ERROR @ * us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected *, got * has 2 failures:

  • Test chip_sw_all_escalation_resets has 2 failures.

    • 3.chip_sw_all_escalation_resets.24666714278691500448544562834539586681638268355565504654903154483950612595378
      Line 756, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 2948.211488 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 2948.211488 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
        
        
      

    • 27.chip_sw_all_escalation_resets.13075902084176977122235301656261266770727253258322731368432654438316905483131
      Line 833, in log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/27.chip_sw_all_escalation_resets/latest/run.log

        UVM_ERROR @ 3566.186768 us: (sw_logger_if.sv:526) [all_escalation_resets_test_sim_dv(w/device/tests/sim_dv/all_escalation_resets_test.c:468)] CHECK-fail: Unexpected mtval: expected 0x40600000, got 0x40600804
        UVM_INFO @ 3566.186768 us: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
        --- UVM Report catcher Summary ---
      

• Job chip_earlgrey_asic-sim-vcs_run_cover_reg_top killed due to: Exit reason: User job exceeded runlimit: User job timed out has 1 failures:

  • Test chip_csr_aliasing has 1 failures.

    • 3.chip_csr_aliasing.16358533282069340466923271080378721518384491193369574145202993689094234846080
      Log /container/opentitan-public/scratch/os_regression/chip_earlgrey_asic-sim-vcs/3.chip_csr_aliasing/latest/run.log

        Job ID: smart:d16b304f-229c-45b6-9a62-83e9bc4b5ddb
      

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