Unified Coverage Report :: Module :: rv_dm

Module : rv_dm

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_rv_dm_0.1/rtl/rv_dm.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_dm	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_rv_dm

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : rv_dm

	Total	Covered	Percent
Totals	82	82	100.00
Total Bits	906	906	100.00
Total Bits 0->1	453	453	100.00
Total Bits 1->0	453	453	100.00

Ports	82	82	100.00
Port Bits	906	906	100.00
Port Bits 0->1	453	453	100.00
Port Bits 1->0	453	453	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
lc_hw_debug_en_i[3:0]	Yes	Yes	T32,T65,T34	Yes	T1,T2,T3	INPUT
pinmux_hw_debug_en_i[3:0]	Yes	Yes	T32,T34,T67	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
scan_rst_ni	Unreachable	Unreachable		Unreachable		INPUT
ndmreset_req_o	Yes	Yes	T47,T48,T191	Yes	T47,T48,T191	OUTPUT
dmactive_o	Yes	Yes	T32,T6,T171	Yes	T32,T72,T6	OUTPUT
debug_req_o	Yes	Yes	T191,T192,T236	Yes	T191,T192,T236	OUTPUT
unavailable_i	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.d_ready	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
regs_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
regs_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T51,T76,T77	Yes	T51,T76,T77	INPUT
regs_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T51,T76,T77	Yes	T51,T76,T77	INPUT
regs_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_data[31:0]	Yes	Yes	T51,T77,T78	Yes	T51,T77,T78	INPUT
regs_tl_d_i.a_mask[3:0]	Yes	Yes	T51,T77,T81	Yes	T51,T77,T81	INPUT
regs_tl_d_i.a_address[1:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	INPUT
regs_tl_d_i.a_address[20:2]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[21]	Yes	Yes	*T51,*T76,*T77	Yes	T51,T76,T77	INPUT
regs_tl_d_i.a_address[23:22]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[24]	Yes	Yes	*T51,*T76,*T77	Yes	T51,T76,T77	INPUT
regs_tl_d_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_address[30]	Yes	Yes	*T51,*T76,*T77	Yes	T51,T76,T77	INPUT
regs_tl_d_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_source[5:0]	Yes	Yes	*T51,T77,T81	Yes	T51,T77,T81	INPUT
regs_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	INPUT
regs_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
regs_tl_d_i.a_opcode[2:0]	Yes	Yes	T77,T78,T81	Yes	T77,T78,T81	INPUT
regs_tl_d_i.a_valid	Yes	Yes	T51,T76,T77	Yes	T51,T76,T77	INPUT
regs_tl_d_o.a_ready	Yes	Yes	T51,T76,T78	Yes	T51,T76,T77	OUTPUT
regs_tl_d_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
regs_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
regs_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T51,T76,T77	Yes	T51,T76,T77	OUTPUT
regs_tl_d_o.d_data[31:0]	Yes	Yes	T51,T76,T77	Yes	T51,T76,T77	OUTPUT
regs_tl_d_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
regs_tl_d_o.d_source[5:0]	Yes	Yes	*T51,T77,T81	Yes	T51,T77,T81	OUTPUT
regs_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_size[1:0]	Yes	Yes	T76,T77,T81	Yes	T76,T77,T81	OUTPUT
regs_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_opcode[0]	Yes	Yes	*T51,*T77,*T81	Yes	T51,T77,T81	OUTPUT
regs_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
regs_tl_d_o.d_valid	Yes	Yes	T51,T76,T77	Yes	T51,T76,T77	OUTPUT
mem_tl_d_i.d_ready	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
mem_tl_d_i.a_user.data_intg[6:0]	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	INPUT
mem_tl_d_i.a_user.cmd_intg[6:0]	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	INPUT
mem_tl_d_i.a_user.instr_type[3:0]	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	INPUT
mem_tl_d_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_data[31:0]	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	INPUT
mem_tl_d_i.a_mask[3:0]	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	INPUT
mem_tl_d_i.a_address[11:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
mem_tl_d_i.a_address[15:12]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_address[16]	Yes	Yes	*T191,*T198,*T192	Yes	T191,T198,T192	INPUT
mem_tl_d_i.a_address[31:17]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_source[5:0]	Yes	Yes	*T191,*T192,*T236	Yes	T191,T192,T236	INPUT
mem_tl_d_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
mem_tl_d_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
mem_tl_d_i.a_opcode[2:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
mem_tl_d_i.a_valid	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	INPUT
mem_tl_d_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mem_tl_d_o.d_error	Yes	Yes	T1,T2,T3	Yes	T32,T65,T34	OUTPUT
mem_tl_d_o.d_user.data_intg[6:0]	Yes	Yes	T191,T192,T236	Yes	T191,T192,T236	OUTPUT
mem_tl_d_o.d_user.rsp_intg[6:0]	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	OUTPUT
mem_tl_d_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T32,T65,T34	OUTPUT
mem_tl_d_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
mem_tl_d_o.d_source[5:0]	Yes	Yes	*T191,*T192,*T236	Yes	T191,T192,T236	OUTPUT
mem_tl_d_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
mem_tl_d_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T32,T65,T34	OUTPUT
mem_tl_d_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
mem_tl_d_o.d_valid	Yes	Yes	T191,T198,T192	Yes	T191,T198,T192	OUTPUT
sba_tl_h_o.d_ready	Yes	Yes	T32,T65,T34	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.data_intg[6:0]	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	OUTPUT
sba_tl_h_o.a_user.cmd_intg[6:0]	Yes	Yes	T32,T65,T34	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.instr_type[3:0]	Yes	Yes	T32,T65,T34	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_data[31:0]	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	OUTPUT
sba_tl_h_o.a_mask[3:0]	Yes	Yes	T32,T65,T34	Yes	T1,T2,T3	OUTPUT
sba_tl_h_o.a_address[31:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
sba_tl_h_o.a_source[5:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
sba_tl_h_o.a_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_size[1:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
sba_tl_h_o.a_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
sba_tl_h_o.a_opcode[2:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
sba_tl_h_o.a_valid	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	OUTPUT
sba_tl_h_i.a_ready	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
sba_tl_h_i.d_error	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	INPUT
sba_tl_h_i.d_user.data_intg[6:0]	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	INPUT
sba_tl_h_i.d_user.rsp_intg[6:0]	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	INPUT
sba_tl_h_i.d_data[31:0]	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	INPUT
sba_tl_h_i.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	INPUT
sba_tl_h_i.d_source[5:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	INPUT
sba_tl_h_i.d_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_size[1:0]	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	INPUT
sba_tl_h_i.d_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_opcode[0]	Yes	Yes	*T72,*T6,*T74	Yes	T72,T6,T74	INPUT
sba_tl_h_i.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		INPUT
sba_tl_h_i.d_valid	Yes	Yes	T72,T6,T74	Yes	T72,T6,T74	INPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T83,T618,T84	Yes	T83,T618,T84	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T83,T618,T84	Yes	T83,T618,T84	OUTPUT
jtag_i.tdi	Yes	Yes	T32,T72,T6	Yes	T32,T72,T6	INPUT
jtag_i.trst_n	Yes	Yes	T32,T72,T6	Yes	T32,T72,T6	INPUT
jtag_i.tms	Yes	Yes	T32,T72,T6	Yes	T32,T72,T6	INPUT
jtag_i.tck	Yes	Yes	T32,T72,T6	Yes	T32,T72,T6	INPUT
jtag_o.tdo_oe	Yes	Yes	T32,T72,T6	Yes	T32,T72,T6	OUTPUT
jtag_o.tdo	Yes	Yes	T32,T72,T6	Yes	T32,T72,T6	OUTPUT

*Tests covering at least one bit in the range