Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pwm_aon.u_reg.u_cfg_cdc.u_src_to_dst_req

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_wkup_detector_en_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_wkup_detector_en_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_wkup_detector_en_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.88	90.91	84.62			100.00	100.00	u_wkup_detector_en_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
41.67	50.00	33.33					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.88	90.91	84.62			100.00	100.00	u_wkup_detector_en_4_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
41.67	50.00	33.33					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_wkup_detector_en_5_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
93.88	90.91	84.62			100.00	100.00	u_wkup_detector_en_6_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
41.67	50.00	33.33					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
98.08	100.00	92.31			100.00	100.00	u_wkup_detector_en_7_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_2_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_3_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_4_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_5_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_6_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_7_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_0_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
97.73	100.00	90.91			100.00	100.00	u_wkup_detector_cnt_th_1_cdc

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_arb

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_flop_2sync	100.00	100.00				100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T54,T55,T51
1	1	Covered	T54,T55,T56

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T54,T55,T56
1	1	Covered	T54,T55,T51

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	217	0	0
SrcPulseCheck_M	121500719	217	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	217	0	0
T51	0	1	0	0
T54	650	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T126	273	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	16	0	0
T201	550	0	0	0
T215	9791	0	0	0
T233	439	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	4	0	0
T376	1282	0	0	0
T377	426	0	0	0
T378	1732	0	0	0
T379	638	0	0	0
T380	1151	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	217	0	0
T51	0	1	0	0
T54	42359	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T126	9829	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	16	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	4	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T54,T55,T51
1	1	Covered	T54,T55,T56

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T54,T55,T56
1	1	Covered	T54,T55,T51

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	217	0	0
SrcPulseCheck_M	1541566	217	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	217	0	0
T51	0	1	0	0
T54	42359	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T126	9829	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	16	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	4	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	217	0	0
T51	0	1	0	0
T54	650	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T126	273	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	16	0	0
T201	550	0	0	0
T215	9791	0	0	0
T233	439	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	4	0	0
T376	1282	0	0	0
T377	426	0	0	0
T378	1732	0	0	0
T379	638	0	0	0
T380	1151	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T51,T57,T347
1	1	Covered	T57,T167,T168

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T57,T167,T168
1	1	Covered	T51,T57,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	199	0	0
SrcPulseCheck_M	121500719	201	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	199	0	0
T51	3823	1	0	0
T57	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	201	0	0
T51	426138	1	0	0
T57	0	3	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T51,T57,T347
1	1	Covered	T57,T167,T168

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T57,T167,T168
1	1	Covered	T51,T57,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	199	0	0
SrcPulseCheck_M	1541566	199	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	199	0	0
T51	426138	1	0	0
T57	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	199	0	0
T51	3823	1	0	0
T57	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T52,T51,T347
1	1	Covered	T52,T167,T168

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T52,T167,T168
1	1	Covered	T52,T51,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	222	0	0
SrcPulseCheck_M	121500719	223	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	222	0	0
T51	0	1	0	0
T52	819	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	3	0	0
T268	505	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	8	0	0
T375	0	2	0	0
T388	945	0	0	0
T389	1064	0	0	0
T390	313	0	0	0
T391	821	0	0	0
T392	529	0	0	0
T393	1431	0	0	0
T394	788	0	0	0
T395	400	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	223	0	0
T51	0	1	0	0
T52	47584	3	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	3	0	0
T268	35974	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	8	0	0
T375	0	2	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T52,T51,T347
1	1	Covered	T52,T167,T168

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T52,T167,T168
1	1	Covered	T52,T51,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	222	0	0
SrcPulseCheck_M	1541566	222	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	222	0	0
T51	0	1	0	0
T52	47584	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	3	0	0
T268	35974	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	8	0	0
T375	0	2	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	222	0	0
T51	0	1	0	0
T52	819	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	3	0	0
T268	505	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	8	0	0
T375	0	2	0	0
T388	945	0	0	0
T389	1064	0	0	0
T390	313	0	0	0
T391	821	0	0	0
T392	529	0	0	0
T393	1431	0	0	0
T394	788	0	0	0
T395	400	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	207	0	0
SrcPulseCheck_M	121500719	207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	207	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	11	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	207	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	11	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	207	0	0
SrcPulseCheck_M	1541566	207	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	207	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	11	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	207	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	11	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	175	0	0
SrcPulseCheck_M	121500719	175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	175	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	175	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	175	0	0
SrcPulseCheck_M	1541566	175	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	175	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	175	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	9	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	218	0	0
SrcPulseCheck_M	121500719	218	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	218	0	0
T16	1382	2	0	0
T19	0	4	0	0
T44	1650	0	0	0
T46	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T58	0	4	0	0
T67	833	0	0	0
T68	752	0	0	0
T104	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	50954	0	0	0
T108	541	0	0	0
T109	707	0	0	0
T110	534	0	0	0
T111	744	0	0	0
T112	4389	0	0	0
T398	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	218	0	0
T16	49927	2	0	0
T19	0	4	0	0
T44	166989	0	0	0
T46	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T58	0	4	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	2	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T16,T19,T46
1	1	Covered	T16,T19,T46

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	218	0	0
SrcPulseCheck_M	1541566	218	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	218	0	0
T16	49927	2	0	0
T19	0	4	0	0
T44	166989	0	0	0
T46	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T58	0	4	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	2	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	218	0	0
T16	1382	2	0	0
T19	0	4	0	0
T44	1650	0	0	0
T46	0	2	0	0
T50	0	4	0	0
T51	0	1	0	0
T58	0	4	0	0
T67	833	0	0	0
T68	752	0	0	0
T104	0	2	0	0
T105	0	2	0	0
T106	0	2	0	0
T107	50954	0	0	0
T108	541	0	0	0
T109	707	0	0	0
T110	534	0	0	0
T111	744	0	0	0
T112	4389	0	0	0
T398	0	2	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	193	0	0
SrcPulseCheck_M	121500719	193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	193	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	1	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	193	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	1	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	193	0	0
SrcPulseCheck_M	1541566	193	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	193	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	1	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	193	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	14	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	1	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T51,T53,T347
1	1	Covered	T53,T167,T168

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T53,T167,T168
1	1	Covered	T51,T53,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	169	0	0
SrcPulseCheck_M	121500719	170	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	169	0	0
T51	3823	1	0	0
T53	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	170	0	0
T51	426138	1	0	0
T53	0	3	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T51,T53,T347
1	1	Covered	T53,T167,T168

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T53,T167,T168
1	1	Covered	T51,T53,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_en_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	169	0	0
SrcPulseCheck_M	1541566	169	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	169	0	0
T51	426138	1	0	0
T53	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	169	0	0
T51	3823	1	0	0
T53	0	2	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	6	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T54,T55,T51
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T167,T168,T169
1	1	Covered	T54,T55,T51

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	212	0	0
SrcPulseCheck_M	121500719	212	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	212	0	0
T51	0	1	0	0
T54	650	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T126	273	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T201	550	0	0	0
T215	9791	0	0	0
T233	439	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	9	0	0
T376	1282	0	0	0
T377	426	0	0	0
T378	1732	0	0	0
T379	638	0	0	0
T380	1151	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	212	0	0
T51	0	1	0	0
T54	42359	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T126	9829	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	9	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T54,T55,T51
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T54,T55,T51
1	0	Covered	T167,T168,T169
1	1	Covered	T54,T55,T51

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	212	0	0
SrcPulseCheck_M	1541566	212	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	212	0	0
T51	0	1	0	0
T54	42359	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T126	9829	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T201	36140	0	0	0
T215	102034	0	0	0
T233	20411	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	9	0	0
T376	132333	0	0	0
T377	27668	0	0	0
T378	47280	0	0	0
T379	35098	0	0	0
T380	53080	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	212	0	0
T51	0	1	0	0
T54	650	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T126	273	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T201	550	0	0	0
T215	9791	0	0	0
T233	439	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	9	0	0
T376	1282	0	0	0
T377	426	0	0	0
T378	1732	0	0	0
T379	638	0	0	0
T380	1151	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T51,T57,T347
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T57,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	172	0	0
SrcPulseCheck_M	121500719	173	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	172	0	0
T51	3823	1	0	0
T57	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	173	0	0
T51	426138	1	0	0
T57	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T51,T57,T347
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T57,T347
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T57,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	172	0	0
SrcPulseCheck_M	1541566	172	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	172	0	0
T51	426138	1	0	0
T57	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	172	0	0
T51	3823	1	0	0
T57	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	9	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T52,T51,T347
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T167,T168,T169
1	1	Covered	T52,T51,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	215	0	0
SrcPulseCheck_M	121500719	215	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	215	0	0
T51	0	1	0	0
T52	819	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	12	0	0
T268	505	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	11	0	0
T375	0	2	0	0
T388	945	0	0	0
T389	1064	0	0	0
T390	313	0	0	0
T391	821	0	0	0
T392	529	0	0	0
T393	1431	0	0	0
T394	788	0	0	0
T395	400	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	215	0	0
T51	0	1	0	0
T52	47584	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	12	0	0
T268	35974	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	11	0	0
T375	0	2	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T52,T51,T347
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T52,T51,T347
1	0	Covered	T167,T168,T169
1	1	Covered	T52,T51,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_2_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	215	0	0
SrcPulseCheck_M	1541566	215	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	215	0	0
T51	0	1	0	0
T52	47584	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	12	0	0
T268	35974	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	11	0	0
T375	0	2	0	0
T388	68974	0	0	0
T389	53942	0	0	0
T390	15769	0	0	0
T391	54726	0	0	0
T392	36985	0	0	0
T393	149250	0	0	0
T394	62029	0	0	0
T395	17551	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	215	0	0
T51	0	1	0	0
T52	819	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	12	0	0
T268	505	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	11	0	0
T375	0	2	0	0
T388	945	0	0	0
T389	1064	0	0	0
T390	313	0	0	0
T391	821	0	0	0
T392	529	0	0	0
T393	1431	0	0	0
T394	788	0	0	0
T395	400	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	211	0	0
SrcPulseCheck_M	121500719	211	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	211	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	22	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	211	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	22	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_3_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	211	0	0
SrcPulseCheck_M	1541566	211	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	211	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	22	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	211	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	22	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	213	0	0
SrcPulseCheck_M	121500719	213	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	213	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	10	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	213	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	10	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_4_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	213	0	0
SrcPulseCheck_M	1541566	213	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	213	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	10	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	213	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	10	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	10	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T16,T19,T46
1	1	Covered	T19,T50,T58

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T19,T50,T58
1	1	Covered	T16,T19,T46

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	232	0	0
SrcPulseCheck_M	121500719	232	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	232	0	0
T16	1382	1	0	0
T19	0	2	0	0
T44	1650	0	0	0
T46	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T58	0	2	0	0
T67	833	0	0	0
T68	752	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	50954	0	0	0
T108	541	0	0	0
T109	707	0	0	0
T110	534	0	0	0
T111	744	0	0	0
T112	4389	0	0	0
T398	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	232	0	0
T16	49927	1	0	0
T19	0	2	0	0
T44	166989	0	0	0
T46	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T58	0	2	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T16,T19,T46
1	1	Covered	T19,T50,T58

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T19,T46
1	0	Covered	T19,T50,T58
1	1	Covered	T16,T19,T46

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_5_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	232	0	0
SrcPulseCheck_M	1541566	232	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	232	0	0
T16	49927	1	0	0
T19	0	2	0	0
T44	166989	0	0	0
T46	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T58	0	2	0	0
T67	55206	0	0	0
T68	60328	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	124989	0	0	0
T108	42647	0	0	0
T109	57592	0	0	0
T110	36955	0	0	0
T111	55936	0	0	0
T112	508996	0	0	0
T398	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	232	0	0
T16	1382	1	0	0
T19	0	2	0	0
T44	1650	0	0	0
T46	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T58	0	2	0	0
T67	833	0	0	0
T68	752	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	50954	0	0	0
T108	541	0	0	0
T109	707	0	0	0
T110	534	0	0	0
T111	744	0	0	0
T112	4389	0	0	0
T398	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	159	0	0
SrcPulseCheck_M	121500719	159	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	159	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	7	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	159	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	7	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_6_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	159	0	0
SrcPulseCheck_M	1541566	159	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	159	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	7	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	159	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	7	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	6	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T51,T53,T347
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T53,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	203	0	0
SrcPulseCheck_M	121500719	203	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	203	0	0
T51	3823	1	0	0
T53	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	8	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	203	0	0
T51	426138	1	0	0
T53	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	8	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T51,T53,T347
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T53,T347
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T53,T347

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_7_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	203	0	0
SrcPulseCheck_M	1541566	203	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	203	0	0
T51	426138	1	0	0
T53	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	8	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	203	0	0
T51	3823	1	0	0
T53	0	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	8	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	4	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	217	0	0
SrcPulseCheck_M	121500719	217	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	217	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	13	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	7	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	217	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	13	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	7	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T51,T347,T167
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T51,T347,T167
1	0	Covered	T167,T168,T169
1	1	Covered	T51,T347,T167

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_0_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	217	0	0
SrcPulseCheck_M	1541566	217	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	217	0	0
T51	426138	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	13	0	0
T303	63454	0	0	0
T348	0	1	0	0
T349	43970	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	7	0	0
T375	0	2	0	0
T381	162098	0	0	0
T382	36121	0	0	0
T383	43274	0	0	0
T384	84158	0	0	0
T385	16554	0	0	0
T386	48523	0	0	0
T387	25641	0	0	0
T397	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	217	0	0
T51	3823	1	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	13	0	0
T303	742	0	0	0
T348	0	1	0	0
T349	515	0	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	7	0	0
T375	0	2	0	0
T381	1577	0	0	0
T382	1171	0	0	0
T383	555	0	0	0
T384	1390	0	0	0
T385	396	0	0	0
T386	632	0	0	0
T387	361	0	0	0
T397	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T48,T49
1	0	Covered	T47,T48,T49
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T48,T49
1	0	Covered	T167,T168,T169
1	1	Covered	T47,T48,T49

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_src_to_dst_req

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	1541566	204	0	0
SrcPulseCheck_M	121500719	205	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	204	0	0
T48	697	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T104	1270	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	5	0	0
T235	329	0	0	0
T245	315	0	0	0
T289	881	0	0	0
T292	958	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T369	0	1	0	0
T374	0	1	0	0
T635	867	0	0	0
T636	1036	0	0	0
T637	849	0	0	0
T638	804	0	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	205	0	0
T41	228909	0	0	0
T47	39472	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T74	87010	0	0	0
T156	52977	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	5	0	0
T199	65841	0	0	0
T225	156774	0	0	0
T227	35710	0	0	0
T270	58540	0	0	0
T271	39129	0	0	0
T272	44962	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
TOTAL		7	7	100.00
ALWAYS	28	3	3	100.00
CONT_ASSIGN	46	0	0
CONT_ASSIGN	49	0	0
ALWAYS	52	0	0
ALWAYS	86	3	3	100.00
CONT_ASSIGN	94	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
31	1	1
46		unreachable
49		unreachable
52		unreachable
53		unreachable
55		unreachable
86	1	1
87	1	1
89	1	1
94	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       31
 EXPRESSION (src_level ^ src_pulse_i)
             ----1----   -----2-----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T48,T49
1	0	Covered	T48,T49,T51
1	1	Covered	T167,T168,T169

 LINE       94
 EXPRESSION (dst_level_q ^ dst_level)
             -----1-----   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T47,T48,T49
1	0	Covered	T167,T168,T169
1	1	Covered	T47,T48,T49

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
IF	28	2	2	100.00
IF	86	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv' or '../src/lowrisc_prim_all_0.1/rtl/prim_pulse_sync.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	28	if ((!rst_src_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	86	if ((!rst_dst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_1_cdc.u_arb.gen_passthru.u_dst_to_src_ack

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	2	2	100.00	2	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	2	2	100.00	2	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DstPulseCheck_A	121500719	205	0	0
SrcPulseCheck_M	1541566	205	0	0

DstPulseCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	121500719	205	0	0
T41	228909	0	0	0
T47	39472	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T74	87010	0	0	0
T156	52977	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	5	0	0
T199	65841	0	0	0
T225	156774	0	0	0
T227	35710	0	0	0
T270	58540	0	0	0
T271	39129	0	0	0
T272	44962	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	1	0	0

SrcPulseCheck_M

Name	Attempts	Real Successes	Failures	Incomplete
Total	1541566	205	0	0
T41	2292	0	0	0
T47	683	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T74	967	0	0	0
T156	601	0	0	0
T167	0	2	0	0
T168	0	2	0	0
T169	0	5	0	0
T199	1004	0	0	0
T225	2245	0	0	0
T227	535	0	0	0
T270	765	0	0	0
T271	580	0	0	0
T272	670	0	0	0
T348	0	1	0	0
T350	0	1	0	0
T374	0	1	0	0