Unified Coverage Report :: Module :: uart

Module : uart

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_uart_0.1/rtl/uart.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_uart0	100.00			100.00
tb.dut.top_earlgrey.u_uart1	100.00			100.00
tb.dut.top_earlgrey.u_uart2	100.00			100.00
tb.dut.top_earlgrey.u_uart3	100.00			100.00

---

Module Instance : tb.dut.top_earlgrey.u_uart0

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart1

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart2

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_uart3

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
94.73	90.65		93.54			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Toggle Coverage for Module : uart

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T43,T86	Yes	T32,T43,T86	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T43,T86	Yes	T32,T43,T86	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T6,*T61,*T79	Yes	T6,T61,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T79,T80	Yes	T61,T79,T80	INPUT
tl_i.a_valid	Yes	Yes	T32,T43,T86	Yes	T32,T43,T86	INPUT
tl_o.a_ready	Yes	Yes	T43,T86,T44	Yes	T43,T86,T44	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T86,T112,T152	Yes	T86,T112,T152	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T86,T112,T152	Yes	T43,T86,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T86,T112,T152	Yes	T43,T86,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T198,*T77,*T81	Yes	T198,T77,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T86,*T112,*T152	Yes	T86,T112,T152	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T86,T44	Yes	T43,T86,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T107,T108,T110	Yes	T107,T108,T110	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T107,T83,T262	Yes	T107,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T107,T83,T84	Yes	T107,T83,T262	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T107,T108,T110	Yes	T107,T108,T110	OUTPUT
cio_rx_i	Yes	Yes	T32,T86,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T86,T112,T152	Yes	T86,T112,T152	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T86,T112,T152	Yes	T86,T112,T152	OUTPUT
intr_rx_watermark_o	Yes	Yes	T86,T112,T152	Yes	T86,T112,T152	OUTPUT
intr_tx_empty_o	Yes	Yes	T86,T112,T152	Yes	T86,T112,T152	OUTPUT
intr_rx_overflow_o	Yes	Yes	T86,T112,T152	Yes	T86,T112,T152	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart0

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	302	302	100.00
Total Bits 0->1	151	151	100.00
Total Bits 1->0	151	151	100.00

Ports	39	39	100.00
Port Bits	302	302	100.00
Port Bits 0->1	151	151	100.00
Port Bits 1->0	151	151	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T32,T43,T86	Yes	T32,T43,T86	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T32,T43,T86	Yes	T32,T43,T86	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[29:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T6,*T61,*T79	Yes	T6,T61,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T79,T80	Yes	T61,T79,T80	INPUT
tl_i.a_valid	Yes	Yes	T32,T43,T86	Yes	T32,T43,T86	INPUT
tl_o.a_ready	Yes	Yes	T43,T86,T44	Yes	T43,T86,T44	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T86,T112,T643	Yes	T86,T112,T643	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T86,T112,T643	Yes	T43,T86,T44	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T86,T112,T643	Yes	T43,T86,T44	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T198,*T77,*T81	Yes	T198,T77,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T86,*T112,*T643	Yes	T86,T112,T643	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T43,T86,T44	Yes	T43,T86,T44	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T107,T121,T610	Yes	T107,T121,T610	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T107,T83,T84	Yes	T107,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T107,T83,T84	Yes	T107,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T107,T121,T610	Yes	T107,T121,T610	OUTPUT
cio_rx_i	Yes	Yes	T32,T86,T33	Yes	T1,T2,T3	INPUT
cio_tx_o	Yes	Yes	T86,T112,T5	Yes	T86,T112,T5	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T86,T112,T270	Yes	T86,T112,T270	OUTPUT
intr_rx_watermark_o	Yes	Yes	T86,T112,T270	Yes	T86,T112,T270	OUTPUT
intr_tx_empty_o	Yes	Yes	T86,T112,T270	Yes	T86,T112,T270	OUTPUT
intr_rx_overflow_o	Yes	Yes	T86,T112,T270	Yes	T86,T112,T270	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart1

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[16]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:17]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T6,*T61,*T79	Yes	T6,T61,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T79,T80	Yes	T61,T79,T80	INPUT
tl_i.a_valid	Yes	Yes	T121,T181,T225	Yes	T121,T181,T225	INPUT
tl_o.a_ready	Yes	Yes	T121,T181,T225	Yes	T121,T181,T225	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T121,T181,T225	Yes	T121,T181,T225	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T121,T181,T225	Yes	T121,T181,T225	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T198,*T77,*T81	Yes	T198,T77,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T181,*T270,*T182	Yes	T181,T270,T182	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T121,T181,T225	Yes	T121,T181,T225	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T107,T108,T110	Yes	T107,T108,T110	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T107,T83,T262	Yes	T107,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T107,T83,T84	Yes	T107,T83,T262	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T107,T108,T110	Yes	T107,T108,T110	OUTPUT
cio_rx_i	Yes	Yes	T181,T182,T35	Yes	T181,T7,T182	INPUT
cio_tx_o	Yes	Yes	T181,T182,T183	Yes	T181,T182,T183	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	OUTPUT
intr_rx_watermark_o	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	OUTPUT
intr_tx_empty_o	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	OUTPUT
intr_rx_overflow_o	Yes	Yes	T181,T270,T182	Yes	T181,T270,T182	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart2

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	304	304	100.00
Total Bits 0->1	152	152	100.00
Total Bits 1->0	152	152	100.00

Ports	39	39	100.00
Port Bits	304	304	100.00
Port Bits 0->1	152	152	100.00
Port Bits 1->0	152	152	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[16:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T6,*T61,*T79	Yes	T6,T61,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T79,T80	Yes	T61,T79,T80	INPUT
tl_i.a_valid	Yes	Yes	T152,T121,T225	Yes	T152,T121,T225	INPUT
tl_o.a_ready	Yes	Yes	T152,T121,T225	Yes	T152,T121,T225	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T152,T121,T225	Yes	T152,T121,T225	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T152,T121,T225	Yes	T152,T121,T225	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T198,*T77,*T81	Yes	T198,T77,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T152,*T270,*T176	Yes	T152,T270,T176	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T152,T121,T225	Yes	T152,T121,T225	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T107,T121,T83	Yes	T107,T121,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T107,T83,T84	Yes	T107,T83,T84	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T107,T83,T84	Yes	T107,T83,T84	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T107,T121,T83	Yes	T107,T121,T83	OUTPUT
cio_rx_i	Yes	Yes	T152,T176,T319	Yes	T152,T176,T319	INPUT
cio_tx_o	Yes	Yes	T152,T176,T319	Yes	T152,T176,T319	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	OUTPUT
intr_rx_watermark_o	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	OUTPUT
intr_tx_empty_o	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	OUTPUT
intr_rx_overflow_o	Yes	Yes	T152,T270,T176	Yes	T152,T270,T176	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT

*Tests covering at least one bit in the range

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_uart3

	Total	Covered	Percent
Totals	39	39	100.00
Total Bits	306	306	100.00
Total Bits 0->1	153	153	100.00
Total Bits 1->0	153	153	100.00

Ports	39	39	100.00
Port Bits	306	306	100.00
Port Bits 0->1	153	153	100.00
Port Bits 1->0	153	153	100.00

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T32,T65,T33	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[5:0]	Yes	Yes	*T76,*T77,*T78	Yes	T76,T77,T78	INPUT
tl_i.a_address[15:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[17:16]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:18]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	Yes	Yes	*T6,*T61,*T79	Yes	T6,T61,T79	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	Yes	Yes	T61,T79,T80	Yes	T61,T79,T80	INPUT
tl_i.a_valid	Yes	Yes	T13,T121,T15	Yes	T13,T121,T15	INPUT
tl_o.a_ready	Yes	Yes	T13,T121,T15	Yes	T13,T121,T15	OUTPUT
tl_o.d_error	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_user.data_intg[6:0]	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	OUTPUT
tl_o.d_user.rsp_intg[6:0]	Yes	Yes	T13,T121,T15	Yes	T13,T121,T15	OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T13,T121,T15	Yes	T13,T121,T15	OUTPUT
tl_o.d_sink	Yes	Yes	T77,T81,T82	Yes	T77,T81,T82	OUTPUT
tl_o.d_source[5:0]	Yes	Yes	*T198,*T77,*T81	Yes	T198,T77,T81	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T76,T77,T78	Yes	T76,T77,T78	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	Yes	Yes	*T13,*T15,*T270	Yes	T13,T15,T270	OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T13,T121,T15	Yes	T13,T121,T15	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	Yes	Yes	T121,T611,T83	Yes	T121,T611,T83	INPUT
alert_rx_i[0].ping_n	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_rx_i[0].ping_p	Yes	Yes	T83,T84,T85	Yes	T83,T84,T85	INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	Yes	Yes	T121,T611,T83	Yes	T121,T611,T83	OUTPUT
cio_rx_i	Yes	Yes	T13,T15,T306	Yes	T13,T15,T306	INPUT
cio_tx_o	Yes	Yes	T13,T15,T306	Yes	T13,T15,T306	OUTPUT
cio_tx_en_o	Unreachable	Unreachable		Unreachable		OUTPUT
intr_tx_watermark_o	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	OUTPUT
intr_rx_watermark_o	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	OUTPUT
intr_tx_empty_o	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	OUTPUT
intr_rx_overflow_o	Yes	Yes	T13,T15,T270	Yes	T13,T15,T270	OUTPUT
intr_rx_frame_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_break_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_timeout_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT
intr_rx_parity_err_o	Yes	Yes	T270,T291,T303	Yes	T270,T291,T303	OUTPUT

*Tests covering at least one bit in the range