Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	0	38	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	1499561	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24112268

1

T1

350

T2

37244

T3

12256

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	16557051	1			T1	176		T2	25944		T3	5504
values[0x0]	7554264	1			T1	174		T2	11300		T3	6752
values[0x1]	1500514	1			T1	3		T2	2717		T3	950

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	8940	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

25602889

1

T1

353

T2

39961

T3

13206

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	12791651	1			T1	177		T2	19981		T3	6604
valid_sources[0x01]	12790911	1			T1	176		T2	19980		T3	6602
valid_sources[0x02]	377	1			T107	1		T30	30		T32	56
valid_sources[0x03]	232	1			T108	13		T30	48		T31	16
valid_sources[0x04]	536	1			T30	56		T32	64		T358	62
valid_sources[0x05]	278	1			T30	32		T32	50		T358	49
valid_sources[0x06]	283	1			T107	1		T30	52		T32	49
valid_sources[0x07]	418	1			T107	1		T30	52		T31	110
valid_sources[0x08]	307	1			T30	56		T31	16		T32	35
valid_sources[0x09]	179	1			T30	32		T32	2		T358	53
valid_sources[0x0a]	200	1			T30	41		T32	24		T358	31
valid_sources[0x0b]	2930	1			T30	45		T31	16		T32	7
valid_sources[0x0c]	309	1			T44	3		T107	2		T30	45
valid_sources[0x0d]	405	1			T70	39		T30	23		T32	40
valid_sources[0x0e]	309	1			T30	39		T32	83		T358	45
valid_sources[0x0f]	234	1			T107	2		T30	49		T32	29
valid_sources[0x10]	226	1			T107	1		T30	44		T31	16
valid_sources[0x11]	314	1			T108	10		T30	43		T31	16
valid_sources[0x12]	303	1			T30	46		T32	57		T358	33
valid_sources[0x13]	252	1			T30	48		T32	44		T358	58
valid_sources[0x14]	374	1			T30	39		T32	25		T358	60
valid_sources[0x15]	335	1			T44	17		T30	43		T31	16
valid_sources[0x16]	297	1			T107	2		T30	32		T32	30
valid_sources[0x17]	363	1			T30	44		T32	52		T358	37
valid_sources[0x18]	298	1			T107	3		T30	34		T32	59
valid_sources[0x19]	406	1			T30	44		T31	16		T32	41
valid_sources[0x1a]	287	1			T30	38		T31	16		T32	31
valid_sources[0x1b]	253	1			T30	33		T32	27		T358	64
valid_sources[0x1c]	344	1			T30	44		T32	75		T358	49
valid_sources[0x1d]	324	1			T30	48		T31	32		T32	8
valid_sources[0x1e]	232	1			T30	51		T32	18		T358	16
valid_sources[0x1f]	2146	1			T30	51		T32	66		T358	50
valid_sources[0x20]	267	1			T107	2		T30	33		T32	3

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

16557051

1

T1

176

T2

25944

T3

5504

values[0x0]

all_enables

biggest_size

7549640

1

T1

174

T2

11300

T3

6752

values[0x1]

all_enables

biggest_size

5577

1

T70

18

T52

22

T44

18