Total Module Definition Coverage Summary 

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.15	95.59	74.02	85.64		94.29	91.19

Total modules in report: 108

---

modlist.html | modlist1.html

---

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
prim_mubi4_dec	0.00	0.00
padring	50.44			50.44
pinmux_wkup	64.07	68.42	69.23			54.55
prim_packer_fifo	68.93	100.00	90.00			85.71	0.00
rv_plic_gateway	69.17	100.00	20.00			87.50
tlul_err_resp	79.42	92.31	68.18			77.78
pinmux	79.44	77.24	84.10	64.46		79.38	92.00
xbar_main	80.89			80.89
ast	80.94			80.94
spi_device	81.13			81.13
otp_ctrl	81.18			81.18
rv_dm	81.46			81.46
usbdev	82.84			82.84
top_earlgrey	83.03	90.65		58.44			100.00
entropy_src	83.08			83.08
tlul_err	83.23	96.15	74.29			62.50	100.00
hmac	83.54			83.54
spi_host	84.36			84.36
prim_generic_clock_mux2	85.19	100.00	55.56				100.00
flash_ctrl	85.85			85.85
lc_ctrl	86.69			86.69
chip_earlgrey_asic	87.01	66.67	100.00	94.37
rv_core_ibex	87.21	96.47	89.29	86.64		100.00	63.64
prim_reg_cdc_arb	88.49	94.00	86.05			73.91	100.00
prim_reg_cdc_arb	86.96					73.91	100.00
prim_reg_cdc_arb ( parameter DataWidth=10,ResetVal=0,DstWrReq=1 + DataWidth=4,ResetVal,DstWrReq=1 + DataWidth=1,ResetVal=0,DstWrReq=1 + DataWidth=14,ResetVal=0,DstWrReq=1 + DataWidth=28,ResetVal=0,DstWrReq=1 + DataWidth=9,ResetVal=0,DstWrReq=1 + DataWidth=5,ResetVal=0,DstWrReq=1 + DataWidth=8,ResetVal=0,DstWrReq=1 + DataWidth=32,ResetVal=0,DstWrReq=1 )	80.05	88.00	72.09
prim_reg_cdc_arb ( parameter DataWidth=2,ResetVal=0,DstWrReq=0 + DataWidth=20,ResetVal,DstWrReq=0 + DataWidth=18,ResetVal=118010,DstWrReq=0 + DataWidth=16,ResetVal,DstWrReq=0 + DataWidth=1,ResetVal=0,DstWrReq=0 + DataWidth=12,ResetVal=0,DstWrReq=0 + DataWidth=8,ResetVal,DstWrReq=0 + DataWidth=14,ResetVal=0,DstWrReq=0 + DataWidth=17,ResetVal=2000,DstWrReq=0 + DataWidth=7,ResetVal=0,DstWrReq=0 + DataWidth=5,ResetVal=0,DstWrReq=0 + DataWidth=32,ResetVal,DstWrReq=0 + DataWidth=4,ResetVal=0,DstWrReq=0 + DataWidth=9,ResetVal=0,DstWrReq=0 + DataWidth=6,ResetVal=0,DstWrReq=0 + DataWidth=13,ResetVal=0,DstWrReq=0 )	100.00	100.00	100.00
tlul_adapter_host	89.09	91.11	75.79			89.44	100.00
tlul_adapter_host	100.00						100.00
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )	87.89	91.30	82.35			90.00
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )	83.01	90.91	69.23			88.89
keymgr	89.24			89.24
rv_timer	89.73			89.73
xbar_peri	89.79			89.79
aon_timer	89.81			89.81
pattgen	90.00			90.00
adc_ctrl	90.12			90.12
pwm	90.20			90.20
uart	90.20			90.20
i2c	90.24			90.24
sysrst_ctrl	91.02			91.02
prim_max_tree	91.31	88.49	76.75			100.00	100.00
tlul_rsp_intg_gen	91.67	83.33					100.00
tlul_rsp_intg_gen	100.00						100.00
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=0,EnableDataIntgGen=0 )	66.67	66.67
tlul_rsp_intg_gen ( parameter EnableRspIntgGen=1,EnableDataIntgGen=1 )	100.00	100.00
prim_sync_reqack	91.67	100.00	66.67			100.00	100.00
rv_core_ibex_cfg_reg_top	91.91	99.44	71.06			97.14	100.00
pinmux_reg_top	92.28	99.61	69.50			100.00	100.00
rv_plic_reg_top	92.38	100.00	69.99			99.51	100.00
rstmgr	92.89			92.89
sensor_ctrl	93.03	90.41	81.36	93.39		100.00	100.00
tlul_socket_1n	93.04	91.07	86.36			94.74	100.00
tlul_rsp_intg_chk	93.33	100.00	80.00				100.00
pwrmgr	93.48			93.48
gpio	94.07			94.07
tlul_adapter_reg	94.24	97.37	79.59			100.00	100.00
sensor_ctrl_reg_top	94.28	100.00	77.12			100.00	100.00
ibex_top	94.28			94.28
sram_ctrl	94.30			94.30
rom_ctrl	94.69			94.69
clkmgr	94.93			94.93
edn	95.61			95.61
rv_plic	96.10	99.82	100.00	90.68		100.00	90.00
prim_edn_req	96.15	100.00	84.62			100.00	100.00
prim_generic_usb_diff_rx	96.30	100.00	88.89			100.00
prim_arbiter_fixed	96.55	100.00	93.33			100.00	92.86
aes	96.62			96.62
usbdev_aon_wake	96.71	100.00	92.11			94.74	100.00
csrng	97.03			97.03
alert_handler	97.21			97.21
prim_reg_cdc	97.25	100.00	89.01			100.00	100.00
prim_reg_cdc	100.00	100.00				100.00	100.00
prim_reg_cdc ( parameter DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=0,TxnWidth=3 + DataWidth=1,ResetVal=0,BitMask=1,DstWrReq=1,TxnWidth=3 )	92.31		92.31
prim_reg_cdc ( parameter DataWidth=2,ResetVal=0,BitMask=3,DstWrReq=0,TxnWidth=3 + DataWidth=10,ResetVal=0,BitMask=769,DstWrReq=1,TxnWidth=3 + DataWidth=4,ResetVal,BitMask=15,DstWrReq=1,TxnWidth=3 + DataWidth=20,ResetVal,BitMask=1048575,DstWrReq=0,TxnWidth=3 + DataWidth=18,ResetVal=118010,BitMask=262143,DstWrReq=0,TxnWidth=3 + DataWidth=16,ResetVal,BitMask=65535,DstWrReq=0,TxnWidth=3 + DataWidth=12,ResetVal=0,BitMask=4095,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal,BitMask=255,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=0,TxnWidth=3 + DataWidth=17,ResetVal=2000,BitMask=131071,DstWrReq=0,TxnWidth=3 + DataWidth=7,ResetVal=0,BitMask=119,DstWrReq=0,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal,BitMask,DstWrReq=0,TxnWidth=3 + DataWidth=4,ResetVal=0,BitMask=15,DstWrReq=0,TxnWidth=3 + DataWidth=14,ResetVal=0,BitMask=16383,DstWrReq=1,TxnWidth=3 + DataWidth=28,ResetVal=0,BitMask=268374015,DstWrReq=1,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=0,TxnWidth=3 + DataWidth=9,ResetVal=0,BitMask=511,DstWrReq=1,TxnWidth=3 + DataWidth=5,ResetVal=0,BitMask=31,DstWrReq=1,TxnWidth=3 + DataWidth=6,ResetVal=0,BitMask=63,DstWrReq=0,TxnWidth=3 + DataWidth=8,ResetVal=0,BitMask=255,DstWrReq=1,TxnWidth=3 + DataWidth=13,ResetVal=0,BitMask=8191,DstWrReq=0,TxnWidth=3 + DataWidth=32,ResetVal=0,BitMask=-1,DstWrReq=1,TxnWidth=3 )	85.71		85.71
otbn	97.31			97.31
kmac	98.28			98.28
pinmux_strap_sampling	99.83	99.34	100.00			100.00	100.00
prim_lc_sync	100.00	100.00					100.00
prim_lc_sync	100.00						100.00
prim_lc_sync ( parameter NumCopies=1,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=2,AsyncOn=1,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=3,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sync ( parameter NumCopies=4,AsyncOn=0,ResetValueIsOn=0,LcResetValue=10 )	100.00	100.00
prim_lc_sender	100.00	100.00
tlul_data_integ_dec	100.00	100.00
tlul_cmd_intg_chk	100.00	100.00					100.00
prim_alert_sender	100.00			100.00
tlul_cmd_intg_gen	100.00	100.00					100.00
tlul_fifo_sync	100.00		100.00			100.00
prim_edge_detector	100.00	100.00	100.00			100.00
clk_ctrl_and_main_pd_sva_if	100.00			100.00
prim_subreg	100.00	100.00	100.00			100.00
prim_subreg	100.00	100.00				100.00
prim_subreg ( parameter DW=1,SwAccess=1,RESVAL,Mubi=0 + DW=1,SwAccess=3,RESVAL,Mubi=0 + DW=1,SwAccess=0,RESVAL,Mubi=0 + DW=1,SwAccess=4,RESVAL=0,Mubi=0 + DW=1,SwAccess=5,RESVAL,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=2,SwAccess=0,RESVAL,Mubi=0 + DW=2,SwAccess=1,RESVAL=0,Mubi=0 + DW=2,SwAccess=3,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=3,SwAccess=0,RESVAL,Mubi=0 + DW=3,SwAccess=1,RESVAL,Mubi=0 + DW=3,SwAccess=3,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=32,SwAccess=1,RESVAL,Mubi=0 + DW=32,SwAccess=0,RESVAL,Mubi=0 + DW=32,SwAccess=3,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=4,SwAccess=0,RESVAL,Mubi + DW=4,SwAccess=1,RESVAL=0,Mubi=0 + DW=4,SwAccess=3,RESVAL=9,Mubi=1 + DW=4,SwAccess=4,RESVAL=9,Mubi=1 )	100.00		100.00
prim_subreg ( parameter DW=6,SwAccess=0,RESVAL,Mubi=0 + DW=6,SwAccess=1,RESVAL=0,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=7,SwAccess=0,RESVAL,Mubi=0 )	100.00		100.00
prim_subreg ( parameter DW=8,SwAccess=0,RESVAL,Mubi=0 + DW=8,SwAccess=1,RESVAL,Mubi=0 + DW=8,SwAccess=3,RESVAL=0,Mubi=0 )	100.00		100.00
prim_filter	100.00	100.00	100.00			100.00
pinmux_jtag_breakout	100.00	100.00		100.00
prim_lc_or_hardened	100.00	100.00	100.00				100.00
prim_generic_buf	100.00	100.00
prim_intr_hw	100.00	100.00	100.00			100.00	100.00
prim_pulse_sync	100.00	100.00	100.00			100.00	100.00
prim_fifo_sync	100.00	100.00					100.00
prim_subreg_arb	100.00	100.00	100.00			100.00
prim_subreg_arb	100.00					100.00
prim_subreg_arb ( parameter DW=1,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=1,SwAccess=3,Mubi=0 + DW=32,SwAccess=3,Mubi=0 + DW=3,SwAccess=3,Mubi=0 + DW=10,SwAccess=3,Mubi=0 + DW=5,SwAccess=3,Mubi=0 + DW=8,SwAccess=3,Mubi=0 + DW=2,SwAccess=3,Mubi=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=1,SwAccess=4,Mubi=0 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=1,SwAccess=5,Mubi=0 + DW=16,SwAccess=5,Mubi=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=2,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=3,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=32,SwAccess=0,Mubi=0 + DW=1,SwAccess=0,Mubi=0 + DW=2,SwAccess=0,Mubi=0 + DW=16,SwAccess=0,Mubi=0 + DW=8,SwAccess=0,Mubi=0 + DW=3,SwAccess=0,Mubi=0 + DW=24,SwAccess=0,Mubi=0 + DW=10,SwAccess=0,Mubi=0 + DW=4,SwAccess=0,Mubi=1 + DW=12,SwAccess=0,Mubi=0 + DW=31,SwAccess=0,Mubi=0 + DW=7,SwAccess=0,Mubi=0 + DW=6,SwAccess=0,Mubi=0 + DW=11,SwAccess=0,Mubi=0 + DW=5,SwAccess=0,Mubi=0 + DW=9,SwAccess=0,Mubi=0 + DW=27,SwAccess=0,Mubi=0 + DW=20,SwAccess=0,Mubi=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=32,SwAccess=1,Mubi=0 + DW=1,SwAccess=1,Mubi=0 + DW=5,SwAccess=1,Mubi=0 + DW=9,SwAccess=1,Mubi=0 + DW=8,SwAccess=1,Mubi=0 + DW=3,SwAccess=1,Mubi=0 + DW=6,SwAccess=1,Mubi=0 + DW=4,SwAccess=1,Mubi=0 + DW=2,SwAccess=1,Mubi=0 + DW=10,SwAccess=1,Mubi=0 + DW=20,SwAccess=1,Mubi=0 )	100.00	100.00
prim_subreg_arb ( parameter DW=4,SwAccess=0,Mubi=1 )	100.00		100.00
prim_subreg_arb ( parameter DW=4,SwAccess=4,Mubi=1 )	100.00	100.00	100.00
prim_subreg_arb ( parameter DW=6,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=7,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_arb ( parameter DW=8,SwAccess=0,Mubi=0 )	100.00		100.00
prim_subreg_ext	100.00	100.00
prim_secded_inv_39_32_enc	100.00	100.00
prim_esc_receiver	100.00			100.00
prim_secded_inv_64_57_enc	100.00	100.00
prim_generic_pad_wrapper	100.00	100.00	100.00			100.00	100.00
prim_generic_pad_wrapper	100.00						100.00
prim_generic_pad_wrapper ( parameter PadType=0,ScanRole=0 )	100.00	100.00	100.00			100.00
prim_generic_pad_wrapper ( parameter PadType=3,ScanRole=0 )	100.00	100.00	100.00			100.00
prim_generic_pad_wrapper ( parameter PadType=4,ScanRole=0 )	100.00	100.00
prim_sync_reqack_data	100.00	100.00					100.00
rv_core_addr_trans	100.00	100.00	100.00			100.00
prim_generic_flop	100.00	100.00				100.00
rv_plic_target	100.00	100.00	100.00			100.00
prim_mubi4_sync	100.00						100.00
prim_generic_clock_buf	100.00	100.00
pinmux_jtag_buf
prim_usb_diff_rx
prim_clock_buf
tlul_data_integ_enc
prim_reg_we_check