| SCORE |
LINE |
COND |
TOGGLE |
FSM |
BRANCH |
ASSERT |
GROUP |
|
| TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | TOTAL | INCR | NAME |
| 40.27 |
40.27 |
39.66 |
39.66 |
39.61 |
39.61 |
37.04 |
37.04 |
|
|
56.19 |
56.19 |
62.11 |
62.11 |
7.03 |
7.03 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4144011962 |
| 50.23 |
9.96 |
47.62 |
7.96 |
48.35 |
8.74 |
40.16 |
3.12 |
|
|
64.21 |
8.03 |
89.83 |
27.73 |
11.21 |
4.18 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3765571048 |
| 59.23 |
9.00 |
47.72 |
0.10 |
48.46 |
0.11 |
44.47 |
4.32 |
|
|
64.25 |
0.04 |
90.02 |
0.18 |
60.44 |
49.23 |
/workspace/coverage/default/2.chip_sw_alert_test.904356234 |
| 66.72 |
7.49 |
65.52 |
17.80 |
59.31 |
10.86 |
47.51 |
3.04 |
|
|
76.40 |
12.15 |
91.13 |
1.11 |
60.44 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1508258506 |
| 71.71 |
5.00 |
76.22 |
10.71 |
65.06 |
5.75 |
51.47 |
3.96 |
|
|
79.38 |
2.97 |
91.13 |
0.00 |
67.03 |
6.59 |
/workspace/coverage/pad_ctrl_test_mode/6.chip_padctrl_attributes.3513460239 |
| 74.72 |
3.01 |
81.62 |
5.39 |
70.96 |
5.90 |
53.02 |
1.55 |
|
|
84.57 |
5.20 |
91.13 |
0.00 |
67.03 |
0.00 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2055691870 |
| 76.62 |
1.90 |
81.72 |
0.11 |
71.00 |
0.04 |
63.82 |
10.81 |
|
|
84.60 |
0.02 |
91.31 |
0.18 |
67.25 |
0.22 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3974286650 |
| 78.28 |
1.66 |
83.65 |
1.93 |
73.55 |
2.55 |
67.31 |
3.48 |
|
|
86.42 |
1.83 |
91.50 |
0.18 |
67.25 |
0.00 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.2930071633 |
| 79.65 |
1.37 |
86.15 |
2.50 |
75.53 |
1.98 |
68.65 |
1.34 |
|
|
88.81 |
2.39 |
91.50 |
0.00 |
67.25 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2988128269 |
| 81.00 |
1.35 |
86.15 |
0.00 |
75.53 |
0.00 |
76.77 |
8.12 |
|
|
88.81 |
0.00 |
91.50 |
0.00 |
67.25 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.724664825 |
| 82.08 |
1.07 |
87.85 |
1.70 |
77.91 |
2.38 |
77.01 |
0.24 |
|
|
90.94 |
2.12 |
91.50 |
0.00 |
67.25 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.600671291 |
| 82.89 |
0.81 |
88.22 |
0.37 |
78.09 |
0.19 |
77.05 |
0.04 |
|
|
91.15 |
0.22 |
95.56 |
4.07 |
67.25 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2562371533 |
| 83.54 |
0.65 |
88.23 |
0.01 |
78.10 |
0.01 |
80.91 |
3.87 |
|
|
91.15 |
0.00 |
95.56 |
0.00 |
67.25 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1827612130 |
| 84.01 |
0.48 |
89.04 |
0.81 |
79.00 |
0.90 |
81.22 |
0.31 |
|
|
91.79 |
0.64 |
95.56 |
0.00 |
67.47 |
0.22 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1732621923 |
| 84.46 |
0.45 |
89.68 |
0.64 |
79.66 |
0.67 |
81.89 |
0.67 |
|
|
92.49 |
0.70 |
95.56 |
0.00 |
67.47 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2433263162 |
| 84.81 |
0.35 |
90.20 |
0.52 |
80.13 |
0.47 |
82.12 |
0.23 |
|
|
92.83 |
0.34 |
96.12 |
0.55 |
67.47 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2341660983 |
| 85.12 |
0.30 |
90.24 |
0.03 |
80.14 |
0.01 |
82.17 |
0.05 |
|
|
92.84 |
0.01 |
96.30 |
0.18 |
69.01 |
1.54 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.75742948 |
| 85.41 |
0.29 |
90.71 |
0.47 |
80.68 |
0.54 |
82.64 |
0.47 |
|
|
93.11 |
0.27 |
96.30 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2605496842 |
| 85.69 |
0.28 |
91.13 |
0.42 |
81.41 |
0.72 |
83.08 |
0.44 |
|
|
93.22 |
0.11 |
96.30 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1490694090 |
| 85.97 |
0.28 |
91.13 |
0.00 |
81.42 |
0.01 |
84.74 |
1.66 |
|
|
93.22 |
0.00 |
96.30 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1532603767 |
| 86.19 |
0.22 |
91.58 |
0.45 |
81.72 |
0.30 |
85.05 |
0.31 |
|
|
93.47 |
0.25 |
96.30 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1015004091 |
| 86.33 |
0.15 |
91.67 |
0.09 |
82.09 |
0.37 |
85.09 |
0.04 |
|
|
93.84 |
0.37 |
96.30 |
0.00 |
69.01 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1613248618 |
| 86.48 |
0.14 |
91.75 |
0.08 |
82.18 |
0.09 |
85.31 |
0.22 |
|
|
93.90 |
0.06 |
96.49 |
0.18 |
69.23 |
0.22 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3571425192 |
| 86.59 |
0.11 |
91.75 |
0.00 |
82.18 |
0.00 |
85.97 |
0.66 |
|
|
93.90 |
0.00 |
96.49 |
0.00 |
69.23 |
0.00 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.859297254 |
| 86.70 |
0.11 |
91.76 |
0.01 |
82.24 |
0.06 |
86.34 |
0.38 |
|
|
93.92 |
0.02 |
96.67 |
0.18 |
69.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.894265702 |
| 86.80 |
0.10 |
91.76 |
0.00 |
82.24 |
0.00 |
86.95 |
0.61 |
|
|
93.92 |
0.00 |
96.67 |
0.00 |
69.23 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.805462230 |
| 86.90 |
0.10 |
92.21 |
0.44 |
82.29 |
0.05 |
87.06 |
0.11 |
|
|
93.92 |
0.00 |
96.67 |
0.00 |
69.23 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.786083274 |
| 86.98 |
0.08 |
92.23 |
0.03 |
82.32 |
0.03 |
87.08 |
0.01 |
|
|
93.96 |
0.03 |
96.86 |
0.18 |
69.45 |
0.22 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.767371765 |
| 87.07 |
0.08 |
92.40 |
0.17 |
82.48 |
0.16 |
87.11 |
0.04 |
|
|
94.10 |
0.14 |
96.86 |
0.00 |
69.45 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2475884238 |
| 87.14 |
0.08 |
92.41 |
0.01 |
82.50 |
0.02 |
87.11 |
0.00 |
|
|
94.12 |
0.02 |
97.04 |
0.18 |
69.67 |
0.22 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.1630648568 |
| 87.22 |
0.07 |
92.42 |
0.01 |
82.52 |
0.03 |
87.11 |
0.00 |
|
|
94.13 |
0.01 |
97.23 |
0.18 |
69.89 |
0.22 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2324280427 |
| 87.29 |
0.07 |
92.42 |
0.00 |
82.52 |
0.00 |
87.55 |
0.44 |
|
|
94.13 |
0.00 |
97.23 |
0.00 |
69.89 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3065548336 |
| 87.35 |
0.06 |
92.45 |
0.03 |
82.54 |
0.01 |
87.61 |
0.06 |
|
|
94.14 |
0.01 |
97.23 |
0.00 |
70.11 |
0.22 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3759974704 |
| 87.39 |
0.05 |
92.53 |
0.08 |
82.59 |
0.05 |
87.68 |
0.07 |
|
|
94.23 |
0.09 |
97.23 |
0.00 |
70.11 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2857914309 |
| 87.44 |
0.05 |
92.54 |
0.01 |
82.62 |
0.03 |
87.69 |
0.01 |
|
|
94.26 |
0.02 |
97.23 |
0.00 |
70.33 |
0.22 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.446207999 |
| 87.49 |
0.05 |
92.59 |
0.06 |
82.65 |
0.03 |
87.86 |
0.17 |
|
|
94.27 |
0.02 |
97.23 |
0.00 |
70.33 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1862899562 |
| 87.53 |
0.04 |
92.59 |
0.00 |
82.65 |
0.00 |
87.88 |
0.02 |
|
|
94.27 |
0.00 |
97.23 |
0.00 |
70.55 |
0.22 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.2102205204 |
| 87.57 |
0.04 |
92.60 |
0.01 |
82.75 |
0.10 |
87.89 |
0.02 |
|
|
94.39 |
0.12 |
97.23 |
0.00 |
70.55 |
0.00 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.934105160 |
| 87.61 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.91 |
0.02 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
70.77 |
0.22 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.4220341337 |
| 87.65 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.01 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
70.99 |
0.22 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2803934327 |
| 87.68 |
0.04 |
92.60 |
0.00 |
82.75 |
0.01 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
71.21 |
0.22 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2755617505 |
| 87.72 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.01 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
71.43 |
0.22 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1338486829 |
| 87.76 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.01 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
71.65 |
0.22 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3215089867 |
| 87.79 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.01 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
71.87 |
0.22 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1163296418 |
| 87.83 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
72.09 |
0.22 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290979130 |
| 87.87 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
72.31 |
0.22 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1012393287 |
| 87.90 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
72.53 |
0.22 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.480557458 |
| 87.94 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
72.75 |
0.22 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.3909253589 |
| 87.98 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
72.97 |
0.22 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2634496510 |
| 88.01 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
73.19 |
0.22 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.3645483516 |
| 88.05 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
73.41 |
0.22 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120194758 |
| 88.09 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
73.63 |
0.22 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3139601515 |
| 88.12 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
73.85 |
0.22 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4082062801 |
| 88.16 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
74.07 |
0.22 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.380058065 |
| 88.20 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
74.29 |
0.22 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1944309944 |
| 88.23 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
74.51 |
0.22 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.941185669 |
| 88.27 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
74.73 |
0.22 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309556495 |
| 88.31 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
74.95 |
0.22 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.46186244 |
| 88.34 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
75.16 |
0.22 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.87992173 |
| 88.38 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
75.38 |
0.22 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.4168336768 |
| 88.42 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
75.60 |
0.22 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.917132920 |
| 88.45 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
75.82 |
0.22 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231771031 |
| 88.49 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
76.04 |
0.22 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078137867 |
| 88.53 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
76.26 |
0.22 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2746371898 |
| 88.56 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
76.48 |
0.22 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3889309841 |
| 88.60 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
76.70 |
0.22 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.650049634 |
| 88.64 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
76.92 |
0.22 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2109867041 |
| 88.67 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
77.14 |
0.22 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.3527799566 |
| 88.71 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
77.36 |
0.22 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1999006919 |
| 88.75 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
77.58 |
0.22 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2769718218 |
| 88.78 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
77.80 |
0.22 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1716956199 |
| 88.82 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
78.02 |
0.22 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2055684470 |
| 88.86 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
78.24 |
0.22 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.953023014 |
| 88.89 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
78.46 |
0.22 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.702766277 |
| 88.93 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
78.68 |
0.22 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040402202 |
| 88.97 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
78.90 |
0.22 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.490033293 |
| 89.00 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
79.12 |
0.22 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800064782 |
| 89.04 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
79.34 |
0.22 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1862600373 |
| 89.08 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
79.56 |
0.22 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.871061220 |
| 89.11 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
79.78 |
0.22 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583799059 |
| 89.15 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
80.00 |
0.22 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.798118919 |
| 89.19 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
80.22 |
0.22 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2249343104 |
| 89.22 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
80.44 |
0.22 |
/workspace/coverage/default/48.chip_sw_alert_handler_lpg_sleep_mode_alerts.1288401562 |
| 89.26 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
80.66 |
0.22 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2364779630 |
| 89.30 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
80.88 |
0.22 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1257142972 |
| 89.33 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
81.10 |
0.22 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4201612335 |
| 89.37 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
81.32 |
0.22 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2387055871 |
| 89.41 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
81.54 |
0.22 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411875047 |
| 89.44 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
81.76 |
0.22 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2415478556 |
| 89.48 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
81.98 |
0.22 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178981075 |
| 89.52 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
82.20 |
0.22 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.979783809 |
| 89.55 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
82.42 |
0.22 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2227054993 |
| 89.59 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
82.64 |
0.22 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.235557821 |
| 89.63 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
82.86 |
0.22 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3701956609 |
| 89.66 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
83.08 |
0.22 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2973413514 |
| 89.70 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
83.30 |
0.22 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791987134 |
| 89.73 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
83.52 |
0.22 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1643828140 |
| 89.77 |
0.04 |
92.60 |
0.00 |
82.75 |
0.00 |
87.92 |
0.00 |
|
|
94.39 |
0.00 |
97.23 |
0.00 |
83.74 |
0.22 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2894193410 |
| 89.81 |
0.04 |
92.67 |
0.08 |
82.75 |
0.00 |
88.05 |
0.13 |
|
|
94.40 |
0.01 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/4.chip_tap_straps_rma.1382355734 |
| 89.84 |
0.03 |
92.67 |
0.00 |
82.94 |
0.18 |
88.05 |
0.00 |
|
|
94.40 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.315200540 |
| 89.87 |
0.03 |
92.69 |
0.02 |
82.94 |
0.01 |
88.20 |
0.15 |
|
|
94.40 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.358106122 |
| 89.89 |
0.03 |
92.69 |
0.00 |
82.94 |
0.00 |
88.37 |
0.17 |
|
|
94.40 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1961033607 |
| 89.92 |
0.03 |
92.76 |
0.06 |
82.97 |
0.03 |
88.38 |
0.01 |
|
|
94.45 |
0.05 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3527608659 |
| 89.94 |
0.02 |
92.82 |
0.06 |
83.04 |
0.07 |
88.38 |
0.00 |
|
|
94.47 |
0.02 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1818764793 |
| 89.97 |
0.02 |
92.87 |
0.06 |
83.10 |
0.07 |
88.38 |
0.00 |
|
|
94.50 |
0.02 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3616061144 |
| 89.99 |
0.02 |
92.91 |
0.04 |
83.14 |
0.03 |
88.41 |
0.03 |
|
|
94.54 |
0.04 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4132307222 |
| 90.01 |
0.02 |
92.92 |
0.01 |
83.14 |
0.01 |
88.53 |
0.12 |
|
|
94.54 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2822991042 |
| 90.04 |
0.02 |
92.92 |
0.00 |
83.14 |
0.00 |
88.65 |
0.13 |
|
|
94.54 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3374596501 |
| 90.06 |
0.02 |
92.92 |
0.00 |
83.14 |
0.01 |
88.77 |
0.12 |
|
|
94.54 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1568266805 |
| 90.07 |
0.02 |
92.92 |
0.00 |
83.14 |
0.00 |
88.88 |
0.11 |
|
|
94.54 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.164380 |
| 90.09 |
0.02 |
92.92 |
0.00 |
83.14 |
0.00 |
88.99 |
0.11 |
|
|
94.54 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_jtag_mem_access.3760527853 |
| 90.11 |
0.02 |
92.94 |
0.02 |
83.17 |
0.03 |
89.02 |
0.03 |
|
|
94.56 |
0.02 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2715176920 |
| 90.13 |
0.02 |
92.94 |
0.00 |
83.17 |
0.00 |
89.12 |
0.10 |
|
|
94.56 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2659978975 |
| 90.14 |
0.02 |
92.94 |
0.00 |
83.27 |
0.10 |
89.12 |
0.00 |
|
|
94.56 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2117129084 |
| 90.16 |
0.02 |
92.95 |
0.01 |
83.27 |
0.01 |
89.21 |
0.08 |
|
|
94.56 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1796676301 |
| 90.17 |
0.02 |
92.95 |
0.00 |
83.27 |
0.00 |
89.30 |
0.09 |
|
|
94.56 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3824043256 |
| 90.19 |
0.01 |
92.95 |
0.00 |
83.36 |
0.09 |
89.30 |
0.00 |
|
|
94.56 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.191708223 |
| 90.20 |
0.01 |
92.97 |
0.03 |
83.38 |
0.02 |
89.31 |
0.01 |
|
|
94.59 |
0.02 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1613469836 |
| 90.21 |
0.01 |
93.00 |
0.02 |
83.38 |
0.00 |
89.36 |
0.05 |
|
|
94.59 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.591152339 |
| 90.22 |
0.01 |
93.00 |
0.00 |
83.40 |
0.02 |
89.40 |
0.04 |
|
|
94.59 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_gpio.4222668042 |
| 90.23 |
0.01 |
93.02 |
0.03 |
83.41 |
0.01 |
89.40 |
0.00 |
|
|
94.61 |
0.02 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.168037246 |
| 90.24 |
0.01 |
93.02 |
0.00 |
83.46 |
0.04 |
89.40 |
0.00 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2892214859 |
| 90.25 |
0.01 |
93.04 |
0.02 |
83.46 |
0.00 |
89.42 |
0.02 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3946903193 |
| 90.25 |
0.01 |
93.04 |
0.00 |
83.46 |
0.00 |
89.46 |
0.04 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3336228126 |
| 90.26 |
0.01 |
93.04 |
0.00 |
83.50 |
0.04 |
89.46 |
0.00 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2619582237 |
| 90.27 |
0.01 |
93.08 |
0.03 |
83.50 |
0.01 |
89.46 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.4285435607 |
| 90.27 |
0.01 |
93.08 |
0.00 |
83.50 |
0.00 |
89.50 |
0.04 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3195491276 |
| 90.28 |
0.01 |
93.08 |
0.00 |
83.50 |
0.00 |
89.53 |
0.03 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2429591355 |
| 90.28 |
0.01 |
93.08 |
0.01 |
83.51 |
0.01 |
89.54 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4134781402 |
| 90.29 |
0.01 |
93.09 |
0.01 |
83.52 |
0.01 |
89.55 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.99497432 |
| 90.29 |
0.01 |
93.09 |
0.00 |
83.54 |
0.02 |
89.55 |
0.00 |
|
|
94.61 |
0.01 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/pad_ctrl_test_mode/0.chip_padctrl_attributes.2184348408 |
| 90.30 |
0.01 |
93.09 |
0.00 |
83.56 |
0.02 |
89.56 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3072379713 |
| 90.30 |
0.01 |
93.09 |
0.00 |
83.58 |
0.02 |
89.57 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.4287061700 |
| 90.31 |
0.01 |
93.09 |
0.00 |
83.59 |
0.01 |
89.58 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.778049783 |
| 90.31 |
0.01 |
93.09 |
0.00 |
83.61 |
0.02 |
89.58 |
0.00 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1759458600 |
| 90.31 |
0.01 |
93.10 |
0.01 |
83.61 |
0.00 |
89.59 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.995617283 |
| 90.32 |
0.01 |
93.10 |
0.01 |
83.62 |
0.01 |
89.60 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3440002510 |
| 90.32 |
0.01 |
93.10 |
0.00 |
83.62 |
0.00 |
89.61 |
0.02 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.307737080 |
| 90.32 |
0.01 |
93.10 |
0.00 |
83.64 |
0.02 |
89.61 |
0.00 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_gpio.2636605747 |
| 90.33 |
0.01 |
93.10 |
0.00 |
83.64 |
0.00 |
89.63 |
0.02 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1298547626 |
| 90.33 |
0.01 |
93.10 |
0.00 |
83.64 |
0.00 |
89.65 |
0.02 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_init.2408644828 |
| 90.33 |
0.01 |
93.10 |
0.00 |
83.64 |
0.00 |
89.66 |
0.02 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1087055976 |
| 90.33 |
0.01 |
93.11 |
0.01 |
83.64 |
0.01 |
89.67 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.749910602 |
| 90.34 |
0.01 |
93.11 |
0.00 |
83.66 |
0.01 |
89.67 |
0.00 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1283969061 |
| 90.34 |
0.01 |
93.11 |
0.00 |
83.66 |
0.00 |
89.68 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1794653031 |
| 90.34 |
0.01 |
93.11 |
0.01 |
83.66 |
0.00 |
89.69 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.533605333 |
| 90.34 |
0.01 |
93.12 |
0.01 |
83.66 |
0.00 |
89.70 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.253689864 |
| 90.34 |
0.01 |
93.12 |
0.00 |
83.66 |
0.00 |
89.71 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3926230332 |
| 90.35 |
0.01 |
93.12 |
0.00 |
83.67 |
0.01 |
89.71 |
0.00 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3923056053 |
| 90.35 |
0.01 |
93.13 |
0.01 |
83.67 |
0.01 |
89.71 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.517644798 |
| 90.35 |
0.01 |
93.13 |
0.00 |
83.67 |
0.00 |
89.72 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3979865931 |
| 90.35 |
0.01 |
93.13 |
0.00 |
83.67 |
0.00 |
89.73 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1449180269 |
| 90.35 |
0.01 |
93.13 |
0.00 |
83.68 |
0.01 |
89.74 |
0.01 |
|
|
94.61 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1573141844 |
| 90.35 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.74 |
0.00 |
|
|
94.62 |
0.01 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/3.chip_tap_straps_dev.1978792092 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.01 |
89.74 |
0.00 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2019825531 |
| 90.36 |
0.01 |
93.13 |
0.01 |
83.68 |
0.00 |
89.74 |
0.00 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.3582657318 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.74 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2395904654 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.75 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.rom_keymgr_functest.523044471 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.76 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.434194710 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.76 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3592034653 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.77 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.255721224 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.68 |
0.00 |
89.77 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3378349315 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.69 |
0.01 |
89.77 |
0.00 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.4193974085 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.69 |
0.01 |
89.77 |
0.00 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2720670328 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.78 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.463400551 |
| 90.36 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.78 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.4184510490 |
| 90.37 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.78 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.2400292991 |
| 90.37 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.78 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.510224403 |
| 90.37 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.79 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/0.rom_raw_unlock.3597499297 |
| 90.37 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.79 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.2875341878 |
| 90.37 |
0.01 |
93.13 |
0.00 |
83.69 |
0.00 |
89.79 |
0.01 |
|
|
94.62 |
0.00 |
97.23 |
0.00 |
83.74 |
0.00 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.911535689 |
| Name |
| /workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.192182493 |
| /workspace/coverage/default/0.chip_sival_flash_info_access.3641154947 |
| /workspace/coverage/default/0.chip_sw_aes_enc.2519045857 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3220333373 |
| /workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2218460588 |
| /workspace/coverage/default/0.chip_sw_aes_entropy.2469773943 |
| /workspace/coverage/default/0.chip_sw_aes_idle.1870760957 |
| /workspace/coverage/default/0.chip_sw_aes_masking_off.347873116 |
| /workspace/coverage/default/0.chip_sw_aes_smoketest.4134214861 |
| /workspace/coverage/default/0.chip_sw_alert_handler_entropy.1986301502 |
| /workspace/coverage/default/0.chip_sw_alert_handler_escalation.1523787348 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1982923534 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1205432069 |
| /workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1461614351 |
| /workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1806464170 |
| /workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3061388052 |
| /workspace/coverage/default/0.chip_sw_alert_test.1679775840 |
| /workspace/coverage/default/0.chip_sw_aon_timer_irq.3074955273 |
| /workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2562834069 |
| /workspace/coverage/default/0.chip_sw_aon_timer_smoketest.2741489184 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.337636565 |
| /workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1935156727 |
| /workspace/coverage/default/0.chip_sw_ast_clk_outputs.480515880 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2318282193 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.434870657 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2922851437 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2052758281 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.781528510 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3176394290 |
| /workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4073467338 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter.3622901817 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.2512323136 |
| /workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4208249185 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1665621737 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1573049202 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1811613678 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2501273528 |
| /workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3144721016 |
| /workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.2703198213 |
| /workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3390442908 |
| /workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1416504666 |
| /workspace/coverage/default/0.chip_sw_csrng_kat_test.3784132959 |
| /workspace/coverage/default/0.chip_sw_csrng_smoketest.1228935162 |
| /workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3795237224 |
| /workspace/coverage/default/0.chip_sw_edn_kat.1420938978 |
| /workspace/coverage/default/0.chip_sw_edn_sw_mode.3944402502 |
| /workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.3203082607 |
| /workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3116812051 |
| /workspace/coverage/default/0.chip_sw_example_concurrency.4206120932 |
| /workspace/coverage/default/0.chip_sw_example_flash.2262570886 |
| /workspace/coverage/default/0.chip_sw_example_manufacturer.1143357388 |
| /workspace/coverage/default/0.chip_sw_example_rom.1871110840 |
| /workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1843943196 |
| /workspace/coverage/default/0.chip_sw_flash_crash_alert.337347780 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access.2747646684 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1778194554 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4146649882 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2209603693 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.176588026 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3880208857 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2867567304 |
| /workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3689472141 |
| /workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2920925249 |
| /workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3036114695 |
| /workspace/coverage/default/0.chip_sw_gpio_smoketest.4048001853 |
| /workspace/coverage/default/0.chip_sw_hmac_enc.82812257 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_idle.1707870815 |
| /workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1255227097 |
| /workspace/coverage/default/0.chip_sw_hmac_smoketest.3806519535 |
| /workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2982300157 |
| /workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.114485405 |
| /workspace/coverage/default/0.chip_sw_inject_scramble_seed.2204596842 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1122510959 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.443629219 |
| /workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2095682153 |
| /workspace/coverage/default/0.chip_sw_kmac_entropy.530881464 |
| /workspace/coverage/default/0.chip_sw_kmac_idle.3964537199 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_cshake.191196269 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac.340790897 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.3100813022 |
| /workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.435791250 |
| /workspace/coverage/default/0.chip_sw_kmac_smoketest.3393036409 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.1783575659 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3032519311 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.715527722 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3775905151 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2215080931 |
| /workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.871725419 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1280933164 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2751044596 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1799030083 |
| /workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2423285805 |
| /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2721476296 |
| /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1483256714 |
| /workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2244092597 |
| /workspace/coverage/default/0.chip_sw_otbn_mem_scramble.566667716 |
| /workspace/coverage/default/0.chip_sw_otbn_randomness.2992736785 |
| /workspace/coverage/default/0.chip_sw_otbn_smoketest.3126436046 |
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| /workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3581083285 |
| /workspace/coverage/default/2.chip_sw_sleep_pin_retention.1676703987 |
| /workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2088979945 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1954497800 |
| /workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.2829118532 |
| /workspace/coverage/default/2.chip_sw_spi_device_pass_through.3704334840 |
| /workspace/coverage/default/2.chip_sw_spi_device_tpm.1510449588 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3727586782 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.551476780 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.688345763 |
| /workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3377763354 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.213917959 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3601669619 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.666705905 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1734642535 |
| /workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.893688501 |
| /workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3919645277 |
| /workspace/coverage/default/2.chip_sw_uart_smoketest.1077471363 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx.2227174016 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3832698927 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2677097242 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2684767278 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3974469452 |
| /workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2907347994 |
| /workspace/coverage/default/2.chip_tap_straps_dev.952373698 |
| /workspace/coverage/default/2.chip_tap_straps_prod.1592052266 |
| /workspace/coverage/default/2.chip_tap_straps_rma.756461002 |
| /workspace/coverage/default/2.chip_tap_straps_testunlock0.3553875100 |
| /workspace/coverage/default/2.rom_e2e_asm_init_dev.3616903507 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod.2112209333 |
| /workspace/coverage/default/2.rom_e2e_asm_init_prod_end.563158793 |
| /workspace/coverage/default/2.rom_e2e_asm_init_rma.1117463369 |
| /workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.177498343 |
| /workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2399725243 |
| /workspace/coverage/default/2.rom_e2e_shutdown_output.79419647 |
| /workspace/coverage/default/2.rom_e2e_smoke.1529763356 |
| /workspace/coverage/default/2.rom_e2e_static_critical.237490966 |
| /workspace/coverage/default/2.rom_keymgr_functest.982351418 |
| /workspace/coverage/default/2.rom_raw_unlock.1131238514 |
| /workspace/coverage/default/2.rom_volatile_raw_unlock.2951791367 |
| /workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1024248095 |
| /workspace/coverage/default/22.chip_sw_all_escalation_resets.3218318982 |
| /workspace/coverage/default/24.chip_sw_all_escalation_resets.3543178901 |
| /workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3985926245 |
| /workspace/coverage/default/26.chip_sw_all_escalation_resets.3313316475 |
| /workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269435211 |
| /workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.3773434255 |
| /workspace/coverage/default/29.chip_sw_all_escalation_resets.616438156 |
| /workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.2124819098 |
| /workspace/coverage/default/3.chip_sw_data_integrity_escalation.2132817206 |
| /workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2211311942 |
| /workspace/coverage/default/3.chip_sw_uart_rand_baudrate.258600475 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx.2031826658 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2503253153 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3222866064 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3999508957 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2877462952 |
| /workspace/coverage/default/3.chip_sw_uart_tx_rx_idx3.1980249621 |
| /workspace/coverage/default/3.chip_tap_straps_prod.3824254127 |
| /workspace/coverage/default/3.chip_tap_straps_rma.1272375040 |
| /workspace/coverage/default/3.chip_tap_straps_testunlock0.272149349 |
| /workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765377714 |
| /workspace/coverage/default/30.chip_sw_all_escalation_resets.3445359662 |
| /workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3521337057 |
| /workspace/coverage/default/31.chip_sw_all_escalation_resets.746876101 |
| /workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199419499 |
| /workspace/coverage/default/33.chip_sw_all_escalation_resets.1411587350 |
| /workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2143078481 |
| /workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.554322674 |
| /workspace/coverage/default/36.chip_sw_all_escalation_resets.3760918357 |
| /workspace/coverage/default/37.chip_sw_all_escalation_resets.276695022 |
| /workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4221168708 |
| /workspace/coverage/default/38.chip_sw_all_escalation_resets.3631457205 |
| /workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.471988499 |
| /workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.391801288 |
| /workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2041566719 |
| /workspace/coverage/default/4.chip_sw_data_integrity_escalation.1548753923 |
| /workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3113220976 |
| /workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4165742308 |
| /workspace/coverage/default/4.chip_sw_uart_rand_baudrate.941130783 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx.2225107485 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1648078550 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2341092859 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3970882126 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1729958268 |
| /workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3545866994 |
| /workspace/coverage/default/4.chip_tap_straps_dev.2354686925 |
| /workspace/coverage/default/4.chip_tap_straps_prod.3086546648 |
| /workspace/coverage/default/4.chip_tap_straps_testunlock0.1928864323 |
| /workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713093267 |
| /workspace/coverage/default/41.chip_sw_all_escalation_resets.2763438246 |
| /workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173205870 |
| /workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980712734 |
| /workspace/coverage/default/44.chip_sw_all_escalation_resets.2998484764 |
| /workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029169301 |
| /workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220984045 |
| /workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.4036329131 |
| /workspace/coverage/default/48.chip_sw_all_escalation_resets.681814619 |
| /workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367677742 |
| /workspace/coverage/default/49.chip_sw_all_escalation_resets.2859296886 |
| /workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.3491775162 |
| /workspace/coverage/default/5.chip_sw_data_integrity_escalation.1876104279 |
| /workspace/coverage/default/5.chip_sw_lc_ctrl_transition.608321320 |
| /workspace/coverage/default/5.chip_sw_uart_rand_baudrate.308081083 |
| /workspace/coverage/default/50.chip_sw_all_escalation_resets.2727628392 |
| /workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871388625 |
| /workspace/coverage/default/51.chip_sw_all_escalation_resets.847462124 |
| /workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230760749 |
| /workspace/coverage/default/52.chip_sw_all_escalation_resets.3219767538 |
| /workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.723599795 |
| /workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1403548998 |
| /workspace/coverage/default/54.chip_sw_all_escalation_resets.1501632087 |
| /workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.347615706 |
| /workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3472355644 |
| /workspace/coverage/default/56.chip_sw_all_escalation_resets.1116067164 |
| /workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996764905 |
| /workspace/coverage/default/57.chip_sw_all_escalation_resets.2815629964 |
| /workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2720426874 |
| /workspace/coverage/default/58.chip_sw_all_escalation_resets.2362209413 |
| /workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.629145928 |
| /workspace/coverage/default/59.chip_sw_all_escalation_resets.1876949237 |
| /workspace/coverage/default/6.chip_sw_all_escalation_resets.713819929 |
| /workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4091198892 |
| /workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2265025465 |
| /workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.488854206 |
| /workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2371752359 |
| /workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2700977084 |
| /workspace/coverage/default/62.chip_sw_all_escalation_resets.2763797235 |
| /workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031800613 |
| /workspace/coverage/default/63.chip_sw_all_escalation_resets.101222508 |
| /workspace/coverage/default/64.chip_sw_all_escalation_resets.2907231465 |
| /workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.221109612 |
| /workspace/coverage/default/65.chip_sw_all_escalation_resets.1372005447 |
| /workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.210089166 |
| /workspace/coverage/default/66.chip_sw_all_escalation_resets.3868020015 |
| /workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313202936 |
| /workspace/coverage/default/67.chip_sw_all_escalation_resets.2024873025 |
| /workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.322392140 |
| /workspace/coverage/default/68.chip_sw_all_escalation_resets.4264175447 |
| /workspace/coverage/default/69.chip_sw_all_escalation_resets.2471634917 |
| /workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.398851260 |
| /workspace/coverage/default/7.chip_sw_all_escalation_resets.174444907 |
| /workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1122394106 |
| /workspace/coverage/default/7.chip_sw_uart_rand_baudrate.180306639 |
| /workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3116039854 |
| /workspace/coverage/default/70.chip_sw_all_escalation_resets.4024978996 |
| /workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1774691927 |
| /workspace/coverage/default/71.chip_sw_all_escalation_resets.3892570313 |
| /workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1887033274 |
| /workspace/coverage/default/72.chip_sw_all_escalation_resets.3567281128 |
| /workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3145519892 |
| /workspace/coverage/default/73.chip_sw_all_escalation_resets.3100456575 |
| /workspace/coverage/default/74.chip_sw_all_escalation_resets.2717943562 |
| /workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1763771569 |
| /workspace/coverage/default/75.chip_sw_all_escalation_resets.2106164766 |
| /workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604341888 |
| /workspace/coverage/default/77.chip_sw_all_escalation_resets.4024211230 |
| /workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099161229 |
| /workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448810136 |
| /workspace/coverage/default/79.chip_sw_all_escalation_resets.975617802 |
| /workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3175411134 |
| /workspace/coverage/default/8.chip_sw_uart_rand_baudrate.3578830494 |
| /workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.224725113 |
| /workspace/coverage/default/80.chip_sw_all_escalation_resets.1878237341 |
| /workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.1434543856 |
| /workspace/coverage/default/81.chip_sw_all_escalation_resets.3039530386 |
| /workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858922945 |
| /workspace/coverage/default/82.chip_sw_all_escalation_resets.3511975238 |
| /workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3069012387 |
| /workspace/coverage/default/83.chip_sw_all_escalation_resets.618074148 |
| /workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848442220 |
| /workspace/coverage/default/84.chip_sw_all_escalation_resets.379560128 |
| /workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.916030209 |
| /workspace/coverage/default/85.chip_sw_all_escalation_resets.2366510767 |
| /workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3703814618 |
| /workspace/coverage/default/86.chip_sw_all_escalation_resets.89328678 |
| /workspace/coverage/default/87.chip_sw_all_escalation_resets.4067058865 |
| /workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4149820289 |
| /workspace/coverage/default/88.chip_sw_all_escalation_resets.3560832898 |
| /workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.380046178 |
| /workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013848547 |
| /workspace/coverage/default/9.chip_sw_all_escalation_resets.3124977927 |
| /workspace/coverage/default/9.chip_sw_lc_ctrl_transition.3832472238 |
| /workspace/coverage/default/9.chip_sw_uart_rand_baudrate.30641775 |
| /workspace/coverage/default/90.chip_sw_all_escalation_resets.2754340509 |
| /workspace/coverage/default/91.chip_sw_all_escalation_resets.2898024833 |
| /workspace/coverage/default/92.chip_sw_all_escalation_resets.3412927188 |
| /workspace/coverage/default/94.chip_sw_all_escalation_resets.3256778717 |
| /workspace/coverage/default/95.chip_sw_all_escalation_resets.2002911792 |
| /workspace/coverage/default/96.chip_sw_all_escalation_resets.4263261594 |
| /workspace/coverage/default/98.chip_sw_all_escalation_resets.916255459 |
| /workspace/coverage/default/99.chip_sw_all_escalation_resets.1742859050 |
| /workspace/coverage/pad_ctrl_test_mode/1.chip_padctrl_attributes.3610993177 |
| /workspace/coverage/pad_ctrl_test_mode/2.chip_padctrl_attributes.285724376 |
| /workspace/coverage/pad_ctrl_test_mode/3.chip_padctrl_attributes.775237622 |
| /workspace/coverage/pad_ctrl_test_mode/4.chip_padctrl_attributes.812822716 |
| /workspace/coverage/pad_ctrl_test_mode/5.chip_padctrl_attributes.1978153916 |
| /workspace/coverage/pad_ctrl_test_mode/7.chip_padctrl_attributes.3900469495 |
| /workspace/coverage/pad_ctrl_test_mode/8.chip_padctrl_attributes.2498915403 |
| /workspace/coverage/pad_ctrl_test_mode/9.chip_padctrl_attributes.520806081 |
| TEST NO | TEST LOCATION | TEST NAME | STATUS | STARTED | FINISHED | SIMULATION TIME |
| T1 |
/workspace/coverage/default/0.chip_tap_straps_prod.1733177932 |
|
|
Mar 10 02:59:20 PM PDT 24 |
Mar 10 03:02:00 PM PDT 24 |
2940703807 ps |
| T2 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.3120122047 |
|
|
Mar 10 03:15:27 PM PDT 24 |
Mar 10 03:36:30 PM PDT 24 |
6030014197 ps |
| T3 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.3926230332 |
|
|
Mar 10 03:14:59 PM PDT 24 |
Mar 10 03:25:49 PM PDT 24 |
6303176634 ps |
| T4 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.3974286650 |
|
|
Mar 10 03:01:17 PM PDT 24 |
Mar 10 03:40:55 PM PDT 24 |
27735368464 ps |
| T50 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.3760501421 |
|
|
Mar 10 03:24:42 PM PDT 24 |
Mar 10 03:39:18 PM PDT 24 |
5562971330 ps |
| T20 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.213917959 |
|
|
Mar 10 03:14:30 PM PDT 24 |
Mar 10 04:05:40 PM PDT 24 |
20064473452 ps |
| T81 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.2819204553 |
|
|
Mar 10 03:20:14 PM PDT 24 |
Mar 10 03:23:48 PM PDT 24 |
2809532440 ps |
| T67 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3824043256 |
|
|
Mar 10 03:17:45 PM PDT 24 |
Mar 10 03:28:02 PM PDT 24 |
4977968960 ps |
| T51 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.99497432 |
|
|
Mar 10 03:02:37 PM PDT 24 |
Mar 10 03:20:04 PM PDT 24 |
6140638346 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.4144011962 |
|
|
Mar 10 03:09:48 PM PDT 24 |
Mar 10 03:20:48 PM PDT 24 |
5299325335 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.1162562687 |
|
|
Mar 10 03:02:27 PM PDT 24 |
Mar 10 03:18:31 PM PDT 24 |
5325748868 ps |
| T153 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2179727604 |
|
|
Mar 10 03:19:09 PM PDT 24 |
Mar 10 03:24:19 PM PDT 24 |
2815774970 ps |
| T61 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.2215080931 |
|
|
Mar 10 03:00:39 PM PDT 24 |
Mar 10 03:02:23 PM PDT 24 |
2138199434 ps |
| T142 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1862899562 |
|
|
Mar 10 03:03:05 PM PDT 24 |
Mar 10 03:19:01 PM PDT 24 |
4973363912 ps |
| T240 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.3321602901 |
|
|
Mar 10 02:59:05 PM PDT 24 |
Mar 10 04:15:03 PM PDT 24 |
22945501936 ps |
| T143 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.2019825531 |
|
|
Mar 10 02:57:28 PM PDT 24 |
Mar 10 03:08:07 PM PDT 24 |
4396940726 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1532603767 |
|
|
Mar 10 03:01:00 PM PDT 24 |
Mar 10 03:09:33 PM PDT 24 |
4558076396 ps |
| T6 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.358106122 |
|
|
Mar 10 03:02:51 PM PDT 24 |
Mar 10 03:28:42 PM PDT 24 |
7300884129 ps |
| T126 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.1508258506 |
|
|
Mar 10 03:05:55 PM PDT 24 |
Mar 10 03:17:20 PM PDT 24 |
5045948336 ps |
| T130 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_prod.3120664459 |
|
|
Mar 10 03:04:06 PM PDT 24 |
Mar 10 03:11:20 PM PDT 24 |
4851416744 ps |
| T236 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.1732621923 |
|
|
Mar 10 03:27:37 PM PDT 24 |
Mar 10 03:34:39 PM PDT 24 |
4097386656 ps |
| T129 |
/workspace/coverage/default/2.rom_keymgr_functest.982351418 |
|
|
Mar 10 03:20:44 PM PDT 24 |
Mar 10 03:29:10 PM PDT 24 |
5036297476 ps |
| T38 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1886674477 |
|
|
Mar 10 03:03:32 PM PDT 24 |
Mar 10 03:33:01 PM PDT 24 |
6997953170 ps |
| T68 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_wakeup.3559612470 |
|
|
Mar 10 03:21:50 PM PDT 24 |
Mar 10 03:28:59 PM PDT 24 |
5718522170 ps |
| T167 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.3527608659 |
|
|
Mar 10 03:20:44 PM PDT 24 |
Mar 10 03:32:21 PM PDT 24 |
6807363158 ps |
| T377 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3280781308 |
|
|
Mar 10 03:20:51 PM PDT 24 |
Mar 10 03:23:48 PM PDT 24 |
2332655680 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.723845920 |
|
|
Mar 10 03:17:13 PM PDT 24 |
Mar 10 03:20:20 PM PDT 24 |
2261762420 ps |
| T137 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.2793769886 |
|
|
Mar 10 03:15:37 PM PDT 24 |
Mar 10 03:58:37 PM PDT 24 |
11852230760 ps |
| T317 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1163296418 |
|
|
Mar 10 03:30:28 PM PDT 24 |
Mar 10 03:37:03 PM PDT 24 |
3453875336 ps |
| T10 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.786083274 |
|
|
Mar 10 03:00:15 PM PDT 24 |
Mar 10 03:04:24 PM PDT 24 |
3034444774 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.2930071633 |
|
|
Mar 10 03:24:14 PM PDT 24 |
Mar 10 04:04:24 PM PDT 24 |
8998913672 ps |
| T378 |
/workspace/coverage/default/1.chip_sw_example_flash.1167212094 |
|
|
Mar 10 03:02:41 PM PDT 24 |
Mar 10 03:06:14 PM PDT 24 |
1973599096 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.233556263 |
|
|
Mar 10 03:17:00 PM PDT 24 |
Mar 10 06:32:35 PM PDT 24 |
255363519700 ps |
| T322 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3889309841 |
|
|
Mar 10 03:26:58 PM PDT 24 |
Mar 10 03:33:44 PM PDT 24 |
3377238710 ps |
| T138 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.4275330527 |
|
|
Mar 10 03:04:18 PM PDT 24 |
Mar 10 03:30:44 PM PDT 24 |
7700454054 ps |
| T148 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.726481041 |
|
|
Mar 10 03:19:00 PM PDT 24 |
Mar 10 03:31:27 PM PDT 24 |
4843143508 ps |
| T186 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.3069012387 |
|
|
Mar 10 03:30:16 PM PDT 24 |
Mar 10 03:37:39 PM PDT 24 |
4057241480 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.805462230 |
|
|
Mar 10 02:59:18 PM PDT 24 |
Mar 10 04:34:58 PM PDT 24 |
52633006274 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.1122510959 |
|
|
Mar 10 02:58:08 PM PDT 24 |
Mar 10 03:07:05 PM PDT 24 |
3932914100 ps |
| T155 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1648078550 |
|
|
Mar 10 03:22:50 PM PDT 24 |
Mar 10 04:30:16 PM PDT 24 |
23763557000 ps |
| T175 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3222866064 |
|
|
Mar 10 03:22:07 PM PDT 24 |
Mar 10 04:03:23 PM PDT 24 |
23082715389 ps |
| T187 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.3336228126 |
|
|
Mar 10 02:58:52 PM PDT 24 |
Mar 10 03:03:46 PM PDT 24 |
2515264417 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.4087071649 |
|
|
Mar 10 03:03:21 PM PDT 24 |
Mar 10 03:13:57 PM PDT 24 |
5021191494 ps |
| T132 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3880208857 |
|
|
Mar 10 02:56:46 PM PDT 24 |
Mar 10 03:04:18 PM PDT 24 |
4502339420 ps |
| T62 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2697243685 |
|
|
Mar 10 03:14:18 PM PDT 24 |
Mar 10 03:41:16 PM PDT 24 |
10383543939 ps |
| T516 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2562834069 |
|
|
Mar 10 02:58:40 PM PDT 24 |
Mar 10 03:07:00 PM PDT 24 |
7231419240 ps |
| T144 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access.894265702 |
|
|
Mar 10 03:06:12 PM PDT 24 |
Mar 10 03:14:01 PM PDT 24 |
3567746312 ps |
| T63 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.3759974704 |
|
|
Mar 10 03:28:51 PM PDT 24 |
Mar 10 03:38:20 PM PDT 24 |
4806696200 ps |
| T276 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.4220341337 |
|
|
Mar 10 03:11:42 PM PDT 24 |
Mar 10 03:22:49 PM PDT 24 |
4817396936 ps |
| T13 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.2341660983 |
|
|
Mar 10 02:59:29 PM PDT 24 |
Mar 10 03:05:19 PM PDT 24 |
4406223606 ps |
| T98 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2433263162 |
|
|
Mar 10 02:57:19 PM PDT 24 |
Mar 10 03:05:34 PM PDT 24 |
4021986100 ps |
| T99 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.1403548998 |
|
|
Mar 10 03:27:50 PM PDT 24 |
Mar 10 03:36:08 PM PDT 24 |
4214456046 ps |
| T100 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.3170478553 |
|
|
Mar 10 03:16:08 PM PDT 24 |
Mar 10 03:32:08 PM PDT 24 |
6171385197 ps |
| T101 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.3923056053 |
|
|
Mar 10 03:00:32 PM PDT 24 |
Mar 10 03:08:22 PM PDT 24 |
4541161248 ps |
| T14 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.1753117151 |
|
|
Mar 10 03:25:02 PM PDT 24 |
Mar 10 04:10:19 PM PDT 24 |
13197490574 ps |
| T102 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.1774691927 |
|
|
Mar 10 03:29:54 PM PDT 24 |
Mar 10 03:35:30 PM PDT 24 |
3371397140 ps |
| T103 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.216754929 |
|
|
Mar 10 03:26:33 PM PDT 24 |
Mar 10 04:30:28 PM PDT 24 |
22888202540 ps |
| T104 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.1255227097 |
|
|
Mar 10 02:58:48 PM PDT 24 |
Mar 10 03:02:25 PM PDT 24 |
3221956238 ps |
| T105 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2193329579 |
|
|
Mar 10 03:04:28 PM PDT 24 |
Mar 10 03:09:51 PM PDT 24 |
3168560446 ps |
| T185 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2769718218 |
|
|
Mar 10 03:21:47 PM PDT 24 |
Mar 10 03:28:41 PM PDT 24 |
3911839048 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.781528510 |
|
|
Mar 10 02:58:19 PM PDT 24 |
Mar 10 03:07:53 PM PDT 24 |
4294672096 ps |
| T325 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583799059 |
|
|
Mar 10 03:27:48 PM PDT 24 |
Mar 10 03:36:06 PM PDT 24 |
4323862960 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3571425192 |
|
|
Mar 10 03:00:35 PM PDT 24 |
Mar 10 03:13:07 PM PDT 24 |
5416126060 ps |
| T41 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1680781544 |
|
|
Mar 10 03:04:33 PM PDT 24 |
Mar 10 03:32:20 PM PDT 24 |
6728847344 ps |
| T91 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.4278099917 |
|
|
Mar 10 03:16:41 PM PDT 24 |
Mar 10 03:54:26 PM PDT 24 |
8324072500 ps |
| T92 |
/workspace/coverage/default/0.chip_sw_kmac_idle.3964537199 |
|
|
Mar 10 03:00:19 PM PDT 24 |
Mar 10 03:04:39 PM PDT 24 |
3412617864 ps |
| T93 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2162280595 |
|
|
Mar 10 03:03:36 PM PDT 24 |
Mar 10 03:34:11 PM PDT 24 |
9154734694 ps |
| T69 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2659978975 |
|
|
Mar 10 03:07:59 PM PDT 24 |
Mar 10 03:15:14 PM PDT 24 |
4027191560 ps |
| T94 |
/workspace/coverage/default/14.chip_sw_uart_rand_baudrate.608414777 |
|
|
Mar 10 03:24:02 PM PDT 24 |
Mar 10 04:01:32 PM PDT 24 |
14326625460 ps |
| T95 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.216683902 |
|
|
Mar 10 03:03:09 PM PDT 24 |
Mar 10 03:28:17 PM PDT 24 |
6182155912 ps |
| T96 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.2072509049 |
|
|
Mar 10 03:13:19 PM PDT 24 |
Mar 10 03:15:10 PM PDT 24 |
1871543666 ps |
| T97 |
/workspace/coverage/default/2.chip_sw_example_rom.1316485687 |
|
|
Mar 10 03:12:40 PM PDT 24 |
Mar 10 03:14:49 PM PDT 24 |
2403391096 ps |
| T198 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.1444663990 |
|
|
Mar 10 03:02:52 PM PDT 24 |
Mar 10 03:41:02 PM PDT 24 |
8393885660 ps |
| T133 |
/workspace/coverage/default/0.chip_sw_edn_auto_mode.1827612130 |
|
|
Mar 10 02:58:49 PM PDT 24 |
Mar 10 03:19:45 PM PDT 24 |
4931083548 ps |
| T517 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.1077471363 |
|
|
Mar 10 03:21:34 PM PDT 24 |
Mar 10 03:26:03 PM PDT 24 |
3397813008 ps |
| T518 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.3372371408 |
|
|
Mar 10 03:15:15 PM PDT 24 |
Mar 10 03:50:24 PM PDT 24 |
9422710910 ps |
| T519 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.3241312636 |
|
|
Mar 10 03:05:29 PM PDT 24 |
Mar 10 03:10:02 PM PDT 24 |
3139825936 ps |
| T316 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1231771031 |
|
|
Mar 10 03:25:37 PM PDT 24 |
Mar 10 03:31:36 PM PDT 24 |
3722280942 ps |
| T520 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.1416504666 |
|
|
Mar 10 02:57:57 PM PDT 24 |
Mar 10 03:53:17 PM PDT 24 |
12811433678 ps |
| T521 |
/workspace/coverage/default/0.chip_sw_pwrmgr_smoketest.4033130132 |
|
|
Mar 10 02:59:23 PM PDT 24 |
Mar 10 03:04:27 PM PDT 24 |
5059112096 ps |
| T270 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.3979865931 |
|
|
Mar 10 02:58:52 PM PDT 24 |
Mar 10 03:06:24 PM PDT 24 |
3379727544 ps |
| T522 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3784780895 |
|
|
Mar 10 03:12:46 PM PDT 24 |
Mar 10 03:22:50 PM PDT 24 |
3315130760 ps |
| T178 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.1338486829 |
|
|
Mar 10 03:26:50 PM PDT 24 |
Mar 10 03:37:34 PM PDT 24 |
4664857758 ps |
| T111 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3036114695 |
|
|
Mar 10 03:04:50 PM PDT 24 |
Mar 10 03:09:03 PM PDT 24 |
2739884720 ps |
| T134 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.1447832745 |
|
|
Mar 10 03:22:05 PM PDT 24 |
Mar 10 03:30:55 PM PDT 24 |
4016259320 ps |
| T247 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.1707347472 |
|
|
Mar 10 03:01:07 PM PDT 24 |
Mar 10 03:20:00 PM PDT 24 |
5877617704 ps |
| T199 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.2007458162 |
|
|
Mar 10 03:03:28 PM PDT 24 |
Mar 10 03:58:39 PM PDT 24 |
11900718160 ps |
| T326 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.3215089867 |
|
|
Mar 10 03:27:07 PM PDT 24 |
Mar 10 03:36:25 PM PDT 24 |
5180875980 ps |
| T70 |
/workspace/coverage/default/2.chip_jtag_mem_access.3925156017 |
|
|
Mar 10 03:11:03 PM PDT 24 |
Mar 10 03:31:30 PM PDT 24 |
13101503090 ps |
| T15 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx3.3545866994 |
|
|
Mar 10 03:23:06 PM PDT 24 |
Mar 10 03:39:16 PM PDT 24 |
5887058636 ps |
| T318 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.446207999 |
|
|
Mar 10 03:24:47 PM PDT 24 |
Mar 10 03:35:09 PM PDT 24 |
4951900610 ps |
| T145 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1757516993 |
|
|
Mar 10 03:01:00 PM PDT 24 |
Mar 10 03:05:28 PM PDT 24 |
2240496378 ps |
| T381 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.3870040815 |
|
|
Mar 10 03:09:05 PM PDT 24 |
Mar 10 03:27:01 PM PDT 24 |
6607256232 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1166105903 |
|
|
Mar 10 03:13:54 PM PDT 24 |
Mar 10 03:17:03 PM PDT 24 |
1881942030 ps |
| T106 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.1029422782 |
|
|
Mar 10 03:24:02 PM PDT 24 |
Mar 10 03:33:41 PM PDT 24 |
4665578330 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.1468468291 |
|
|
Mar 10 03:02:57 PM PDT 24 |
Mar 10 03:04:59 PM PDT 24 |
2652303970 ps |
| T218 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.681814619 |
|
|
Mar 10 03:27:45 PM PDT 24 |
Mar 10 03:36:24 PM PDT 24 |
5110717750 ps |
| T243 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.2982300157 |
|
|
Mar 10 02:57:29 PM PDT 24 |
Mar 10 03:05:03 PM PDT 24 |
3375681732 ps |
| T523 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.3640615533 |
|
|
Mar 10 03:20:55 PM PDT 24 |
Mar 10 03:30:36 PM PDT 24 |
3460156074 ps |
| T135 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_otbn_trans.359884937 |
|
|
Mar 10 03:06:35 PM PDT 24 |
Mar 10 03:17:06 PM PDT 24 |
4133021780 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.1500926057 |
|
|
Mar 10 03:03:56 PM PDT 24 |
Mar 10 03:21:44 PM PDT 24 |
5756175200 ps |
| T204 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2448810136 |
|
|
Mar 10 03:29:48 PM PDT 24 |
Mar 10 03:35:47 PM PDT 24 |
3411047444 ps |
| T524 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter.106208262 |
|
|
Mar 10 03:07:19 PM PDT 24 |
Mar 10 03:11:30 PM PDT 24 |
2644114058 ps |
| T382 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.3909037063 |
|
|
Mar 10 03:07:18 PM PDT 24 |
Mar 10 03:15:39 PM PDT 24 |
3395293832 ps |
| T450 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.4221168708 |
|
|
Mar 10 03:26:40 PM PDT 24 |
Mar 10 03:34:30 PM PDT 24 |
4130413640 ps |
| T248 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.2225107485 |
|
|
Mar 10 03:21:59 PM PDT 24 |
Mar 10 03:38:19 PM PDT 24 |
5770394880 ps |
| T525 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.3915017025 |
|
|
Mar 10 03:11:42 PM PDT 24 |
Mar 10 03:17:09 PM PDT 24 |
2785164644 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1483256714 |
|
|
Mar 10 02:59:28 PM PDT 24 |
Mar 10 03:59:07 PM PDT 24 |
18594278207 ps |
| T251 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.75742948 |
|
|
Mar 10 03:14:11 PM PDT 24 |
Mar 10 03:28:06 PM PDT 24 |
5932737832 ps |
| T267 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.292836707 |
|
|
Mar 10 03:17:07 PM PDT 24 |
Mar 10 03:25:12 PM PDT 24 |
3575211784 ps |
| T264 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.2713348862 |
|
|
Mar 10 03:20:46 PM PDT 24 |
Mar 10 03:26:04 PM PDT 24 |
2738871636 ps |
| T60 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2423285805 |
|
|
Mar 10 02:56:56 PM PDT 24 |
Mar 10 03:36:04 PM PDT 24 |
27660869616 ps |
| T250 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.1614998875 |
|
|
Mar 10 03:07:29 PM PDT 24 |
Mar 10 03:54:16 PM PDT 24 |
26644233736 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2605496842 |
|
|
Mar 10 02:58:53 PM PDT 24 |
Mar 10 03:06:16 PM PDT 24 |
5267780112 ps |
| T235 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3124977927 |
|
|
Mar 10 03:26:16 PM PDT 24 |
Mar 10 03:38:50 PM PDT 24 |
4536531984 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.231122130 |
|
|
Mar 10 03:15:04 PM PDT 24 |
Mar 10 03:36:37 PM PDT 24 |
5392860132 ps |
| T211 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.3145519892 |
|
|
Mar 10 03:33:17 PM PDT 24 |
Mar 10 03:40:18 PM PDT 24 |
4088533348 ps |
| T269 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.2535861956 |
|
|
Mar 10 03:17:15 PM PDT 24 |
Mar 10 03:34:58 PM PDT 24 |
5962550064 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.2501273528 |
|
|
Mar 10 03:00:07 PM PDT 24 |
Mar 10 03:08:37 PM PDT 24 |
4244327240 ps |
| T127 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.2126618368 |
|
|
Mar 10 03:04:01 PM PDT 24 |
Mar 10 03:09:57 PM PDT 24 |
3634277480 ps |
| T131 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.724664825 |
|
|
Mar 10 03:00:06 PM PDT 24 |
Mar 10 03:09:34 PM PDT 24 |
5592533100 ps |
| T39 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.155057012 |
|
|
Mar 10 03:05:02 PM PDT 24 |
Mar 10 03:54:36 PM PDT 24 |
12044149232 ps |
| T128 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.3051729771 |
|
|
Mar 10 03:20:28 PM PDT 24 |
Mar 10 03:25:24 PM PDT 24 |
3098407022 ps |
| T526 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.340790897 |
|
|
Mar 10 02:59:09 PM PDT 24 |
Mar 10 03:04:51 PM PDT 24 |
2954714104 ps |
| T260 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.3582657318 |
|
|
Mar 10 02:57:24 PM PDT 24 |
Mar 10 03:02:20 PM PDT 24 |
3255524844 ps |
| T527 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1143357388 |
|
|
Mar 10 03:00:29 PM PDT 24 |
Mar 10 03:04:02 PM PDT 24 |
2402687506 ps |
| T359 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.46186244 |
|
|
Mar 10 03:25:17 PM PDT 24 |
Mar 10 03:36:16 PM PDT 24 |
5283344616 ps |
| T192 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.1122394106 |
|
|
Mar 10 03:23:07 PM PDT 24 |
Mar 10 03:41:14 PM PDT 24 |
12941602706 ps |
| T232 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1527304834 |
|
|
Mar 10 03:19:22 PM PDT 24 |
Mar 10 03:29:38 PM PDT 24 |
4772546539 ps |
| T205 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1982923534 |
|
|
Mar 10 02:59:27 PM PDT 24 |
Mar 10 03:28:56 PM PDT 24 |
7237012900 ps |
| T351 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.176588026 |
|
|
Mar 10 02:57:39 PM PDT 24 |
Mar 10 03:05:01 PM PDT 24 |
3270070984 ps |
| T396 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.5331701 |
|
|
Mar 10 03:18:20 PM PDT 24 |
Mar 10 03:31:41 PM PDT 24 |
5033432048 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.191196269 |
|
|
Mar 10 02:59:02 PM PDT 24 |
Mar 10 03:03:44 PM PDT 24 |
3076211480 ps |
| T154 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.3195491276 |
|
|
Mar 10 02:57:58 PM PDT 24 |
Mar 10 03:03:37 PM PDT 24 |
4415694885 ps |
| T398 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.4062482414 |
|
|
Mar 10 03:04:00 PM PDT 24 |
Mar 10 03:26:52 PM PDT 24 |
6078755392 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.4134781402 |
|
|
Mar 10 03:01:03 PM PDT 24 |
Mar 10 04:14:29 PM PDT 24 |
23486908140 ps |
| T170 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3871515001 |
|
|
Mar 10 03:17:15 PM PDT 24 |
Mar 10 03:28:24 PM PDT 24 |
4571275080 ps |
| T117 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.2132817206 |
|
|
Mar 10 03:21:45 PM PDT 24 |
Mar 10 03:34:41 PM PDT 24 |
5255533024 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.3032519311 |
|
|
Mar 10 02:58:42 PM PDT 24 |
Mar 10 03:01:10 PM PDT 24 |
3270036654 ps |
| T528 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.4208249185 |
|
|
Mar 10 02:58:39 PM PDT 24 |
Mar 10 03:02:08 PM PDT 24 |
2458223901 ps |
| T529 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.177498343 |
|
|
Mar 10 03:23:10 PM PDT 24 |
Mar 10 03:48:22 PM PDT 24 |
6658168506 ps |
| T294 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.2387055871 |
|
|
Mar 10 03:27:44 PM PDT 24 |
Mar 10 03:40:59 PM PDT 24 |
4160302378 ps |
| T196 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2301394180 |
|
|
Mar 10 03:02:46 PM PDT 24 |
Mar 10 03:20:54 PM PDT 24 |
10637573441 ps |
| T530 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.244309517 |
|
|
Mar 10 03:17:03 PM PDT 24 |
Mar 10 03:21:55 PM PDT 24 |
2697911400 ps |
| T197 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.2457396680 |
|
|
Mar 10 03:04:32 PM PDT 24 |
Mar 10 03:39:52 PM PDT 24 |
8779709404 ps |
| T531 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.1603148765 |
|
|
Mar 10 03:04:10 PM PDT 24 |
Mar 10 03:13:04 PM PDT 24 |
5348483154 ps |
| T532 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3003459436 |
|
|
Mar 10 03:08:58 PM PDT 24 |
Mar 10 03:12:05 PM PDT 24 |
2438111629 ps |
| T533 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.941130783 |
|
|
Mar 10 03:22:03 PM PDT 24 |
Mar 10 04:07:47 PM PDT 24 |
14626531868 ps |
| T119 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.2656626637 |
|
|
Mar 10 03:02:11 PM PDT 24 |
Mar 10 03:06:43 PM PDT 24 |
3077590600 ps |
| T234 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.2858922945 |
|
|
Mar 10 03:30:10 PM PDT 24 |
Mar 10 03:38:41 PM PDT 24 |
3308398000 ps |
| T71 |
/workspace/coverage/default/3.chip_tap_straps_rma.1272375040 |
|
|
Mar 10 03:20:39 PM PDT 24 |
Mar 10 03:29:53 PM PDT 24 |
5850123058 ps |
| T389 |
/workspace/coverage/default/2.chip_sw_edn_kat.3419148107 |
|
|
Mar 10 03:17:28 PM PDT 24 |
Mar 10 03:30:18 PM PDT 24 |
3190824702 ps |
| T534 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.2422151771 |
|
|
Mar 10 03:13:40 PM PDT 24 |
Mar 10 03:20:07 PM PDT 24 |
3188247880 ps |
| T212 |
/workspace/coverage/default/9.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013848547 |
|
|
Mar 10 03:23:18 PM PDT 24 |
Mar 10 03:30:24 PM PDT 24 |
3777246290 ps |
| T535 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.2819585917 |
|
|
Mar 10 03:16:47 PM PDT 24 |
Mar 10 03:23:04 PM PDT 24 |
2992736384 ps |
| T304 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1850923798 |
|
|
Mar 10 03:16:10 PM PDT 24 |
Mar 10 03:23:01 PM PDT 24 |
3143699560 ps |
| T239 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.2720670328 |
|
|
Mar 10 03:00:30 PM PDT 24 |
Mar 10 03:06:56 PM PDT 24 |
3050300280 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_rstmgr_alert_info.1489618798 |
|
|
Mar 10 03:00:41 PM PDT 24 |
Mar 10 03:25:52 PM PDT 24 |
11605694910 ps |
| T303 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1800174923 |
|
|
Mar 10 03:17:59 PM PDT 24 |
Mar 10 03:38:02 PM PDT 24 |
5351339064 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.164380 |
|
|
Mar 10 02:56:53 PM PDT 24 |
Mar 10 03:01:25 PM PDT 24 |
2842734834 ps |
| T536 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.1943865842 |
|
|
Mar 10 03:20:21 PM PDT 24 |
Mar 10 03:24:28 PM PDT 24 |
2105933900 ps |
| T367 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.3290979130 |
|
|
Mar 10 02:59:04 PM PDT 24 |
Mar 10 03:05:19 PM PDT 24 |
3968956648 ps |
| T328 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.979783809 |
|
|
Mar 10 03:29:16 PM PDT 24 |
Mar 10 03:36:19 PM PDT 24 |
3858708724 ps |
| T374 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2143078481 |
|
|
Mar 10 03:26:18 PM PDT 24 |
Mar 10 03:32:14 PM PDT 24 |
3286222644 ps |
| T375 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.817805303 |
|
|
Mar 10 03:00:34 PM PDT 24 |
Mar 10 03:02:34 PM PDT 24 |
2710618152 ps |
| T216 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.860430891 |
|
|
Mar 10 03:15:32 PM PDT 24 |
Mar 10 03:44:34 PM PDT 24 |
7624962792 ps |
| T376 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.380046178 |
|
|
Mar 10 03:31:19 PM PDT 24 |
Mar 10 03:37:31 PM PDT 24 |
3760937280 ps |
| T25 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3310696998 |
|
|
Mar 10 03:01:38 PM PDT 24 |
Mar 10 03:07:02 PM PDT 24 |
4142318020 ps |
| T221 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.931257936 |
|
|
Mar 10 03:09:38 PM PDT 24 |
Mar 10 03:48:47 PM PDT 24 |
19807223198 ps |
| T76 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.4030962176 |
|
|
Mar 10 03:01:59 PM PDT 24 |
Mar 10 03:07:43 PM PDT 24 |
4732862044 ps |
| T323 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.554322674 |
|
|
Mar 10 03:31:43 PM PDT 24 |
Mar 10 03:39:01 PM PDT 24 |
3904586332 ps |
| T537 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.85150430 |
|
|
Mar 10 03:13:40 PM PDT 24 |
Mar 10 03:17:44 PM PDT 24 |
2284876010 ps |
| T383 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1313202936 |
|
|
Mar 10 03:31:06 PM PDT 24 |
Mar 10 03:39:25 PM PDT 24 |
3668092888 ps |
| T538 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1025485105 |
|
|
Mar 10 03:02:35 PM PDT 24 |
Mar 10 03:33:59 PM PDT 24 |
8945664552 ps |
| T74 |
/workspace/coverage/default/4.chip_tap_straps_prod.3086546648 |
|
|
Mar 10 03:21:29 PM PDT 24 |
Mar 10 03:29:55 PM PDT 24 |
5243564804 ps |
| T306 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.4201612335 |
|
|
Mar 10 03:27:57 PM PDT 24 |
Mar 10 03:40:08 PM PDT 24 |
4651038794 ps |
| T118 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2717943562 |
|
|
Mar 10 03:33:25 PM PDT 24 |
Mar 10 03:43:32 PM PDT 24 |
4846181188 ps |
| T43 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.4132307222 |
|
|
Mar 10 03:18:26 PM PDT 24 |
Mar 10 03:24:48 PM PDT 24 |
2884497750 ps |
| T16 |
/workspace/coverage/default/0.chip_sw_usbdev_pincfg.1796676301 |
|
|
Mar 10 02:58:14 PM PDT 24 |
Mar 10 04:51:48 PM PDT 24 |
31638090024 ps |
| T333 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2715176920 |
|
|
Mar 10 02:59:20 PM PDT 24 |
Mar 10 03:44:26 PM PDT 24 |
21518589429 ps |
| T410 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.108496227 |
|
|
Mar 10 02:59:15 PM PDT 24 |
Mar 10 03:05:31 PM PDT 24 |
5697275000 ps |
| T411 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.702766277 |
|
|
Mar 10 03:27:04 PM PDT 24 |
Mar 10 03:34:46 PM PDT 24 |
3684583416 ps |
| T412 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.434870657 |
|
|
Mar 10 02:57:50 PM PDT 24 |
Mar 10 03:08:16 PM PDT 24 |
3666001240 ps |
| T348 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3072379713 |
|
|
Mar 10 03:25:04 PM PDT 24 |
Mar 10 03:39:39 PM PDT 24 |
4600719388 ps |
| T42 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.2475884238 |
|
|
Mar 10 03:11:46 PM PDT 24 |
Mar 10 03:18:52 PM PDT 24 |
4861020800 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.1157226606 |
|
|
Mar 10 03:14:15 PM PDT 24 |
Mar 10 03:19:36 PM PDT 24 |
2823338776 ps |
| T319 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.2700977084 |
|
|
Mar 10 03:28:54 PM PDT 24 |
Mar 10 03:35:52 PM PDT 24 |
4227205338 ps |
| T340 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.1166210612 |
|
|
Mar 10 03:04:36 PM PDT 24 |
Mar 10 03:28:07 PM PDT 24 |
6278546160 ps |
| T203 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1024248095 |
|
|
Mar 10 03:25:56 PM PDT 24 |
Mar 10 03:31:22 PM PDT 24 |
3617989716 ps |
| T222 |
/workspace/coverage/default/1.chip_sw_flash_init.2209113337 |
|
|
Mar 10 03:00:23 PM PDT 24 |
Mar 10 03:37:08 PM PDT 24 |
23807128055 ps |
| T400 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.128740115 |
|
|
Mar 10 03:23:40 PM PDT 24 |
Mar 10 03:40:19 PM PDT 24 |
9304100329 ps |
| T401 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2211311942 |
|
|
Mar 10 03:21:26 PM PDT 24 |
Mar 10 03:31:45 PM PDT 24 |
7045221247 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.1120552905 |
|
|
Mar 10 03:15:05 PM PDT 24 |
Mar 10 03:24:17 PM PDT 24 |
4655393991 ps |
| T78 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.1986301502 |
|
|
Mar 10 03:00:12 PM PDT 24 |
Mar 10 03:05:30 PM PDT 24 |
3705827022 ps |
| T539 |
/workspace/coverage/default/1.rom_e2e_asm_init_test_unlocked0.3277602155 |
|
|
Mar 10 03:15:45 PM PDT 24 |
Mar 10 03:45:58 PM PDT 24 |
6455667766 ps |
| T109 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1794653031 |
|
|
Mar 10 03:00:25 PM PDT 24 |
Mar 10 05:45:53 PM PDT 24 |
58079181284 ps |
| T150 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.1449180269 |
|
|
Mar 10 02:59:52 PM PDT 24 |
Mar 10 03:07:55 PM PDT 24 |
6374595427 ps |
| T35 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.4285435607 |
|
|
Mar 10 03:05:25 PM PDT 24 |
Mar 10 03:12:07 PM PDT 24 |
3877070664 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.221055829 |
|
|
Mar 10 03:13:11 PM PDT 24 |
Mar 10 03:17:06 PM PDT 24 |
3466965910 ps |
| T54 |
/workspace/coverage/default/2.chip_sw_alert_test.904356234 |
|
|
Mar 10 03:18:13 PM PDT 24 |
Mar 10 03:23:00 PM PDT 24 |
3347866840 ps |
| T540 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1935156727 |
|
|
Mar 10 02:59:26 PM PDT 24 |
Mar 10 03:09:48 PM PDT 24 |
4899172124 ps |
| T79 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.859297254 |
|
|
Mar 10 03:16:59 PM PDT 24 |
Mar 10 03:40:58 PM PDT 24 |
11315233800 ps |
| T244 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.1258319855 |
|
|
Mar 10 02:58:19 PM PDT 24 |
Mar 10 03:23:26 PM PDT 24 |
8710327016 ps |
| T200 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_address_translation.2562371533 |
|
|
Mar 10 03:10:04 PM PDT 24 |
Mar 10 03:14:38 PM PDT 24 |
2807534924 ps |
| T288 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.1999006919 |
|
|
Mar 10 03:29:22 PM PDT 24 |
Mar 10 03:42:10 PM PDT 24 |
6379147576 ps |
| T188 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.1087055976 |
|
|
Mar 10 03:13:09 PM PDT 24 |
Mar 10 03:14:54 PM PDT 24 |
1923569781 ps |
| T125 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.821873621 |
|
|
Mar 10 03:05:46 PM PDT 24 |
Mar 10 03:22:06 PM PDT 24 |
8427391584 ps |
| T289 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3107084478 |
|
|
Mar 10 03:03:34 PM PDT 24 |
Mar 10 03:21:45 PM PDT 24 |
13941432143 ps |
| T52 |
/workspace/coverage/default/1.chip_jtag_csr_rw.1490694090 |
|
|
Mar 10 03:00:57 PM PDT 24 |
Mar 10 03:33:12 PM PDT 24 |
15647118409 ps |
| T290 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1501632087 |
|
|
Mar 10 03:28:23 PM PDT 24 |
Mar 10 03:41:31 PM PDT 24 |
5099436624 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.2774111241 |
|
|
Mar 10 02:58:51 PM PDT 24 |
Mar 10 03:03:38 PM PDT 24 |
2962769647 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1395582897 |
|
|
Mar 10 03:00:41 PM PDT 24 |
Mar 10 03:11:11 PM PDT 24 |
5631918344 ps |
| T291 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.3702533652 |
|
|
Mar 10 02:57:48 PM PDT 24 |
Mar 10 03:14:40 PM PDT 24 |
5695867256 ps |
| T345 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3543178901 |
|
|
Mar 10 03:26:19 PM PDT 24 |
Mar 10 03:34:54 PM PDT 24 |
5573097400 ps |
| T256 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.722661537 |
|
|
Mar 10 03:04:51 PM PDT 24 |
Mar 10 03:58:28 PM PDT 24 |
12312152344 ps |
| T509 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.2173205870 |
|
|
Mar 10 03:27:53 PM PDT 24 |
Mar 10 03:33:35 PM PDT 24 |
3562704236 ps |
| T541 |
/workspace/coverage/default/0.chip_sw_entropy_src_smoketest.3116812051 |
|
|
Mar 10 03:01:15 PM PDT 24 |
Mar 10 03:08:40 PM PDT 24 |
3269698488 ps |
| T542 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.1117463369 |
|
|
Mar 10 03:24:22 PM PDT 24 |
Mar 10 03:53:48 PM PDT 24 |
8312692778 ps |
| T305 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.4193974085 |
|
|
Mar 10 03:02:03 PM PDT 24 |
Mar 10 03:08:29 PM PDT 24 |
3571152640 ps |
| T543 |
/workspace/coverage/default/1.chip_sw_kmac_idle.2200729360 |
|
|
Mar 10 03:05:55 PM PDT 24 |
Mar 10 03:09:32 PM PDT 24 |
2133352620 ps |
| T464 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3521337057 |
|
|
Mar 10 03:26:23 PM PDT 24 |
Mar 10 03:32:25 PM PDT 24 |
3361739174 ps |
| T544 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.1876949237 |
|
|
Mar 10 03:28:25 PM PDT 24 |
Mar 10 03:40:02 PM PDT 24 |
6229166116 ps |
| T249 |
/workspace/coverage/default/2.chip_tap_straps_prod.1592052266 |
|
|
Mar 10 03:18:32 PM PDT 24 |
Mar 10 03:20:57 PM PDT 24 |
2546985824 ps |
| T439 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.221109612 |
|
|
Mar 10 03:28:36 PM PDT 24 |
Mar 10 03:35:59 PM PDT 24 |
4294111290 ps |
| T245 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.3501801757 |
|
|
Mar 10 03:02:41 PM PDT 24 |
Mar 10 03:15:18 PM PDT 24 |
5890911174 ps |
| T545 |
/workspace/coverage/default/2.chip_sw_kmac_idle.2045212595 |
|
|
Mar 10 03:16:30 PM PDT 24 |
Mar 10 03:20:23 PM PDT 24 |
2238748536 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.709713723 |
|
|
Mar 10 03:19:09 PM PDT 24 |
Mar 10 04:25:54 PM PDT 24 |
24607823839 ps |
| T262 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.2806308679 |
|
|
Mar 10 03:00:58 PM PDT 24 |
Mar 10 03:04:24 PM PDT 24 |
2923517604 ps |
| T432 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3892570313 |
|
|
Mar 10 03:30:47 PM PDT 24 |
Mar 10 03:43:45 PM PDT 24 |
6106337336 ps |
| T441 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.3567281128 |
|
|
Mar 10 03:30:51 PM PDT 24 |
Mar 10 03:40:46 PM PDT 24 |
5362102600 ps |
| T263 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.2120402030 |
|
|
Mar 10 03:03:16 PM PDT 24 |
Mar 10 03:07:23 PM PDT 24 |
2961527120 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.737411604 |
|
|
Mar 10 03:14:01 PM PDT 24 |
Mar 10 03:43:41 PM PDT 24 |
14308255008 ps |
| T444 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.3139601515 |
|
|
Mar 10 03:25:10 PM PDT 24 |
Mar 10 03:40:03 PM PDT 24 |
4790402520 ps |
| T176 |
/workspace/coverage/default/1.chip_sw_power_idle_load.1089264847 |
|
|
Mar 10 03:11:56 PM PDT 24 |
Mar 10 03:22:14 PM PDT 24 |
4631987128 ps |
| T217 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.909114861 |
|
|
Mar 10 03:04:51 PM PDT 24 |
Mar 10 03:09:09 PM PDT 24 |
2955712788 ps |
| T495 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1996764905 |
|
|
Mar 10 03:29:56 PM PDT 24 |
Mar 10 03:38:22 PM PDT 24 |
3458795090 ps |
| T293 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.2366577007 |
|
|
Mar 10 03:01:19 PM PDT 24 |
Mar 10 03:09:58 PM PDT 24 |
5607622834 ps |
| T64 |
/workspace/coverage/default/4.chip_tap_straps_rma.1382355734 |
|
|
Mar 10 03:22:32 PM PDT 24 |
Mar 10 03:30:25 PM PDT 24 |
4703968500 ps |
| T440 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.3269435211 |
|
|
Mar 10 03:25:31 PM PDT 24 |
Mar 10 03:32:26 PM PDT 24 |
4200200600 ps |
| T546 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.250430643 |
|
|
Mar 10 03:22:07 PM PDT 24 |
Mar 10 03:39:53 PM PDT 24 |
9464230136 ps |
| T113 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.115492932 |
|
|
Mar 10 03:20:18 PM PDT 24 |
Mar 10 03:23:52 PM PDT 24 |
2643407850 ps |
| T547 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.888488485 |
|
|
Mar 10 03:11:41 PM PDT 24 |
Mar 10 03:15:38 PM PDT 24 |
2192434262 ps |
| T414 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.2951791367 |
|
|
Mar 10 03:20:26 PM PDT 24 |
Mar 10 03:22:25 PM PDT 24 |
2331603315 ps |
| T17 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.2346727286 |
|
|
Mar 10 02:59:05 PM PDT 24 |
Mar 10 03:03:30 PM PDT 24 |
2792436908 ps |
| T548 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2665072605 |
|
|
Mar 10 02:59:27 PM PDT 24 |
Mar 10 03:50:31 PM PDT 24 |
39077705144 ps |
| T82 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.748932516 |
|
|
Mar 10 03:23:46 PM PDT 24 |
Mar 10 03:30:06 PM PDT 24 |
3635682768 ps |
| T549 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.4262121708 |
|
|
Mar 10 03:07:18 PM PDT 24 |
Mar 10 03:17:14 PM PDT 24 |
4467982614 ps |
| T550 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.1707870815 |
|
|
Mar 10 02:59:28 PM PDT 24 |
Mar 10 03:03:45 PM PDT 24 |
2915427288 ps |
| T420 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2199180798 |
|
|
Mar 10 02:57:53 PM PDT 24 |
Mar 10 03:06:07 PM PDT 24 |
4374120321 ps |
| T551 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1013221292 |
|
|
Mar 10 02:58:06 PM PDT 24 |
Mar 10 03:24:24 PM PDT 24 |
15957497344 ps |