Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	45021964	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	45021964	0	0
T1	53377	3456	0	0
T2	356036	41166	0	0
T3	202622	22336	0	0
T4	104946	369235	0	0
T20	175818	129791	0	0
T33	278985	21714	0	0
T50	342668	29799	0	0
T51	362939	35235	0	0
T67	182258	23650	0	0
T81	73338	8569	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	34197985	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	34197985	0	0
T1	53377	1864	0	0
T2	356036	31570	0	0
T3	202622	18150	0	0
T4	104946	185528	0	0
T20	175818	124737	0	0
T33	278985	17604	0	0
T50	342668	25720	0	0
T51	362939	30968	0	0
T67	182258	20934	0	0
T81	73338	6101	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	31325048	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	31325048	0	0
T1	53377	464	0	0
T2	356036	42788	0	0
T3	202622	13473	0	0
T4	104946	30693	0	0
T20	175818	122076	0	0
T33	278985	13289	0	0
T50	342668	38050	0	0
T51	362939	32985	0	0
T67	182258	4160	0	0
T81	73338	4938	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	25696521	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	25696521	0	0
T1	53377	353	0	0
T2	356036	39961	0	0
T3	202622	13206	0	0
T4	104946	29023	0	0
T20	175818	121690	0	0
T33	278985	13037	0	0
T50	342668	37840	0	0
T51	362939	32682	0	0
T67	182258	3959	0	0
T81	73338	4735	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	62003	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	62003	0	0
T1	53377	8	0	0
T2	356036	14	0	0
T3	202622	27	0	0
T4	104946	152	0	0
T20	175818	61	0	0
T33	278985	29	0	0
T50	342668	53	0	0
T51	362939	23	0	0
T67	182258	78	0	0
T81	73338	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	62003	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	62003	0	0
T1	53377	8	0	0
T2	356036	14	0	0
T3	202622	27	0	0
T4	104946	152	0	0
T20	175818	61	0	0
T33	278985	29	0	0
T50	342668	53	0	0
T51	362939	23	0	0
T67	182258	78	0	0
T81	73338	14	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	49411	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	49411	0	0
T1	53377	8	0	0
T2	356036	13	0	0
T3	202622	25	0	0
T4	104946	143	0	0
T20	175818	59	0	0
T33	278985	25	0	0
T50	342668	52	0	0
T51	362939	20	0	0
T67	182258	77	0	0
T81	73338	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	49411	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	49411	0	0
T1	53377	8	0	0
T2	356036	13	0	0
T3	202622	25	0	0
T4	104946	143	0	0
T20	175818	59	0	0
T33	278985	25	0	0
T50	342668	52	0	0
T51	362939	20	0	0
T67	182258	77	0	0
T81	73338	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	12592	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	12592	0	0
T2	356036	1	0	0
T3	202622	2	0	0
T4	104946	9	0	0
T20	175818	2	0	0
T33	278985	4	0	0
T50	342668	1	0	0
T51	362939	3	0	0
T67	182258	1	0	0
T81	73338	1	0	0
T140	339753	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	402887193	12592	0	0
DepthKnown_A	402887193	402787144	0	0
RvalidKnown_A	402887193	402787144	0	0
WreadyKnown_A	402887193	402787144	0	0
gen_passthru_fifo.paramCheckPass	952	952	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	12592	0	0
T2	356036	1	0	0
T3	202622	2	0	0
T4	104946	9	0	0
T20	175818	2	0	0
T33	278985	4	0	0
T50	342668	1	0	0
T51	362939	3	0	0
T67	182258	1	0	0
T81	73338	1	0	0
T140	339753	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	402787144	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0