Module Definition
dashboard | hierarchy | modlist | groups | tests | asserts

Module : rv_plic_reg_top
SCORELINECONDTOGGLEFSMBRANCHASSERT
92.38 100.00 69.99 99.51 100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv

Module self-instances :
NAMESCORELINECONDTOGGLEFSMBRANCHASSERT
tb.dut.top_earlgrey.u_rv_plic.u_reg 92.38 100.00 69.99 99.51 100.00

Line Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
TOTAL15281528100.00
ALWAYS6844100.00
CONT_ASSIGN7711100.00
CONT_ASSIGN8911100.00
CONT_ASSIGN9011100.00
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CONT_ASSIGN11911100.00
CONT_ASSIGN1622711100.00
CONT_ASSIGN1624111100.00
CONT_ASSIGN1627511100.00
CONT_ASSIGN1628911100.00
ALWAYS16295199199100.00
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ALWAYS1650011100.00
CONT_ASSIGN1670211100.00
CONT_ASSIGN1670411100.00
CONT_ASSIGN1670511100.00
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CONT_ASSIGN1731711100.00
CONT_ASSIGN1731911100.00
CONT_ASSIGN1732111100.00
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CONT_ASSIGN1732511100.00
CONT_ASSIGN1732711100.00
CONT_ASSIGN1732911100.00
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ALWAYS17634199199100.00
ALWAYS17837552552100.00
CONT_ASSIGN1899400
CONT_ASSIGN1900211100.00
CONT_ASSIGN1900311100.00
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' was not found, so annotated line coverage report could not be generated.
Line No.CoveredStatements
68 1 1
69 1 1
70 1 1
71 1 1
MISSING_ELSE
77 1 1
89 1 1
90 1 1
118 1 1
119 1 1
16227 1 1
16241 1 1
16275 1 1
16289 1 1
16295 1 1
16296 1 1
16297 1 1
16298 1 1
16299 1 1
16300 1 1
16301 1 1
16302 1 1
16303 1 1
16304 1 1
16305 1 1
16306 1 1
16307 1 1
16308 1 1
16309 1 1
16310 1 1
16311 1 1
16312 1 1
16313 1 1
16314 1 1
16315 1 1
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16317 1 1
16318 1 1
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16326 1 1
16327 1 1
16328 1 1
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16330 1 1
16331 1 1
16332 1 1
16333 1 1
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16335 1 1
16336 1 1
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18964 1 1
18968 1 1
18972 1 1
18976 1 1
18980 1 1
18994 unreachable
19002 1 1
19003 1 1


Cond Coverage for Module : rv_plic_reg_top
TotalCoveredPercent
Conditions1983138869.99
Logical1983138869.99
Non-Logical00
Event00

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.
Line numbersPercent
58-1648598.48
16486-1650044.54
16500-1691571.06
16918-1762875.00

Branch Coverage for Module : rv_plic_reg_top
Line No.TotalCoveredPercent
Branches 204 203 99.51
TERNARY 16496 2 2 100.00
IF 68 3 3 100.00
CASE 17838 199 198 99.50

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv' or '../src/lowrisc_opentitan_top_earlgrey_rv_plic_0/rtl/rv_plic_reg_top.sv was not found/opened, so annotated branch coverage report could not be generated.

LineNo. Expression -1-: 16496 ((reg_re || reg_we)) ?

Branches:
-1-StatusTests
1 Covered T50,T51,T140
0 Covered T1,T2,T3


LineNo. Expression -1-: 68 if ((!rst_ni)) -2-: 70 if ((intg_err || reg_we_err))

Branches:
-1--2-StatusTests
1 - Covered T1,T2,T3
0 1 Covered T359,T360,T361
0 0 Covered T1,T2,T3


LineNo. Expression -1-: 17838 case (1'b1)

Branches:
-1-StatusTests
addr_hit[0] Covered T3,T50,T51
addr_hit[1] Covered T126,T155,T98
addr_hit[2] Covered T126,T155,T98
addr_hit[3] Covered T126,T155,T98
addr_hit[4] Covered T126,T155,T98
addr_hit[5] Covered T126,T155,T98
addr_hit[6] Covered T126,T155,T98
addr_hit[7] Covered T126,T155,T98
addr_hit[8] Covered T126,T155,T98
addr_hit[9] Covered T50,T140,T240
addr_hit[10] Covered T50,T140,T240
addr_hit[11] Covered T50,T140,T240
addr_hit[12] Covered T50,T140,T240
addr_hit[13] Covered T50,T140,T240
addr_hit[14] Covered T50,T140,T240
addr_hit[15] Covered T50,T140,T240
addr_hit[16] Covered T50,T140,T240
addr_hit[17] Covered T126,T175,T98
addr_hit[18] Covered T126,T175,T98
addr_hit[19] Covered T126,T175,T98
addr_hit[20] Covered T126,T175,T98
addr_hit[21] Covered T126,T175,T98
addr_hit[22] Covered T126,T175,T98
addr_hit[23] Covered T126,T175,T98
addr_hit[24] Covered T126,T175,T98
addr_hit[25] Covered T126,T98,T14
addr_hit[26] Covered T126,T98,T14
addr_hit[27] Covered T126,T98,T14
addr_hit[28] Covered T126,T98,T14
addr_hit[29] Covered T126,T98,T14
addr_hit[30] Covered T126,T98,T14
addr_hit[31] Covered T126,T98,T14
addr_hit[32] Covered T126,T98,T14
addr_hit[33] Covered T126,T98,T260
addr_hit[34] Covered T126,T98,T260
addr_hit[35] Covered T126,T98,T260
addr_hit[36] Covered T126,T98,T260
addr_hit[37] Covered T126,T98,T260
addr_hit[38] Covered T126,T98,T260
addr_hit[39] Covered T126,T98,T260
addr_hit[40] Covered T126,T98,T260
addr_hit[41] Covered T126,T98,T260
addr_hit[42] Covered T126,T98,T260
addr_hit[43] Covered T126,T98,T260
addr_hit[44] Covered T126,T98,T260
addr_hit[45] Covered T126,T98,T260
addr_hit[46] Covered T126,T98,T260
addr_hit[47] Covered T126,T98,T260
addr_hit[48] Covered T126,T98,T260
addr_hit[49] Covered T126,T98,T260
addr_hit[50] Covered T126,T98,T260
addr_hit[51] Covered T126,T98,T260
addr_hit[52] Covered T126,T98,T260
addr_hit[53] Covered T126,T98,T260
addr_hit[54] Covered T126,T98,T260
addr_hit[55] Covered T126,T98,T260
addr_hit[56] Covered T126,T98,T260
addr_hit[57] Covered T126,T98,T260
addr_hit[58] Covered T126,T98,T260
addr_hit[59] Covered T126,T98,T260
addr_hit[60] Covered T126,T98,T260
addr_hit[61] Covered T126,T98,T260
addr_hit[62] Covered T126,T98,T260
addr_hit[63] Covered T126,T98,T260
addr_hit[64] Covered T126,T98,T260
addr_hit[65] Covered T126,T98,T260
addr_hit[66] Covered T126,T98,T260
addr_hit[67] Covered T126,T98,T260
addr_hit[68] Covered T126,T98,T260
addr_hit[69] Covered T126,T98,T260
addr_hit[70] Covered T126,T98,T260
addr_hit[71] Covered T126,T98,T260
addr_hit[72] Covered T126,T98,T260
addr_hit[73] Covered T126,T238,T98
addr_hit[74] Covered T126,T238,T98
addr_hit[75] Covered T126,T98,T260
addr_hit[76] Covered T126,T238,T98
addr_hit[77] Covered T126,T238,T98
addr_hit[78] Covered T126,T238,T98
addr_hit[79] Covered T126,T238,T98
addr_hit[80] Covered T126,T238,T98
addr_hit[81] Covered T126,T98,T260
addr_hit[82] Covered T126,T238,T98
addr_hit[83] Covered T126,T98,T260
addr_hit[84] Covered T126,T98,T260
addr_hit[85] Covered T126,T98,T260
addr_hit[86] Covered T126,T98,T260
addr_hit[87] Covered T126,T98,T260
addr_hit[88] Covered T126,T98,T260
addr_hit[89] Covered T126,T98,T260
addr_hit[90] Covered T126,T98,T260
addr_hit[91] Covered T126,T98,T260
addr_hit[92] Covered T126,T98,T260
addr_hit[93] Covered T126,T98,T260
addr_hit[94] Covered T126,T98,T260
addr_hit[95] Covered T126,T98,T260
addr_hit[96] Covered T126,T98,T260
addr_hit[97] Covered T126,T98,T243
addr_hit[98] Covered T126,T98,T243
addr_hit[99] Covered T126,T98,T260
addr_hit[100] Covered T126,T98,T243
addr_hit[101] Covered T126,T98,T243
addr_hit[102] Covered T126,T98,T243
addr_hit[103] Covered T51,T126,T98
addr_hit[104] Covered T51,T126,T98
addr_hit[105] Covered T126,T98,T260
addr_hit[106] Covered T51,T126,T98
addr_hit[107] Covered T51,T126,T98
addr_hit[108] Covered T51,T126,T98
addr_hit[109] Covered T51,T126,T98
addr_hit[110] Covered T51,T126,T98
addr_hit[111] Covered T126,T98,T260
addr_hit[112] Covered T51,T126,T98
addr_hit[113] Covered T126,T98,T260
addr_hit[114] Covered T126,T98,T260
addr_hit[115] Covered T126,T98,T260
addr_hit[116] Covered T126,T98,T260
addr_hit[117] Covered T126,T98,T260
addr_hit[118] Covered T126,T98,T260
addr_hit[119] Covered T126,T98,T260
addr_hit[120] Covered T126,T98,T260
addr_hit[121] Covered T126,T98,T260
addr_hit[122] Covered T126,T98,T260
addr_hit[123] Covered T126,T141,T62
addr_hit[124] Covered T126,T141,T62
addr_hit[125] Covered T126,T141,T62
addr_hit[126] Covered T126,T141,T62
addr_hit[127] Covered T126,T98,T260
addr_hit[128] Covered T126,T98,T260
addr_hit[129] Covered T126,T98,T260
addr_hit[130] Covered T126,T98,T260
addr_hit[131] Covered T126,T98,T260
addr_hit[132] Covered T126,T98,T260
addr_hit[133] Covered T126,T98,T260
addr_hit[134] Covered T126,T98,T260
addr_hit[135] Covered T126,T98,T260
addr_hit[136] Covered T126,T98,T260
addr_hit[137] Covered T126,T98,T260
addr_hit[138] Covered T126,T98,T260
addr_hit[139] Covered T126,T98,T260
addr_hit[140] Covered T126,T98,T260
addr_hit[141] Covered T126,T98,T260
addr_hit[142] Covered T126,T98,T260
addr_hit[143] Covered T126,T98,T260
addr_hit[144] Covered T126,T98,T260
addr_hit[145] Covered T126,T98,T260
addr_hit[146] Covered T126,T98,T260
addr_hit[147] Covered T126,T98,T260
addr_hit[148] Covered T126,T98,T260
addr_hit[149] Covered T126,T236,T68
addr_hit[150] Covered T126,T98,T260
addr_hit[151] Covered T126,T98,T260
addr_hit[152] Covered T126,T62,T63
addr_hit[153] Covered T126,T62,T63
addr_hit[154] Covered T126,T98,T260
addr_hit[155] Covered T126,T98,T260
addr_hit[156] Covered T143,T126,T98
addr_hit[157] Covered T143,T126,T98
addr_hit[158] Covered T143,T126,T98
addr_hit[159] Covered T143,T126,T98
addr_hit[160] Covered T143,T126,T98
addr_hit[161] Covered T126,T98,T260
addr_hit[162] Covered T126,T98,T104
addr_hit[163] Covered T126,T98,T104
addr_hit[164] Covered T126,T98,T260
addr_hit[165] Covered T126,T98,T260
addr_hit[166] Covered T126,T98,T260
addr_hit[167] Covered T126,T98,T260
addr_hit[168] Covered T126,T98,T164
addr_hit[169] Covered T126,T98,T260
addr_hit[170] Covered T126,T98,T260
addr_hit[171] Covered T126,T98,T260
addr_hit[172] Covered T126,T98,T260
addr_hit[173] Covered T126,T98,T260
addr_hit[174] Covered T126,T98,T260
addr_hit[175] Covered T126,T98,T260
addr_hit[176] Covered T126,T98,T260
addr_hit[177] Covered T126,T98,T260
addr_hit[178] Covered T126,T98,T260
addr_hit[179] Covered T126,T98,T260
addr_hit[180] Covered T126,T98,T260
addr_hit[181] Covered T126,T98,T260
addr_hit[182] Covered T53
addr_hit[183] Covered T53
addr_hit[184] Covered T53
addr_hit[185] Covered T53
addr_hit[186] Covered T362,T53,T363
addr_hit[187] Covered T53
addr_hit[188] Covered T50,T140,T240
addr_hit[189] Covered T126,T98,T14
addr_hit[190] Covered T126,T238,T98
addr_hit[191] Covered T51,T126,T141
addr_hit[192] Covered T143,T126,T236
addr_hit[193] Covered T143,T126,T98
addr_hit[194] Covered T50,T140,T240
addr_hit[195] Covered T50,T51,T140
addr_hit[196] Covered T260,T261,T53
addr_hit[197] Covered T54,T55,T53
default Not Covered


Assert Coverage for Module : rv_plic_reg_top
TotalAttemptedPercentSucceeded/MatchedPercent
Assertions 4 4 100.00 4 100.00
Cover properties 0 0 0
Cover sequences 0 0 0
Total 4 4 100.00 4 100.00




Assertion Details

NameAttemptsReal SuccessesFailuresIncomplete
en2addrHit 402887193 33775 0 0
reAfterRv 402887193 33775 0 0
rePulse 402887193 13729 0 0
wePulse 402887193 20046 0 0


en2addrHit
NameAttemptsReal SuccessesFailuresIncomplete
Total 402887193 33775 0 0
T20 175818 0 0 0
T33 278985 0 0 0
T50 342668 51 0 0
T51 362939 48 0 0
T61 39006 0 0 0
T67 182258 0 0 0
T68 0 5 0 0
T81 73338 0 0 0
T126 0 646 0 0
T140 339753 51 0 0
T141 0 26 0 0
T142 282583 0 0 0
T143 0 110 0 0
T153 87087 0 0 0
T236 0 8 0 0
T240 0 53 0 0
T317 0 8 0 0

reAfterRv
NameAttemptsReal SuccessesFailuresIncomplete
Total 402887193 33775 0 0
T20 175818 0 0 0
T33 278985 0 0 0
T50 342668 51 0 0
T51 362939 48 0 0
T61 39006 0 0 0
T67 182258 0 0 0
T68 0 5 0 0
T81 73338 0 0 0
T126 0 646 0 0
T140 339753 51 0 0
T141 0 26 0 0
T142 282583 0 0 0
T143 0 110 0 0
T153 87087 0 0 0
T236 0 8 0 0
T240 0 53 0 0
T317 0 8 0 0

rePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 402887193 13729 0 0
T20 175818 0 0 0
T33 278985 0 0 0
T50 342668 21 0 0
T51 362939 20 0 0
T61 39006 0 0 0
T67 182258 0 0 0
T68 0 2 0 0
T81 73338 0 0 0
T126 0 232 0 0
T140 339753 21 0 0
T141 0 8 0 0
T142 282583 0 0 0
T143 0 52 0 0
T153 87087 0 0 0
T236 0 3 0 0
T240 0 22 0 0
T317 0 3 0 0

wePulse
NameAttemptsReal SuccessesFailuresIncomplete
Total 402887193 20046 0 0
T20 175818 0 0 0
T33 278985 0 0 0
T50 342668 30 0 0
T51 362939 28 0 0
T61 39006 0 0 0
T67 182258 0 0 0
T68 0 3 0 0
T81 73338 0 0 0
T126 0 414 0 0
T140 339753 30 0 0
T141 0 18 0 0
T142 282583 0 0 0
T143 0 58 0 0
T153 87087 0 0 0
T236 0 5 0 0
T240 0 31 0 0
T317 0 5 0 0

0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%