Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	96.55	100.00	93.33			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.55	100.00	93.33			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T200,T44,T201
0	1	Covered	T200,T201,T202
1	0	Covered	T44

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T44,T201
1	Covered	T200,T44,T201

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T44,T201
1	Covered	T200,T44,T201

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T200,T201,T202
1	1	Covered	T200,T44,T201

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T200,T44,T201
1	0	Covered	T200,T44,T201
1	1	Covered	T200,T201,T202

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T200,T44,T201

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T44,T201
0	Covered	T200,T44,T201

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T44,T201
0	Covered	T200,T44,T201

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	805774386	787753606	0	0
CheckNGreaterZero_A	1904	1904	0	0
GntImpliesReady_A	805774386	5342	0	0
GntImpliesValid_A	805774386	5342	0	0
GrantKnown_A	805774386	787753606	0	0
IdxKnown_A	805774386	787753606	0	0
IndexIsCorrect_A	805774386	5342	0	0
NoReadyValidNoGrant_A	805774386	0	0	0
Priority_A	805774386	5342	0	0
ReadyAndValidImplyGrant_A	805774386	5342	0	0
ReqAndReadyImplyGrant_A	805774386	5342	0	0
ReqImpliesValid_A	805774386	5342	0	0
ValidKnown_A	805774386	787753606	0	0
gen_data_port_assertion.DataFlow_A	805774386	5342	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	787753606	0	0
T1	106754	106638	0	0
T2	712072	711970	0	0
T3	405244	405034	0	0
T4	209892	209698	0	0
T20	351636	351614	0	0
T33	557970	557744	0	0
T50	685336	685212	0	0
T51	725878	725754	0	0
T67	364516	364400	0	0
T81	146676	146560	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1904	1904	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T20	2	2	0	0
T33	2	2	0	0
T50	2	2	0	0
T51	2	2	0	0
T67	2	2	0	0
T81	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	787753606	0	0
T1	106754	106638	0	0
T2	712072	711970	0	0
T3	405244	405034	0	0
T4	209892	209698	0	0
T20	351636	351614	0	0
T33	557970	557744	0	0
T50	685336	685212	0	0
T51	725878	725754	0	0
T67	364516	364400	0	0
T81	146676	146560	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	787753606	0	0
T1	106754	106638	0	0
T2	712072	711970	0	0
T3	405244	405034	0	0
T4	209892	209698	0	0
T20	351636	351614	0	0
T33	557970	557744	0	0
T50	685336	685212	0	0
T51	725878	725754	0	0
T67	364516	364400	0	0
T81	146676	146560	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	787753606	0	0
T1	106754	106638	0	0
T2	712072	711970	0	0
T3	405244	405034	0	0
T4	209892	209698	0	0
T20	351636	351614	0	0
T33	557970	557744	0	0
T50	685336	685212	0	0
T51	725878	725754	0	0
T67	364516	364400	0	0
T81	146676	146560	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	805774386	5342	0	0
T52	266788	0	0	0
T125	1051406	0	0	0
T151	191984	0	0	0
T169	414052	0	0	0
T188	72100	0	0	0
T200	161758	1773	0	0
T201	0	1786	0	0
T202	0	1783	0	0
T288	560160	0	0	0
T289	1086240	0	0	0
T290	561074	0	0	0
T291	750942	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T200,T44,T201
0	1	Covered	T200,T201,T202
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T201,T202
1	Covered	T200,T44,T201

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T201,T202
1	Covered	T200,T44,T201

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T200,T201,T202
1	1	Covered	T200,T201,T202

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T200,T44,T201
1	0	Covered	T200,T201,T202
1	1	Covered	T200,T201,T202

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T200,T201,T202

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T44,T201
0	Covered	T200,T201,T202

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T44,T201
0	Covered	T200,T201,T202

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402887193	393876803	0	0
CheckNGreaterZero_A	952	952	0	0
GntImpliesReady_A	402887193	4310	0	0
GntImpliesValid_A	402887193	4310	0	0
GrantKnown_A	402887193	393876803	0	0
IdxKnown_A	402887193	393876803	0	0
IndexIsCorrect_A	402887193	4310	0	0
NoReadyValidNoGrant_A	402887193	0	0	0
Priority_A	402887193	4310	0	0
ReadyAndValidImplyGrant_A	402887193	4310	0	0
ReqAndReadyImplyGrant_A	402887193	4310	0	0
ReqImpliesValid_A	402887193	4310	0	0
ValidKnown_A	402887193	393876803	0	0
gen_data_port_assertion.DataFlow_A	402887193	4310	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	4310	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	1429	0	0
T201	0	1442	0	0
T202	0	1439	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T200,T44,T201
0	1	Covered	T200,T201,T202
1	0	Covered	T44

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T44,T201
1	Covered	T200,T44,T201

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T200,T44,T201
1	Covered	T200,T44,T201

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T200,T201,T202
1	1	Covered	T200,T44,T201

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T200,T44,T201
1	0	Covered	T200,T44,T201
1	1	Covered	T200,T201,T202

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T200,T44,T201

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T44,T201
0	Covered	T200,T44,T201

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T200,T44,T201
0	Covered	T200,T44,T201

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	402887193	393876803	0	0
CheckNGreaterZero_A	952	952	0	0
GntImpliesReady_A	402887193	1032	0	0
GntImpliesValid_A	402887193	1032	0	0
GrantKnown_A	402887193	393876803	0	0
IdxKnown_A	402887193	393876803	0	0
IndexIsCorrect_A	402887193	1032	0	0
NoReadyValidNoGrant_A	402887193	0	0	0
Priority_A	402887193	1032	0	0
ReadyAndValidImplyGrant_A	402887193	1032	0	0
ReqAndReadyImplyGrant_A	402887193	1032	0	0
ReqImpliesValid_A	402887193	1032	0	0
ValidKnown_A	402887193	393876803	0	0
gen_data_port_assertion.DataFlow_A	402887193	1032	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	952	952	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T20	1	1	0	0
T33	1	1	0	0
T50	1	1	0	0
T51	1	1	0	0
T67	1	1	0	0
T81	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	393876803	0	0
T1	53377	53319	0	0
T2	356036	355985	0	0
T3	202622	202517	0	0
T4	104946	104849	0	0
T20	175818	175807	0	0
T33	278985	278872	0	0
T50	342668	342606	0	0
T51	362939	362877	0	0
T67	182258	182200	0	0
T81	73338	73280	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	402887193	1032	0	0
T52	133394	0	0	0
T125	525703	0	0	0
T151	95992	0	0	0
T169	207026	0	0	0
T188	36050	0	0	0
T200	80879	344	0	0
T201	0	344	0	0
T202	0	344	0	0
T288	280080	0	0	0
T289	543120	0	0	0
T290	280537	0	0	0
T291	375471	0	0	0