| T552 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.4026410446 |
|
|
Mar 10 02:58:49 PM PDT 24 |
Mar 10 03:19:49 PM PDT 24 |
8128223572 ps |
| T553 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.159593570 |
|
|
Mar 10 03:24:21 PM PDT 24 |
Mar 10 04:27:04 PM PDT 24 |
23624856040 ps |
| T349 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2265025465 |
|
|
Mar 10 03:22:56 PM PDT 24 |
Mar 10 03:35:49 PM PDT 24 |
4545697448 ps |
| T237 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.3601669619 |
|
|
Mar 10 03:15:14 PM PDT 24 |
Mar 10 03:26:02 PM PDT 24 |
5284275301 ps |
| T554 |
/workspace/coverage/default/2.chip_sw_aes_idle.1438465591 |
|
|
Mar 10 03:18:33 PM PDT 24 |
Mar 10 03:21:31 PM PDT 24 |
2452713468 ps |
| T421 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.629145928 |
|
|
Mar 10 03:27:53 PM PDT 24 |
Mar 10 03:36:25 PM PDT 24 |
4001244140 ps |
| T183 |
/workspace/coverage/default/0.rom_raw_unlock.3597499297 |
|
|
Mar 10 03:00:20 PM PDT 24 |
Mar 10 03:35:21 PM PDT 24 |
14680703511 ps |
| T555 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.2041566719 |
|
|
Mar 10 03:23:17 PM PDT 24 |
Mar 10 03:32:17 PM PDT 24 |
7141109622 ps |
| T219 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3374596501 |
|
|
Mar 10 03:14:04 PM PDT 24 |
Mar 10 04:40:22 PM PDT 24 |
50555483774 ps |
| T511 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.2800064782 |
|
|
Mar 10 03:27:48 PM PDT 24 |
Mar 10 03:36:36 PM PDT 24 |
4285436408 ps |
| T465 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.490033293 |
|
|
Mar 10 03:22:07 PM PDT 24 |
Mar 10 03:33:21 PM PDT 24 |
5293880792 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.1537280612 |
|
|
Mar 10 02:58:25 PM PDT 24 |
Mar 10 03:09:31 PM PDT 24 |
6335080740 ps |
| T330 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3233465980 |
|
|
Mar 10 03:12:56 PM PDT 24 |
Mar 10 03:30:07 PM PDT 24 |
5985227684 ps |
| T556 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.2594307117 |
|
|
Mar 10 03:05:21 PM PDT 24 |
Mar 10 03:38:55 PM PDT 24 |
9066519625 ps |
| T557 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.3622901817 |
|
|
Mar 10 02:57:48 PM PDT 24 |
Mar 10 03:02:35 PM PDT 24 |
3086178977 ps |
| T180 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.2619582237 |
|
|
Mar 10 03:05:50 PM PDT 24 |
Mar 10 03:16:14 PM PDT 24 |
3973514204 ps |
| T558 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.3144721016 |
|
|
Mar 10 02:59:41 PM PDT 24 |
Mar 10 03:19:12 PM PDT 24 |
10566485348 ps |
| T55 |
/workspace/coverage/default/1.chip_sw_alert_test.3534992340 |
|
|
Mar 10 03:02:45 PM PDT 24 |
Mar 10 03:07:52 PM PDT 24 |
3044375368 ps |
| T146 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.688345763 |
|
|
Mar 10 03:20:17 PM PDT 24 |
Mar 10 03:31:46 PM PDT 24 |
4741540047 ps |
| T559 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.1573049202 |
|
|
Mar 10 03:01:03 PM PDT 24 |
Mar 10 03:10:03 PM PDT 24 |
5183242684 ps |
| T560 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.2806682819 |
|
|
Mar 10 03:01:16 PM PDT 24 |
Mar 10 03:05:36 PM PDT 24 |
2592408640 ps |
| T292 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1544915802 |
|
|
Mar 10 03:18:03 PM PDT 24 |
Mar 10 04:12:26 PM PDT 24 |
15584230960 ps |
| T561 |
/workspace/coverage/default/9.chip_sw_uart_rand_baudrate.30641775 |
|
|
Mar 10 03:22:43 PM PDT 24 |
Mar 10 04:08:58 PM PDT 24 |
14261198128 ps |
| T562 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.2987469949 |
|
|
Mar 10 03:23:22 PM PDT 24 |
Mar 10 03:28:23 PM PDT 24 |
2599318122 ps |
| T233 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.950229227 |
|
|
Mar 10 03:13:30 PM PDT 24 |
Mar 10 03:27:29 PM PDT 24 |
4128411846 ps |
| T563 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1799185356 |
|
|
Mar 10 03:14:03 PM PDT 24 |
Mar 10 03:23:37 PM PDT 24 |
5840594834 ps |
| T564 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.2285015624 |
|
|
Mar 10 03:02:33 PM PDT 24 |
Mar 10 03:11:09 PM PDT 24 |
4484975400 ps |
| T384 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.2081562255 |
|
|
Mar 10 03:04:36 PM PDT 24 |
Mar 10 03:11:19 PM PDT 24 |
2585074240 ps |
| T496 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.2366510767 |
|
|
Mar 10 03:31:04 PM PDT 24 |
Mar 10 03:41:41 PM PDT 24 |
5759824802 ps |
| T565 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.2554915784 |
|
|
Mar 10 02:57:58 PM PDT 24 |
Mar 10 03:13:47 PM PDT 24 |
5921050004 ps |
| T513 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.1643828140 |
|
|
Mar 10 03:31:19 PM PDT 24 |
Mar 10 03:39:50 PM PDT 24 |
5663801820 ps |
| T566 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.3306328942 |
|
|
Mar 10 03:18:16 PM PDT 24 |
Mar 10 03:28:18 PM PDT 24 |
4677689352 ps |
| T567 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2469773943 |
|
|
Mar 10 02:58:54 PM PDT 24 |
Mar 10 03:03:30 PM PDT 24 |
2892575952 ps |
| T261 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.2201504685 |
|
|
Mar 10 03:05:57 PM PDT 24 |
Mar 10 03:10:47 PM PDT 24 |
2922900688 ps |
| T457 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.1220984045 |
|
|
Mar 10 03:28:19 PM PDT 24 |
Mar 10 03:34:52 PM PDT 24 |
3484763974 ps |
| T568 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.576224238 |
|
|
Mar 10 03:18:19 PM PDT 24 |
Mar 10 03:24:50 PM PDT 24 |
5341892176 ps |
| T346 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.397534104 |
|
|
Mar 10 03:02:43 PM PDT 24 |
Mar 10 03:14:17 PM PDT 24 |
4346562118 ps |
| T569 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.3220333373 |
|
|
Mar 10 02:58:48 PM PDT 24 |
Mar 10 03:03:20 PM PDT 24 |
2679756480 ps |
| T225 |
/workspace/coverage/default/0.chip_sw_flash_init.2408644828 |
|
|
Mar 10 02:58:25 PM PDT 24 |
Mar 10 03:39:59 PM PDT 24 |
17356275560 ps |
| T570 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1792012037 |
|
|
Mar 10 03:12:59 PM PDT 24 |
Mar 10 03:38:33 PM PDT 24 |
6850228424 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.1015004091 |
|
|
Mar 10 03:13:44 PM PDT 24 |
Mar 10 03:18:12 PM PDT 24 |
3020344145 ps |
| T446 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.4067058865 |
|
|
Mar 10 03:34:21 PM PDT 24 |
Mar 10 03:44:16 PM PDT 24 |
5020760848 ps |
| T571 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2996993168 |
|
|
Mar 10 03:00:56 PM PDT 24 |
Mar 10 03:05:01 PM PDT 24 |
2911106952 ps |
| T327 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3168895032 |
|
|
Mar 10 03:16:07 PM PDT 24 |
Mar 10 03:41:47 PM PDT 24 |
6878794262 ps |
| T572 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2820538616 |
|
|
Mar 10 03:03:17 PM PDT 24 |
Mar 10 03:54:01 PM PDT 24 |
11483975647 ps |
| T360 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3412927188 |
|
|
Mar 10 03:31:36 PM PDT 24 |
Mar 10 03:41:39 PM PDT 24 |
4520898520 ps |
| T573 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.352378323 |
|
|
Mar 10 03:15:15 PM PDT 24 |
Mar 10 03:51:09 PM PDT 24 |
9325409010 ps |
| T362 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.2564940291 |
|
|
Mar 10 03:15:12 PM PDT 24 |
Mar 10 03:19:44 PM PDT 24 |
3143936444 ps |
| T295 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.351671583 |
|
|
Mar 10 03:19:14 PM PDT 24 |
Mar 10 03:29:27 PM PDT 24 |
4811932293 ps |
| T574 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2115120601 |
|
|
Mar 10 03:09:00 PM PDT 24 |
Mar 10 03:27:17 PM PDT 24 |
7247008825 ps |
| T206 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.2117129084 |
|
|
Mar 10 02:59:38 PM PDT 24 |
Mar 10 03:11:50 PM PDT 24 |
4360885688 ps |
| T80 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3740083043 |
|
|
Mar 10 03:05:31 PM PDT 24 |
Mar 10 03:12:38 PM PDT 24 |
3236775125 ps |
| T356 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.4142680452 |
|
|
Mar 10 03:01:23 PM PDT 24 |
Mar 10 03:30:20 PM PDT 24 |
11992600806 ps |
| T491 |
/workspace/coverage/default/66.chip_sw_alert_handler_lpg_sleep_mode_alerts.210089166 |
|
|
Mar 10 03:28:25 PM PDT 24 |
Mar 10 03:35:30 PM PDT 24 |
3631142630 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2871570192 |
|
|
Mar 10 03:23:24 PM PDT 24 |
Mar 10 03:55:52 PM PDT 24 |
8739962372 ps |
| T299 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1878237341 |
|
|
Mar 10 03:31:12 PM PDT 24 |
Mar 10 03:42:14 PM PDT 24 |
5471906728 ps |
| T438 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.798118919 |
|
|
Mar 10 03:28:29 PM PDT 24 |
Mar 10 03:42:52 PM PDT 24 |
4884644880 ps |
| T575 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1348596279 |
|
|
Mar 10 03:05:29 PM PDT 24 |
Mar 10 03:09:25 PM PDT 24 |
3210430302 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.3946903193 |
|
|
Mar 10 02:58:24 PM PDT 24 |
Mar 10 03:27:52 PM PDT 24 |
21700479796 ps |
| T350 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.3832698927 |
|
|
Mar 10 03:14:16 PM PDT 24 |
Mar 10 03:27:30 PM PDT 24 |
4304015332 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.4171915283 |
|
|
Mar 10 03:00:18 PM PDT 24 |
Mar 10 03:10:38 PM PDT 24 |
4169537231 ps |
| T576 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.4146649882 |
|
|
Mar 10 02:58:55 PM PDT 24 |
Mar 10 03:17:50 PM PDT 24 |
7280430006 ps |
| T83 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.746876101 |
|
|
Mar 10 03:25:54 PM PDT 24 |
Mar 10 03:38:06 PM PDT 24 |
4109752624 ps |
| T577 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.943622011 |
|
|
Mar 10 02:58:08 PM PDT 24 |
Mar 10 03:01:23 PM PDT 24 |
2167698024 ps |
| T578 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2209603693 |
|
|
Mar 10 02:57:14 PM PDT 24 |
Mar 10 03:13:14 PM PDT 24 |
5827983895 ps |
| T579 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.87555688 |
|
|
Mar 10 03:04:35 PM PDT 24 |
Mar 10 03:44:32 PM PDT 24 |
22746267005 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.1832589052 |
|
|
Mar 10 03:00:44 PM PDT 24 |
Mar 10 03:10:11 PM PDT 24 |
4455659020 ps |
| T18 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.517644798 |
|
|
Mar 10 03:00:12 PM PDT 24 |
Mar 10 03:06:40 PM PDT 24 |
4312782620 ps |
| T580 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.794720748 |
|
|
Mar 10 03:11:52 PM PDT 24 |
Mar 10 03:19:52 PM PDT 24 |
4409963432 ps |
| T478 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2227054993 |
|
|
Mar 10 03:29:43 PM PDT 24 |
Mar 10 03:36:21 PM PDT 24 |
4117812520 ps |
| T484 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.2415478556 |
|
|
Mar 10 03:30:27 PM PDT 24 |
Mar 10 03:41:39 PM PDT 24 |
6632568432 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.749910602 |
|
|
Mar 10 03:00:04 PM PDT 24 |
Mar 10 03:17:34 PM PDT 24 |
5178733980 ps |
| T507 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2029169301 |
|
|
Mar 10 03:27:26 PM PDT 24 |
Mar 10 03:34:23 PM PDT 24 |
3203535144 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.3859261012 |
|
|
Mar 10 02:57:47 PM PDT 24 |
Mar 10 03:02:02 PM PDT 24 |
3179947448 ps |
| T508 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2040402202 |
|
|
Mar 10 03:27:11 PM PDT 24 |
Mar 10 03:33:05 PM PDT 24 |
3604649356 ps |
| T581 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.347873116 |
|
|
Mar 10 02:58:00 PM PDT 24 |
Mar 10 03:02:24 PM PDT 24 |
2662005599 ps |
| T582 |
/workspace/coverage/default/4.chip_tap_straps_dev.2354686925 |
|
|
Mar 10 03:21:19 PM PDT 24 |
Mar 10 03:49:32 PM PDT 24 |
14843788540 ps |
| T583 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.4187569562 |
|
|
Mar 10 03:04:29 PM PDT 24 |
Mar 10 03:11:30 PM PDT 24 |
5980344984 ps |
| T584 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.799744729 |
|
|
Mar 10 03:11:25 PM PDT 24 |
Mar 10 03:15:37 PM PDT 24 |
2669159408 ps |
| T585 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.4269630909 |
|
|
Mar 10 03:03:03 PM PDT 24 |
Mar 10 03:27:50 PM PDT 24 |
10312000054 ps |
| T586 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.3074955273 |
|
|
Mar 10 02:58:47 PM PDT 24 |
Mar 10 03:05:21 PM PDT 24 |
4370814834 ps |
| T587 |
/workspace/coverage/default/2.chip_sw_example_flash.1845907597 |
|
|
Mar 10 03:12:24 PM PDT 24 |
Mar 10 03:18:23 PM PDT 24 |
3221622332 ps |
| T149 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1049542990 |
|
|
Mar 10 03:13:04 PM PDT 24 |
Mar 10 06:17:36 PM PDT 24 |
58708559320 ps |
| T355 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.214082594 |
|
|
Mar 10 03:00:01 PM PDT 24 |
Mar 10 03:14:39 PM PDT 24 |
4242529560 ps |
| T258 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1876104279 |
|
|
Mar 10 03:23:47 PM PDT 24 |
Mar 10 03:36:39 PM PDT 24 |
5224146730 ps |
| T7 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.600671291 |
|
|
Mar 10 03:03:14 PM PDT 24 |
Mar 10 03:08:27 PM PDT 24 |
2962931194 ps |
| T588 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1438622097 |
|
|
Mar 10 03:06:37 PM PDT 24 |
Mar 10 03:17:18 PM PDT 24 |
5359101224 ps |
| T442 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.4056940585 |
|
|
Mar 10 03:14:07 PM PDT 24 |
Mar 10 03:25:07 PM PDT 24 |
4250967704 ps |
| T589 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.308081083 |
|
|
Mar 10 03:22:51 PM PDT 24 |
Mar 10 03:38:30 PM PDT 24 |
5834809724 ps |
| T73 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.272149349 |
|
|
Mar 10 03:21:22 PM PDT 24 |
Mar 10 03:33:14 PM PDT 24 |
7403854409 ps |
| T590 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.3232157694 |
|
|
Mar 10 03:12:50 PM PDT 24 |
Mar 10 03:17:35 PM PDT 24 |
2855686610 ps |
| T591 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.2218460588 |
|
|
Mar 10 02:57:10 PM PDT 24 |
Mar 10 03:00:47 PM PDT 24 |
2649044471 ps |
| T361 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.767371765 |
|
|
Mar 10 03:31:10 PM PDT 24 |
Mar 10 03:40:01 PM PDT 24 |
5180152416 ps |
| T241 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.4048001853 |
|
|
Mar 10 02:59:34 PM PDT 24 |
Mar 10 03:03:59 PM PDT 24 |
2635518029 ps |
| T436 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2763797235 |
|
|
Mar 10 03:29:14 PM PDT 24 |
Mar 10 03:39:35 PM PDT 24 |
5454284480 ps |
| T592 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2677097242 |
|
|
Mar 10 03:15:13 PM PDT 24 |
Mar 10 04:00:39 PM PDT 24 |
23862065194 ps |
| T593 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.510224403 |
|
|
Mar 10 03:00:03 PM PDT 24 |
Mar 10 03:10:12 PM PDT 24 |
6800445276 ps |
| T594 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1568667365 |
|
|
Mar 10 03:18:39 PM PDT 24 |
Mar 10 03:29:58 PM PDT 24 |
3893052584 ps |
| T259 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.651272739 |
|
|
Mar 10 03:11:35 PM PDT 24 |
Mar 10 03:23:50 PM PDT 24 |
5534032334 ps |
| T515 |
/workspace/coverage/default/5.chip_sw_all_escalation_resets.2364779630 |
|
|
Mar 10 03:23:01 PM PDT 24 |
Mar 10 03:33:20 PM PDT 24 |
5639156918 ps |
| T334 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.893688501 |
|
|
Mar 10 03:15:45 PM PDT 24 |
Mar 10 03:24:01 PM PDT 24 |
5555011656 ps |
| T595 |
/workspace/coverage/default/1.chip_sw_aes_enc.87337693 |
|
|
Mar 10 03:03:09 PM PDT 24 |
Mar 10 03:07:23 PM PDT 24 |
2862240248 ps |
| T596 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.112164353 |
|
|
Mar 10 03:15:51 PM PDT 24 |
Mar 10 03:30:07 PM PDT 24 |
5062998816 ps |
| T597 |
/workspace/coverage/default/2.chip_sw_example_concurrency.4255525330 |
|
|
Mar 10 03:14:07 PM PDT 24 |
Mar 10 03:18:08 PM PDT 24 |
2877517260 ps |
| T166 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en.4002222568 |
|
|
Mar 10 03:02:58 PM PDT 24 |
Mar 10 04:01:18 PM PDT 24 |
19108248359 ps |
| T497 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2848442220 |
|
|
Mar 10 03:31:51 PM PDT 24 |
Mar 10 03:38:53 PM PDT 24 |
3953032504 ps |
| T385 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.1961033607 |
|
|
Mar 10 02:58:58 PM PDT 24 |
Mar 10 03:14:04 PM PDT 24 |
5142598829 ps |
| T598 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.2227174016 |
|
|
Mar 10 03:13:55 PM PDT 24 |
Mar 10 03:31:38 PM PDT 24 |
5076283460 ps |
| T152 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3581083285 |
|
|
Mar 10 03:17:28 PM PDT 24 |
Mar 10 03:21:45 PM PDT 24 |
2630092355 ps |
| T599 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.7757384 |
|
|
Mar 10 03:00:17 PM PDT 24 |
Mar 10 03:15:34 PM PDT 24 |
5107374040 ps |
| T600 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.1592779787 |
|
|
Mar 10 02:58:43 PM PDT 24 |
Mar 10 03:09:49 PM PDT 24 |
5725523248 ps |
| T601 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2828800350 |
|
|
Mar 10 03:19:14 PM PDT 24 |
Mar 10 03:24:55 PM PDT 24 |
2759095534 ps |
| T602 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.1200522993 |
|
|
Mar 10 03:14:55 PM PDT 24 |
Mar 10 04:14:02 PM PDT 24 |
16764008434 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.3946695684 |
|
|
Mar 10 02:56:58 PM PDT 24 |
Mar 10 03:04:58 PM PDT 24 |
3389436720 ps |
| T437 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.4082062801 |
|
|
Mar 10 03:23:45 PM PDT 24 |
Mar 10 03:33:30 PM PDT 24 |
4404916436 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.114485405 |
|
|
Mar 10 02:57:00 PM PDT 24 |
Mar 10 03:12:32 PM PDT 24 |
4688269426 ps |
| T335 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.2264125168 |
|
|
Mar 10 03:02:57 PM PDT 24 |
Mar 10 03:10:44 PM PDT 24 |
4829831876 ps |
| T603 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.1157772691 |
|
|
Mar 10 03:01:01 PM PDT 24 |
Mar 10 03:06:02 PM PDT 24 |
3404820076 ps |
| T604 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.2075627661 |
|
|
Mar 10 03:05:31 PM PDT 24 |
Mar 10 03:33:33 PM PDT 24 |
9032733464 ps |
| T184 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3523554882 |
|
|
Mar 10 03:04:20 PM PDT 24 |
Mar 10 06:10:51 PM PDT 24 |
254287936188 ps |
| T459 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.3511975238 |
|
|
Mar 10 03:30:08 PM PDT 24 |
Mar 10 03:40:30 PM PDT 24 |
5163784610 ps |
| T605 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.4211402330 |
|
|
Mar 10 02:58:37 PM PDT 24 |
Mar 10 03:10:32 PM PDT 24 |
3899154126 ps |
| T606 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2127657837 |
|
|
Mar 10 03:07:27 PM PDT 24 |
Mar 10 03:13:40 PM PDT 24 |
6232567680 ps |
| T273 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2606985272 |
|
|
Mar 10 03:05:11 PM PDT 24 |
Mar 10 03:14:25 PM PDT 24 |
3910543033 ps |
| T114 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.3764641630 |
|
|
Mar 10 03:06:13 PM PDT 24 |
Mar 10 03:14:06 PM PDT 24 |
9320843588 ps |
| T607 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.3026208063 |
|
|
Mar 10 03:04:02 PM PDT 24 |
Mar 10 03:09:37 PM PDT 24 |
2858292598 ps |
| T608 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.3395454594 |
|
|
Mar 10 03:05:05 PM PDT 24 |
Mar 10 03:56:39 PM PDT 24 |
12199758279 ps |
| T609 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.4099161229 |
|
|
Mar 10 03:31:57 PM PDT 24 |
Mar 10 03:42:08 PM PDT 24 |
3954642922 ps |
| T610 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.1277436157 |
|
|
Mar 10 03:14:11 PM PDT 24 |
Mar 10 03:22:05 PM PDT 24 |
4222891679 ps |
| T460 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.713819929 |
|
|
Mar 10 03:23:12 PM PDT 24 |
Mar 10 03:37:37 PM PDT 24 |
5028135336 ps |
| T368 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1713093267 |
|
|
Mar 10 03:26:50 PM PDT 24 |
Mar 10 03:32:46 PM PDT 24 |
4130341768 ps |
| T341 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.4287061700 |
|
|
Mar 10 02:58:52 PM PDT 24 |
Mar 10 03:30:44 PM PDT 24 |
7083325780 ps |
| T611 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.483714526 |
|
|
Mar 10 03:24:17 PM PDT 24 |
Mar 10 03:39:47 PM PDT 24 |
5374951926 ps |
| T369 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2471634917 |
|
|
Mar 10 03:29:26 PM PDT 24 |
Mar 10 03:40:27 PM PDT 24 |
5813529602 ps |
| T274 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2429591355 |
|
|
Mar 10 03:01:36 PM PDT 24 |
Mar 10 03:13:22 PM PDT 24 |
5538262992 ps |
| T477 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.3256778717 |
|
|
Mar 10 03:31:15 PM PDT 24 |
Mar 10 03:43:16 PM PDT 24 |
5747182974 ps |
| T612 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.3126436046 |
|
|
Mar 10 03:00:06 PM PDT 24 |
Mar 10 03:14:44 PM PDT 24 |
5217574610 ps |
| T613 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_wakeup.1449377680 |
|
|
Mar 10 02:58:09 PM PDT 24 |
Mar 10 03:03:26 PM PDT 24 |
4605753080 ps |
| T614 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.3378349315 |
|
|
Mar 10 02:57:37 PM PDT 24 |
Mar 10 03:03:31 PM PDT 24 |
5095864910 ps |
| T615 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2579517974 |
|
|
Mar 10 03:13:01 PM PDT 24 |
Mar 10 03:18:51 PM PDT 24 |
3783829080 ps |
| T616 |
/workspace/coverage/default/75.chip_sw_all_escalation_resets.2106164766 |
|
|
Mar 10 03:30:59 PM PDT 24 |
Mar 10 03:41:11 PM PDT 24 |
5187114920 ps |
| T314 |
/workspace/coverage/default/2.rom_raw_unlock.1131238514 |
|
|
Mar 10 03:21:06 PM PDT 24 |
Mar 10 03:52:57 PM PDT 24 |
14906595816 ps |
| T617 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.858834124 |
|
|
Mar 10 03:00:42 PM PDT 24 |
Mar 10 03:15:08 PM PDT 24 |
10306836408 ps |
| T300 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.4118537298 |
|
|
Mar 10 03:05:04 PM PDT 24 |
Mar 10 04:15:54 PM PDT 24 |
17833207636 ps |
| T481 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2367677742 |
|
|
Mar 10 03:27:53 PM PDT 24 |
Mar 10 03:33:40 PM PDT 24 |
3631668344 ps |
| T618 |
/workspace/coverage/default/0.chip_sw_aes_idle.1870760957 |
|
|
Mar 10 03:00:14 PM PDT 24 |
Mar 10 03:03:39 PM PDT 24 |
3276860108 ps |
| T390 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.2002911792 |
|
|
Mar 10 03:31:21 PM PDT 24 |
Mar 10 03:42:00 PM PDT 24 |
5813584910 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2204596842 |
|
|
Mar 10 02:57:18 PM PDT 24 |
Mar 10 06:00:22 PM PDT 24 |
64066014967 ps |
| T619 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3795237224 |
|
|
Mar 10 02:57:36 PM PDT 24 |
Mar 10 03:16:52 PM PDT 24 |
5204020946 ps |
| T620 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.480521174 |
|
|
Mar 10 03:06:57 PM PDT 24 |
Mar 10 03:54:25 PM PDT 24 |
11609184716 ps |
| T621 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.2503253153 |
|
|
Mar 10 03:21:32 PM PDT 24 |
Mar 10 03:58:13 PM PDT 24 |
13445033404 ps |
| T622 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.3919645277 |
|
|
Mar 10 03:12:24 PM PDT 24 |
Mar 10 03:30:00 PM PDT 24 |
5125886524 ps |
| T623 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_por_reset.461580671 |
|
|
Mar 10 03:14:56 PM PDT 24 |
Mar 10 03:29:33 PM PDT 24 |
8575180968 ps |
| T312 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3305575561 |
|
|
Mar 10 02:58:20 PM PDT 24 |
Mar 10 03:01:51 PM PDT 24 |
2295026740 ps |
| T624 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.2687615553 |
|
|
Mar 10 03:04:19 PM PDT 24 |
Mar 10 03:14:23 PM PDT 24 |
4684458296 ps |
| T625 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2907347994 |
|
|
Mar 10 03:12:38 PM PDT 24 |
Mar 10 03:28:02 PM PDT 24 |
5448105576 ps |
| T626 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2721476296 |
|
|
Mar 10 03:00:17 PM PDT 24 |
Mar 10 04:09:51 PM PDT 24 |
16966805550 ps |
| T22 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.1734642535 |
|
|
Mar 10 03:14:49 PM PDT 24 |
Mar 10 03:40:24 PM PDT 24 |
23517085928 ps |
| T386 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3592034653 |
|
|
Mar 10 03:09:48 PM PDT 24 |
Mar 10 04:07:02 PM PDT 24 |
25223913385 ps |
| T627 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.3806519535 |
|
|
Mar 10 03:01:37 PM PDT 24 |
Mar 10 03:06:43 PM PDT 24 |
3510568866 ps |
| T343 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.3728027106 |
|
|
Mar 10 03:14:14 PM PDT 24 |
Mar 10 03:23:06 PM PDT 24 |
4157641512 ps |
| T628 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2415658214 |
|
|
Mar 10 03:04:29 PM PDT 24 |
Mar 10 03:42:45 PM PDT 24 |
8847158206 ps |
| T629 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.768114908 |
|
|
Mar 10 03:07:33 PM PDT 24 |
Mar 10 03:17:01 PM PDT 24 |
5214202044 ps |
| T415 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.2154584971 |
|
|
Mar 10 03:00:17 PM PDT 24 |
Mar 10 03:02:04 PM PDT 24 |
1948911942 ps |
| T213 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2988128269 |
|
|
Mar 10 03:05:50 PM PDT 24 |
Mar 10 03:23:54 PM PDT 24 |
6426910340 ps |
| T630 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2500791937 |
|
|
Mar 10 03:04:36 PM PDT 24 |
Mar 10 03:11:27 PM PDT 24 |
3366633332 ps |
| T161 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.3111245885 |
|
|
Mar 10 03:09:47 PM PDT 24 |
Mar 10 04:12:08 PM PDT 24 |
17886045169 ps |
| T631 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1228935162 |
|
|
Mar 10 03:00:49 PM PDT 24 |
Mar 10 03:05:24 PM PDT 24 |
3211104984 ps |
| T632 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3174841870 |
|
|
Mar 10 03:04:20 PM PDT 24 |
Mar 10 03:19:58 PM PDT 24 |
5358216618 ps |
| T633 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.3999508957 |
|
|
Mar 10 03:21:02 PM PDT 24 |
Mar 10 03:39:35 PM PDT 24 |
5193912940 ps |
| T498 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.1078137867 |
|
|
Mar 10 03:24:33 PM PDT 24 |
Mar 10 03:30:05 PM PDT 24 |
3143848250 ps |
| T634 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.1325942743 |
|
|
Mar 10 03:03:59 PM PDT 24 |
Mar 10 03:39:28 PM PDT 24 |
8524454478 ps |
| T223 |
/workspace/coverage/default/2.chip_sw_flash_init.156908999 |
|
|
Mar 10 03:12:33 PM PDT 24 |
Mar 10 03:46:41 PM PDT 24 |
21577473563 ps |
| T635 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3728786476 |
|
|
Mar 10 03:06:50 PM PDT 24 |
Mar 10 03:18:02 PM PDT 24 |
3999516728 ps |
| T468 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2055684470 |
|
|
Mar 10 03:26:42 PM PDT 24 |
Mar 10 03:40:31 PM PDT 24 |
5729745352 ps |
| T636 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.3440002510 |
|
|
Mar 10 02:59:02 PM PDT 24 |
Mar 10 03:16:20 PM PDT 24 |
6127598519 ps |
| T347 |
/workspace/coverage/default/1.chip_sw_hmac_enc.4172208598 |
|
|
Mar 10 03:08:32 PM PDT 24 |
Mar 10 03:12:48 PM PDT 24 |
3253441260 ps |
| T453 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1765377714 |
|
|
Mar 10 03:27:40 PM PDT 24 |
Mar 10 03:35:30 PM PDT 24 |
3338737080 ps |
| T637 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.4263261594 |
|
|
Mar 10 03:31:37 PM PDT 24 |
Mar 10 03:41:42 PM PDT 24 |
4695668260 ps |
| T638 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.341994703 |
|
|
Mar 10 03:16:08 PM PDT 24 |
Mar 10 03:19:43 PM PDT 24 |
2880502440 ps |
| T639 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.2805863061 |
|
|
Mar 10 03:02:33 PM PDT 24 |
Mar 10 03:23:12 PM PDT 24 |
6503114920 ps |
| T419 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.355995546 |
|
|
Mar 10 03:02:43 PM PDT 24 |
Mar 10 04:08:34 PM PDT 24 |
21020458161 ps |
| T640 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.4179418779 |
|
|
Mar 10 03:08:04 PM PDT 24 |
Mar 10 03:15:40 PM PDT 24 |
7968127084 ps |
| T427 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.847462124 |
|
|
Mar 10 03:29:04 PM PDT 24 |
Mar 10 03:38:09 PM PDT 24 |
4473382600 ps |
| T641 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1230760749 |
|
|
Mar 10 03:29:33 PM PDT 24 |
Mar 10 03:35:10 PM PDT 24 |
3554074266 ps |
| T642 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.1077768287 |
|
|
Mar 10 03:10:59 PM PDT 24 |
Mar 10 03:40:24 PM PDT 24 |
8579840610 ps |
| T461 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.2755617505 |
|
|
Mar 10 03:26:24 PM PDT 24 |
Mar 10 03:36:25 PM PDT 24 |
5238357892 ps |
| T643 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.862725934 |
|
|
Mar 10 03:09:51 PM PDT 24 |
Mar 10 03:15:09 PM PDT 24 |
3693208356 ps |
| T644 |
/workspace/coverage/default/2.chip_sw_kmac_entropy.2319196657 |
|
|
Mar 10 03:14:58 PM PDT 24 |
Mar 10 03:19:38 PM PDT 24 |
3119091384 ps |
| T645 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.904797850 |
|
|
Mar 10 03:23:23 PM PDT 24 |
Mar 10 03:27:19 PM PDT 24 |
2613841824 ps |
| T257 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod.48414037 |
|
|
Mar 10 03:06:10 PM PDT 24 |
Mar 10 04:00:26 PM PDT 24 |
12452780958 ps |
| T34 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.591152339 |
|
|
Mar 10 03:12:34 PM PDT 24 |
Mar 10 03:18:29 PM PDT 24 |
3121414264 ps |
| T646 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.3944402502 |
|
|
Mar 10 02:59:32 PM PDT 24 |
Mar 10 03:28:31 PM PDT 24 |
7566443468 ps |
| T647 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.2642926017 |
|
|
Mar 10 03:18:47 PM PDT 24 |
Mar 10 03:33:41 PM PDT 24 |
7234592392 ps |
| T423 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.723599795 |
|
|
Mar 10 03:27:41 PM PDT 24 |
Mar 10 03:35:05 PM PDT 24 |
3699695160 ps |
| T648 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.2374732484 |
|
|
Mar 10 03:04:20 PM PDT 24 |
Mar 10 03:08:22 PM PDT 24 |
2261608348 ps |
| T190 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3065548336 |
|
|
Mar 10 02:58:04 PM PDT 24 |
Mar 10 03:13:07 PM PDT 24 |
4968973000 ps |
| T391 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4149820289 |
|
|
Mar 10 03:31:07 PM PDT 24 |
Mar 10 03:38:04 PM PDT 24 |
3672404170 ps |
| T252 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2998484764 |
|
|
Mar 10 03:26:47 PM PDT 24 |
Mar 10 03:37:08 PM PDT 24 |
5782726366 ps |
| T447 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.322392140 |
|
|
Mar 10 03:29:53 PM PDT 24 |
Mar 10 03:36:05 PM PDT 24 |
4068392976 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.1806319214 |
|
|
Mar 10 03:20:46 PM PDT 24 |
Mar 10 03:25:49 PM PDT 24 |
3026114659 ps |
| T344 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1116067164 |
|
|
Mar 10 03:28:32 PM PDT 24 |
Mar 10 03:38:26 PM PDT 24 |
5787777458 ps |
| T649 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.2240081498 |
|
|
Mar 10 03:07:22 PM PDT 24 |
Mar 10 03:40:36 PM PDT 24 |
8196983751 ps |
| T392 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2907231465 |
|
|
Mar 10 03:29:05 PM PDT 24 |
Mar 10 03:39:51 PM PDT 24 |
4412565646 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2088979945 |
|
|
Mar 10 03:12:26 PM PDT 24 |
Mar 10 03:33:59 PM PDT 24 |
8408584780 ps |
| T650 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.3561784106 |
|
|
Mar 10 03:04:51 PM PDT 24 |
Mar 10 03:38:58 PM PDT 24 |
9302200513 ps |
| T490 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.235557821 |
|
|
Mar 10 03:30:22 PM PDT 24 |
Mar 10 03:46:11 PM PDT 24 |
6015663436 ps |
| T275 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.1440463354 |
|
|
Mar 10 03:03:50 PM PDT 24 |
Mar 10 03:11:15 PM PDT 24 |
3513891860 ps |
| T651 |
/workspace/coverage/default/1.chip_sw_example_concurrency.4251419826 |
|
|
Mar 10 03:02:44 PM PDT 24 |
Mar 10 03:07:45 PM PDT 24 |
3619429204 ps |
| T254 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.2324280427 |
|
|
Mar 10 03:25:20 PM PDT 24 |
Mar 10 03:31:34 PM PDT 24 |
3515853000 ps |
| T220 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1280933164 |
|
|
Mar 10 02:57:50 PM PDT 24 |
Mar 10 04:35:25 PM PDT 24 |
49152626480 ps |
| T277 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3215109760 |
|
|
Mar 10 03:24:30 PM PDT 24 |
Mar 10 03:36:51 PM PDT 24 |
6430722320 ps |
| T278 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.337347780 |
|
|
Mar 10 02:58:01 PM PDT 24 |
Mar 10 03:11:33 PM PDT 24 |
5016908208 ps |
| T279 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2922851437 |
|
|
Mar 10 03:00:04 PM PDT 24 |
Mar 10 03:11:34 PM PDT 24 |
4060163020 ps |
| T280 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.1462274499 |
|
|
Mar 10 03:19:32 PM PDT 24 |
Mar 10 03:23:43 PM PDT 24 |
3288996067 ps |
| T281 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1613469836 |
|
|
Mar 10 03:28:17 PM PDT 24 |
Mar 10 03:40:11 PM PDT 24 |
4580078936 ps |
| T282 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.3525859134 |
|
|
Mar 10 03:21:58 PM PDT 24 |
Mar 10 03:31:45 PM PDT 24 |
5352954880 ps |
| T283 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.2851594656 |
|
|
Mar 10 03:10:30 PM PDT 24 |
Mar 10 03:15:38 PM PDT 24 |
3289065664 ps |
| T284 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4073467338 |
|
|
Mar 10 02:58:13 PM PDT 24 |
Mar 10 03:07:13 PM PDT 24 |
4802466088 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1914095298 |
|
|
Mar 10 03:00:15 PM PDT 24 |
Mar 10 03:06:21 PM PDT 24 |
3156545864 ps |
| T652 |
/workspace/coverage/default/1.chip_sival_flash_info_access.4189056019 |
|
|
Mar 10 03:00:09 PM PDT 24 |
Mar 10 03:05:54 PM PDT 24 |
2921863106 ps |
| T424 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.391801288 |
|
|
Mar 10 03:22:16 PM PDT 24 |
Mar 10 03:27:56 PM PDT 24 |
3809223256 ps |
| T653 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.2395904654 |
|
|
Mar 10 03:04:41 PM PDT 24 |
Mar 10 03:49:05 PM PDT 24 |
9391060512 ps |
| T654 |
/workspace/coverage/default/2.chip_sw_aes_smoketest.2236130290 |
|
|
Mar 10 03:21:36 PM PDT 24 |
Mar 10 03:26:36 PM PDT 24 |
2769160502 ps |
| T655 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.1280816063 |
|
|
Mar 10 02:59:14 PM PDT 24 |
Mar 10 03:07:11 PM PDT 24 |
3976506795 ps |
| T44 |
/workspace/coverage/default/0.chip_jtag_csr_rw.3765571048 |
|
|
Mar 10 02:50:23 PM PDT 24 |
Mar 10 03:12:22 PM PDT 24 |
11630404595 ps |
| T403 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1023522986 |
|
|
Mar 10 03:15:14 PM PDT 24 |
Mar 10 03:22:08 PM PDT 24 |
3134852347 ps |
| T404 |
/workspace/coverage/default/0.chip_tap_straps_dev.2568398384 |
|
|
Mar 10 02:56:49 PM PDT 24 |
Mar 10 03:00:52 PM PDT 24 |
3003167744 ps |
| T405 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.21763245 |
|
|
Mar 10 02:58:41 PM PDT 24 |
Mar 10 03:15:01 PM PDT 24 |
4971356198 ps |
| T370 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.1630648568 |
|
|
Mar 10 03:24:51 PM PDT 24 |
Mar 10 03:35:00 PM PDT 24 |
5416276800 ps |
| T337 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.3275676537 |
|
|
Mar 10 03:09:29 PM PDT 24 |
Mar 10 03:23:14 PM PDT 24 |
4123329163 ps |
| T406 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1944309944 |
|
|
Mar 10 03:24:29 PM PDT 24 |
Mar 10 03:30:50 PM PDT 24 |
4082841280 ps |
| T407 |
/workspace/coverage/default/0.chip_sw_alert_handler_escalation.1523787348 |
|
|
Mar 10 02:59:13 PM PDT 24 |
Mar 10 03:10:28 PM PDT 24 |
5610305568 ps |
| T408 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.3768373938 |
|
|
Mar 10 03:03:03 PM PDT 24 |
Mar 10 03:18:10 PM PDT 24 |
5307687712 ps |
| T409 |
/workspace/coverage/default/1.chip_tap_straps_dev.586811843 |
|
|
Mar 10 03:08:24 PM PDT 24 |
Mar 10 03:10:19 PM PDT 24 |
2554331676 ps |
| T230 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.1224272438 |
|
|
Mar 10 03:13:48 PM PDT 24 |
Mar 10 04:46:48 PM PDT 24 |
49991965272 ps |
| T416 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.871725419 |
|
|
Mar 10 02:58:13 PM PDT 24 |
Mar 10 03:00:15 PM PDT 24 |
3035849782 ps |
| T656 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3616903507 |
|
|
Mar 10 03:23:28 PM PDT 24 |
Mar 10 03:54:33 PM PDT 24 |
8952217032 ps |
| T657 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.3974469452 |
|
|
Mar 10 03:15:05 PM PDT 24 |
Mar 10 03:29:56 PM PDT 24 |
5305444296 ps |
| T658 |
/workspace/coverage/default/0.chip_sw_entropy_src_kat_test.255721224 |
|
|
Mar 10 02:58:38 PM PDT 24 |
Mar 10 03:01:55 PM PDT 24 |
2792830254 ps |
| T208 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1298547626 |
|
|
Mar 10 03:00:17 PM PDT 24 |
Mar 10 03:11:08 PM PDT 24 |
3158824940 ps |
| T659 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.1437110155 |
|
|
Mar 10 03:05:33 PM PDT 24 |
Mar 10 03:09:31 PM PDT 24 |
2901011621 ps |
| T660 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.1882267176 |
|
|
Mar 10 03:05:11 PM PDT 24 |
Mar 10 03:47:05 PM PDT 24 |
9124138677 ps |
| T448 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.1411875047 |
|
|
Mar 10 03:23:34 PM PDT 24 |
Mar 10 03:31:48 PM PDT 24 |
3048650316 ps |
| T661 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.828485787 |
|
|
Mar 10 03:20:19 PM PDT 24 |
Mar 10 03:28:07 PM PDT 24 |
3469016938 ps |
| T486 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.379560128 |
|
|
Mar 10 03:30:23 PM PDT 24 |
Mar 10 03:41:21 PM PDT 24 |
5433560208 ps |
| T662 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1774284335 |
|
|
Mar 10 03:12:46 PM PDT 24 |
Mar 10 03:19:32 PM PDT 24 |
3468798640 ps |
| T12 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.712189435 |
|
|
Mar 10 02:57:52 PM PDT 24 |
Mar 10 03:10:02 PM PDT 24 |
7073493015 ps |
| T663 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3669117544 |
|
|
Mar 10 03:19:46 PM PDT 24 |
Mar 10 03:37:53 PM PDT 24 |
7995101440 ps |
| T664 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.666705905 |
|
|
Mar 10 03:16:46 PM PDT 24 |
Mar 10 03:22:50 PM PDT 24 |
2577394707 ps |