| T665 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2341092859 |
|
|
Mar 10 03:23:16 PM PDT 24 |
Mar 10 04:09:11 PM PDT 24 |
23108112044 ps |
| T666 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.3095447769 |
|
|
Mar 10 03:20:15 PM PDT 24 |
Mar 10 03:25:29 PM PDT 24 |
2410858693 ps |
| T667 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.2184344895 |
|
|
Mar 10 03:14:15 PM PDT 24 |
Mar 10 03:18:48 PM PDT 24 |
3723190320 ps |
| T668 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.135933676 |
|
|
Mar 10 03:02:09 PM PDT 24 |
Mar 10 03:09:46 PM PDT 24 |
5469247770 ps |
| T669 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.4066446355 |
|
|
Mar 10 03:20:48 PM PDT 24 |
Mar 10 03:25:32 PM PDT 24 |
2830412008 ps |
| T670 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1729958268 |
|
|
Mar 10 03:21:42 PM PDT 24 |
Mar 10 03:38:38 PM PDT 24 |
6179605244 ps |
| T428 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.953023014 |
|
|
Mar 10 03:25:56 PM PDT 24 |
Mar 10 03:34:56 PM PDT 24 |
5241844372 ps |
| T352 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1573141844 |
|
|
Mar 10 02:59:43 PM PDT 24 |
Mar 10 03:04:14 PM PDT 24 |
3127095788 ps |
| T72 |
/workspace/coverage/default/2.chip_tap_straps_rma.756461002 |
|
|
Mar 10 03:18:19 PM PDT 24 |
Mar 10 03:23:36 PM PDT 24 |
3951562081 ps |
| T671 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.1120621895 |
|
|
Mar 10 03:05:32 PM PDT 24 |
Mar 10 03:34:33 PM PDT 24 |
6545398680 ps |
| T353 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.2433817674 |
|
|
Mar 10 03:17:58 PM PDT 24 |
Mar 10 03:22:04 PM PDT 24 |
3418201449 ps |
| T672 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.2571188172 |
|
|
Mar 10 03:18:34 PM PDT 24 |
Mar 10 03:54:11 PM PDT 24 |
20379684476 ps |
| T673 |
/workspace/coverage/default/1.chip_sw_example_rom.515857793 |
|
|
Mar 10 03:00:58 PM PDT 24 |
Mar 10 03:02:53 PM PDT 24 |
2138587288 ps |
| T57 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.2857914309 |
|
|
Mar 10 02:58:23 PM PDT 24 |
Mar 10 03:07:24 PM PDT 24 |
3282329436 ps |
| T674 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2684767278 |
|
|
Mar 10 03:12:27 PM PDT 24 |
Mar 10 03:32:17 PM PDT 24 |
5376378264 ps |
| T454 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.3445359662 |
|
|
Mar 10 03:25:23 PM PDT 24 |
Mar 10 03:34:51 PM PDT 24 |
5443969740 ps |
| T320 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.995617283 |
|
|
Mar 10 03:01:10 PM PDT 24 |
Mar 10 03:04:54 PM PDT 24 |
2577700112 ps |
| T675 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_prod.2885455017 |
|
|
Mar 10 03:17:06 PM PDT 24 |
Mar 10 03:24:28 PM PDT 24 |
3399415600 ps |
| T430 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2178981075 |
|
|
Mar 10 03:28:14 PM PDT 24 |
Mar 10 03:35:22 PM PDT 24 |
3766954200 ps |
| T201 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4133809057 |
|
|
Mar 10 02:58:41 PM PDT 24 |
Mar 10 03:03:37 PM PDT 24 |
2901806916 ps |
| T443 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.347615706 |
|
|
Mar 10 03:28:25 PM PDT 24 |
Mar 10 03:34:28 PM PDT 24 |
4009464836 ps |
| T676 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.215160896 |
|
|
Mar 10 03:05:26 PM PDT 24 |
Mar 10 03:16:30 PM PDT 24 |
4961405280 ps |
| T677 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.3931232034 |
|
|
Mar 10 03:09:16 PM PDT 24 |
Mar 10 03:11:55 PM PDT 24 |
2983386606 ps |
| T493 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.1791987134 |
|
|
Mar 10 03:31:17 PM PDT 24 |
Mar 10 03:39:02 PM PDT 24 |
3954825402 ps |
| T425 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.2249343104 |
|
|
Mar 10 03:27:59 PM PDT 24 |
Mar 10 03:39:19 PM PDT 24 |
5886637500 ps |
| T678 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.4013089175 |
|
|
Mar 10 03:12:38 PM PDT 24 |
Mar 10 03:39:38 PM PDT 24 |
7255611528 ps |
| T434 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.3985926245 |
|
|
Mar 10 03:30:06 PM PDT 24 |
Mar 10 03:36:15 PM PDT 24 |
3872422080 ps |
| T679 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2033794009 |
|
|
Mar 10 03:13:49 PM PDT 24 |
Mar 10 03:23:40 PM PDT 24 |
6772622556 ps |
| T417 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.743197738 |
|
|
Mar 10 03:00:28 PM PDT 24 |
Mar 10 03:02:23 PM PDT 24 |
2873379587 ps |
| T680 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3487900567 |
|
|
Mar 10 03:23:41 PM PDT 24 |
Mar 10 03:39:59 PM PDT 24 |
13026028908 ps |
| T228 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1139045435 |
|
|
Mar 10 03:18:09 PM PDT 24 |
Mar 10 03:46:23 PM PDT 24 |
26604291921 ps |
| T681 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2850244054 |
|
|
Mar 10 03:19:37 PM PDT 24 |
Mar 10 03:31:32 PM PDT 24 |
4186805358 ps |
| T682 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2399725243 |
|
|
Mar 10 03:24:07 PM PDT 24 |
Mar 10 03:59:16 PM PDT 24 |
8648449944 ps |
| T683 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.3970882126 |
|
|
Mar 10 03:21:18 PM PDT 24 |
Mar 10 03:35:43 PM PDT 24 |
5120864436 ps |
| T684 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1192577032 |
|
|
Mar 10 03:03:15 PM PDT 24 |
Mar 10 03:08:03 PM PDT 24 |
3353216426 ps |
| T45 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.694091473 |
|
|
Mar 10 03:09:59 PM PDT 24 |
Mar 10 03:17:52 PM PDT 24 |
3823266440 ps |
| T685 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2553782858 |
|
|
Mar 10 03:03:52 PM PDT 24 |
Mar 10 03:19:41 PM PDT 24 |
5306895432 ps |
| T686 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.1054688887 |
|
|
Mar 10 03:11:37 PM PDT 24 |
Mar 10 03:16:34 PM PDT 24 |
2785558488 ps |
| T687 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1782064266 |
|
|
Mar 10 03:19:32 PM PDT 24 |
Mar 10 03:23:42 PM PDT 24 |
2687219140 ps |
| T688 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3277296488 |
|
|
Mar 10 03:08:52 PM PDT 24 |
Mar 10 03:18:16 PM PDT 24 |
5939146146 ps |
| T689 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.87570407 |
|
|
Mar 10 03:11:35 PM PDT 24 |
Mar 10 03:13:20 PM PDT 24 |
2436473009 ps |
| T690 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3473928124 |
|
|
Mar 10 03:14:35 PM PDT 24 |
Mar 10 03:51:24 PM PDT 24 |
8750244058 ps |
| T115 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.2953437141 |
|
|
Mar 10 03:05:30 PM PDT 24 |
Mar 10 03:09:48 PM PDT 24 |
2719176082 ps |
| T691 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1127994875 |
|
|
Mar 10 03:15:00 PM PDT 24 |
Mar 10 03:52:04 PM PDT 24 |
18016674887 ps |
| T692 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2163456350 |
|
|
Mar 10 03:02:24 PM PDT 24 |
Mar 10 03:08:12 PM PDT 24 |
3254263076 ps |
| T321 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.393383879 |
|
|
Mar 10 03:12:12 PM PDT 24 |
Mar 10 03:17:21 PM PDT 24 |
3138068888 ps |
| T693 |
/workspace/coverage/default/2.rom_e2e_static_critical.237490966 |
|
|
Mar 10 03:23:10 PM PDT 24 |
Mar 10 04:01:50 PM PDT 24 |
11289572752 ps |
| T694 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.3176394290 |
|
|
Mar 10 02:58:24 PM PDT 24 |
Mar 10 03:09:17 PM PDT 24 |
3876509786 ps |
| T27 |
/workspace/coverage/default/2.chip_sw_gpio.4222668042 |
|
|
Mar 10 03:12:23 PM PDT 24 |
Mar 10 03:22:53 PM PDT 24 |
4371181280 ps |
| T695 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.443629219 |
|
|
Mar 10 02:59:18 PM PDT 24 |
Mar 10 03:06:11 PM PDT 24 |
4106491581 ps |
| T696 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.2534744613 |
|
|
Mar 10 03:17:02 PM PDT 24 |
Mar 10 03:21:28 PM PDT 24 |
2487951929 ps |
| T697 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.1837319194 |
|
|
Mar 10 03:01:36 PM PDT 24 |
Mar 10 03:07:06 PM PDT 24 |
3160914883 ps |
| T698 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.708281713 |
|
|
Mar 10 03:06:38 PM PDT 24 |
Mar 10 03:16:43 PM PDT 24 |
4139591320 ps |
| T214 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.191708223 |
|
|
Mar 10 02:59:11 PM PDT 24 |
Mar 10 03:17:57 PM PDT 24 |
5902346748 ps |
| T8 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.934105160 |
|
|
Mar 10 03:14:22 PM PDT 24 |
Mar 10 03:19:56 PM PDT 24 |
3223287485 ps |
| T699 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_wakeup.3321442558 |
|
|
Mar 10 03:09:17 PM PDT 24 |
Mar 10 03:19:40 PM PDT 24 |
5893198600 ps |
| T315 |
/workspace/coverage/default/1.rom_raw_unlock.440112096 |
|
|
Mar 10 03:15:06 PM PDT 24 |
Mar 10 03:50:06 PM PDT 24 |
15297140715 ps |
| T700 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.4091198892 |
|
|
Mar 10 03:23:58 PM PDT 24 |
Mar 10 03:32:15 PM PDT 24 |
5839956966 ps |
| T701 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1786972937 |
|
|
Mar 10 03:07:18 PM PDT 24 |
Mar 10 03:16:48 PM PDT 24 |
4757101574 ps |
| T504 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.488854206 |
|
|
Mar 10 03:28:16 PM PDT 24 |
Mar 10 03:36:08 PM PDT 24 |
3447903676 ps |
| T84 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2371752359 |
|
|
Mar 10 03:29:34 PM PDT 24 |
Mar 10 03:37:44 PM PDT 24 |
4272553272 ps |
| T702 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2401329285 |
|
|
Mar 10 03:01:00 PM PDT 24 |
Mar 10 03:07:30 PM PDT 24 |
7337084054 ps |
| T703 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.392608789 |
|
|
Mar 10 03:22:07 PM PDT 24 |
Mar 10 03:31:28 PM PDT 24 |
4568957264 ps |
| T485 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.3703814618 |
|
|
Mar 10 03:34:14 PM PDT 24 |
Mar 10 03:41:37 PM PDT 24 |
3500098302 ps |
| T455 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.3909253589 |
|
|
Mar 10 03:23:35 PM PDT 24 |
Mar 10 03:34:12 PM PDT 24 |
6325991416 ps |
| T704 |
/workspace/coverage/default/0.chip_sw_example_rom.1871110840 |
|
|
Mar 10 02:57:06 PM PDT 24 |
Mar 10 02:59:03 PM PDT 24 |
1958072186 ps |
| T48 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.1676703987 |
|
|
Mar 10 03:12:27 PM PDT 24 |
Mar 10 03:16:47 PM PDT 24 |
3646624500 ps |
| T705 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.3669177873 |
|
|
Mar 10 02:56:50 PM PDT 24 |
Mar 10 03:06:54 PM PDT 24 |
5529235331 ps |
| T226 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2920925249 |
|
|
Mar 10 02:58:31 PM PDT 24 |
Mar 10 03:30:53 PM PDT 24 |
21275326099 ps |
| T706 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2733492203 |
|
|
Mar 10 03:03:19 PM PDT 24 |
Mar 10 03:11:56 PM PDT 24 |
5002048772 ps |
| T510 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3116039854 |
|
|
Mar 10 03:30:07 PM PDT 24 |
Mar 10 03:38:12 PM PDT 24 |
3918699832 ps |
| T707 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3784132959 |
|
|
Mar 10 02:59:29 PM PDT 24 |
Mar 10 03:02:58 PM PDT 24 |
2881870908 ps |
| T708 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.530881464 |
|
|
Mar 10 02:58:54 PM PDT 24 |
Mar 10 03:04:13 PM PDT 24 |
2797098136 ps |
| T431 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.3604341888 |
|
|
Mar 10 03:31:30 PM PDT 24 |
Mar 10 03:37:19 PM PDT 24 |
3252200280 ps |
| T709 |
/workspace/coverage/default/3.chip_sw_uart_rand_baudrate.258600475 |
|
|
Mar 10 03:21:46 PM PDT 24 |
Mar 10 03:37:04 PM PDT 24 |
5526810248 ps |
| T710 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3474949432 |
|
|
Mar 10 02:57:27 PM PDT 24 |
Mar 10 03:06:37 PM PDT 24 |
5623902744 ps |
| T65 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3553875100 |
|
|
Mar 10 03:17:49 PM PDT 24 |
Mar 10 03:23:45 PM PDT 24 |
3595957364 ps |
| T393 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.4264175447 |
|
|
Mar 10 03:31:18 PM PDT 24 |
Mar 10 03:40:55 PM PDT 24 |
5417830200 ps |
| T711 |
/workspace/coverage/default/0.chip_sw_example_flash.2262570886 |
|
|
Mar 10 03:00:59 PM PDT 24 |
Mar 10 03:05:51 PM PDT 24 |
2228954168 ps |
| T712 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1778194554 |
|
|
Mar 10 02:59:33 PM PDT 24 |
Mar 10 03:19:47 PM PDT 24 |
5245952319 ps |
| T85 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.224725113 |
|
|
Mar 10 03:32:31 PM PDT 24 |
Mar 10 03:39:19 PM PDT 24 |
3991409800 ps |
| T713 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.197979800 |
|
|
Mar 10 03:13:52 PM PDT 24 |
Mar 10 03:37:30 PM PDT 24 |
7282988460 ps |
| T714 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_lc.4074965029 |
|
|
Mar 10 03:07:44 PM PDT 24 |
Mar 10 03:25:07 PM PDT 24 |
10062037251 ps |
| T715 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3188023910 |
|
|
Mar 10 03:01:15 PM PDT 24 |
Mar 10 03:20:53 PM PDT 24 |
8654410112 ps |
| T716 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3815138098 |
|
|
Mar 10 03:19:03 PM PDT 24 |
Mar 10 03:27:25 PM PDT 24 |
5564079588 ps |
| T717 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.1357755679 |
|
|
Mar 10 03:02:27 PM PDT 24 |
Mar 10 03:29:51 PM PDT 24 |
9659970793 ps |
| T418 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.736570650 |
|
|
Mar 10 03:15:33 PM PDT 24 |
Mar 10 03:29:38 PM PDT 24 |
4813823184 ps |
| T718 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2746371898 |
|
|
Mar 10 03:29:05 PM PDT 24 |
Mar 10 03:40:09 PM PDT 24 |
4811061750 ps |
| T719 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.111275373 |
|
|
Mar 10 03:02:44 PM PDT 24 |
Mar 10 03:08:15 PM PDT 24 |
2814054200 ps |
| T720 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.2473676283 |
|
|
Mar 10 03:04:42 PM PDT 24 |
Mar 10 04:06:35 PM PDT 24 |
16648728392 ps |
| T721 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.2268780248 |
|
|
Mar 10 03:19:07 PM PDT 24 |
Mar 10 03:25:31 PM PDT 24 |
4121404004 ps |
| T722 |
/workspace/coverage/default/33.chip_sw_alert_handler_lpg_sleep_mode_alerts.1199419499 |
|
|
Mar 10 03:26:31 PM PDT 24 |
Mar 10 03:33:40 PM PDT 24 |
3852055596 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2545083025 |
|
|
Mar 10 02:58:04 PM PDT 24 |
Mar 10 03:02:42 PM PDT 24 |
2987875368 ps |
| T724 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.79419647 |
|
|
Mar 10 03:26:53 PM PDT 24 |
Mar 10 04:14:17 PM PDT 24 |
21683076240 ps |
| T479 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2973413514 |
|
|
Mar 10 03:24:11 PM PDT 24 |
Mar 10 03:35:50 PM PDT 24 |
4842971720 ps |
| T725 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1805032396 |
|
|
Mar 10 03:14:51 PM PDT 24 |
Mar 10 03:37:14 PM PDT 24 |
11867418047 ps |
| T726 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2531023693 |
|
|
Mar 10 03:13:20 PM PDT 24 |
Mar 10 03:23:04 PM PDT 24 |
4409239080 ps |
| T727 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.480438166 |
|
|
Mar 10 03:00:22 PM PDT 24 |
Mar 10 03:45:58 PM PDT 24 |
22698796672 ps |
| T456 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.2894193410 |
|
|
Mar 10 03:32:39 PM PDT 24 |
Mar 10 03:43:55 PM PDT 24 |
5214066744 ps |
| T728 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.2031826658 |
|
|
Mar 10 03:21:48 PM PDT 24 |
Mar 10 03:38:43 PM PDT 24 |
5708838042 ps |
| T499 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.3472355644 |
|
|
Mar 10 03:28:16 PM PDT 24 |
Mar 10 03:35:41 PM PDT 24 |
4050175400 ps |
| T729 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3061388052 |
|
|
Mar 10 02:57:49 PM PDT 24 |
Mar 10 06:30:01 PM PDT 24 |
255962405768 ps |
| T730 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2744722432 |
|
|
Mar 10 03:18:37 PM PDT 24 |
Mar 10 03:29:22 PM PDT 24 |
4363386400 ps |
| T445 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.3701956609 |
|
|
Mar 10 03:31:49 PM PDT 24 |
Mar 10 03:43:20 PM PDT 24 |
5718387204 ps |
| T388 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.4110245413 |
|
|
Mar 10 03:16:04 PM PDT 24 |
Mar 10 03:42:44 PM PDT 24 |
5984776540 ps |
| T107 |
/workspace/coverage/default/1.chip_jtag_mem_access.3396525787 |
|
|
Mar 10 03:01:01 PM PDT 24 |
Mar 10 03:26:32 PM PDT 24 |
13394321061 ps |
| T429 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.2859296886 |
|
|
Mar 10 03:27:06 PM PDT 24 |
Mar 10 03:37:01 PM PDT 24 |
5079958000 ps |
| T731 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3462124030 |
|
|
Mar 10 03:01:22 PM PDT 24 |
Mar 10 03:03:23 PM PDT 24 |
3137235822 ps |
| T732 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.3010346575 |
|
|
Mar 10 03:04:52 PM PDT 24 |
Mar 10 03:09:04 PM PDT 24 |
3151990476 ps |
| T733 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.1911493033 |
|
|
Mar 10 03:05:29 PM PDT 24 |
Mar 10 03:51:25 PM PDT 24 |
10459181505 ps |
| T734 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.551476780 |
|
|
Mar 10 03:17:11 PM PDT 24 |
Mar 10 03:26:22 PM PDT 24 |
4112331209 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1613248618 |
|
|
Mar 10 02:59:53 PM PDT 24 |
Mar 10 03:05:13 PM PDT 24 |
3235685349 ps |
| T379 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.911535689 |
|
|
Mar 10 03:09:03 PM PDT 24 |
Mar 10 03:11:03 PM PDT 24 |
2341162340 ps |
| T209 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.364914933 |
|
|
Mar 10 03:16:24 PM PDT 24 |
Mar 10 03:26:41 PM PDT 24 |
3344992100 ps |
| T735 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.766580238 |
|
|
Mar 10 03:17:57 PM PDT 24 |
Mar 10 03:27:05 PM PDT 24 |
5353424770 ps |
| T736 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3377763354 |
|
|
Mar 10 03:21:23 PM PDT 24 |
Mar 10 03:27:06 PM PDT 24 |
3095200696 ps |
| T162 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2216411742 |
|
|
Mar 10 03:20:01 PM PDT 24 |
Mar 10 04:14:50 PM PDT 24 |
20143404632 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.3616061144 |
|
|
Mar 10 02:58:43 PM PDT 24 |
Mar 10 03:02:03 PM PDT 24 |
3363813196 ps |
| T737 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.332319890 |
|
|
Mar 10 03:16:00 PM PDT 24 |
Mar 10 03:32:16 PM PDT 24 |
7144538262 ps |
| T338 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1759458600 |
|
|
Mar 10 03:02:03 PM PDT 24 |
Mar 10 03:11:05 PM PDT 24 |
4832016173 ps |
| T738 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1811613678 |
|
|
Mar 10 02:59:52 PM PDT 24 |
Mar 10 03:08:31 PM PDT 24 |
4746536288 ps |
| T739 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3028728727 |
|
|
Mar 10 03:01:49 PM PDT 24 |
Mar 10 03:08:30 PM PDT 24 |
5781570436 ps |
| T740 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.2606036582 |
|
|
Mar 10 03:11:32 PM PDT 24 |
Mar 10 03:14:25 PM PDT 24 |
2011243894 ps |
| T46 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.1818764793 |
|
|
Mar 10 02:57:11 PM PDT 24 |
Mar 10 03:04:56 PM PDT 24 |
5544621720 ps |
| T741 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.2112209333 |
|
|
Mar 10 03:24:42 PM PDT 24 |
Mar 10 03:55:15 PM PDT 24 |
8613005480 ps |
| T469 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1742859050 |
|
|
Mar 10 03:30:55 PM PDT 24 |
Mar 10 03:43:25 PM PDT 24 |
4592968600 ps |
| T387 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2244092597 |
|
|
Mar 10 03:01:23 PM PDT 24 |
Mar 10 04:00:49 PM PDT 24 |
25022799131 ps |
| T742 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.522825665 |
|
|
Mar 10 03:16:48 PM PDT 24 |
Mar 10 03:32:12 PM PDT 24 |
6208775086 ps |
| T488 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.917132920 |
|
|
Mar 10 03:25:12 PM PDT 24 |
Mar 10 03:37:41 PM PDT 24 |
4676691434 ps |
| T354 |
/workspace/coverage/default/0.chip_sw_hmac_enc.82812257 |
|
|
Mar 10 03:00:30 PM PDT 24 |
Mar 10 03:04:03 PM PDT 24 |
2526084620 ps |
| T743 |
/workspace/coverage/default/0.rom_keymgr_functest.523044471 |
|
|
Mar 10 02:59:55 PM PDT 24 |
Mar 10 03:11:16 PM PDT 24 |
3752999656 ps |
| T371 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.101222508 |
|
|
Mar 10 03:28:07 PM PDT 24 |
Mar 10 03:40:33 PM PDT 24 |
5384222416 ps |
| T744 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.942660818 |
|
|
Mar 10 03:07:49 PM PDT 24 |
Mar 10 03:17:16 PM PDT 24 |
4679553152 ps |
| T745 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.3305166933 |
|
|
Mar 10 03:00:16 PM PDT 24 |
Mar 10 03:18:33 PM PDT 24 |
5746667764 ps |
| T746 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.1806464170 |
|
|
Mar 10 02:59:26 PM PDT 24 |
Mar 10 03:06:10 PM PDT 24 |
3970556856 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.778049783 |
|
|
Mar 10 02:57:35 PM PDT 24 |
Mar 10 03:24:07 PM PDT 24 |
10457956766 ps |
| T474 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.89328678 |
|
|
Mar 10 03:34:21 PM PDT 24 |
Mar 10 03:43:25 PM PDT 24 |
5907297136 ps |
| T747 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3171799042 |
|
|
Mar 10 03:02:19 PM PDT 24 |
Mar 10 03:18:15 PM PDT 24 |
5224755802 ps |
| T748 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3808422620 |
|
|
Mar 10 03:07:24 PM PDT 24 |
Mar 10 03:13:50 PM PDT 24 |
3546901080 ps |
| T172 |
/workspace/coverage/default/4.chip_sw_sensor_ctrl_alert.4165742308 |
|
|
Mar 10 03:23:07 PM PDT 24 |
Mar 10 03:34:29 PM PDT 24 |
8450812620 ps |
| T86 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1763771569 |
|
|
Mar 10 03:30:06 PM PDT 24 |
Mar 10 03:38:43 PM PDT 24 |
3592068482 ps |
| T749 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.1198043177 |
|
|
Mar 10 03:12:31 PM PDT 24 |
Mar 10 03:18:40 PM PDT 24 |
2571123478 ps |
| T215 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.315200540 |
|
|
Mar 10 03:16:41 PM PDT 24 |
Mar 10 03:37:48 PM PDT 24 |
5509489822 ps |
| T750 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.337636565 |
|
|
Mar 10 02:57:52 PM PDT 24 |
Mar 10 03:08:34 PM PDT 24 |
7645595892 ps |
| T24 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.4080635937 |
|
|
Mar 10 02:57:24 PM PDT 24 |
Mar 10 03:46:25 PM PDT 24 |
11776574576 ps |
| T231 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1799030083 |
|
|
Mar 10 02:58:02 PM PDT 24 |
Mar 10 04:27:14 PM PDT 24 |
48233953489 ps |
| T751 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3113220976 |
|
|
Mar 10 03:21:47 PM PDT 24 |
Mar 10 03:30:47 PM PDT 24 |
6010328898 ps |
| T752 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.2992736785 |
|
|
Mar 10 02:58:55 PM PDT 24 |
Mar 10 03:14:12 PM PDT 24 |
5904793000 ps |
| T413 |
/workspace/coverage/default/3.chip_tap_straps_dev.1978792092 |
|
|
Mar 10 03:21:01 PM PDT 24 |
Mar 10 03:46:25 PM PDT 24 |
13724845083 ps |
| T66 |
/workspace/coverage/default/1.chip_tap_straps_rma.2116158101 |
|
|
Mar 10 03:08:00 PM PDT 24 |
Mar 10 03:17:12 PM PDT 24 |
5886794967 ps |
| T487 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2109867041 |
|
|
Mar 10 03:30:11 PM PDT 24 |
Mar 10 03:37:12 PM PDT 24 |
4479607864 ps |
| T753 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_req.1633948592 |
|
|
Mar 10 03:14:29 PM PDT 24 |
Mar 10 03:21:19 PM PDT 24 |
3718310880 ps |
| T754 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.3727586782 |
|
|
Mar 10 03:16:37 PM PDT 24 |
Mar 10 03:25:42 PM PDT 24 |
3749033950 ps |
| T53 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2055691870 |
|
|
Mar 10 03:11:12 PM PDT 24 |
Mar 10 03:48:37 PM PDT 24 |
18270349340 ps |
| T755 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.2747646684 |
|
|
Mar 10 02:57:09 PM PDT 24 |
Mar 10 03:13:29 PM PDT 24 |
5914783674 ps |
| T756 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.307737080 |
|
|
Mar 10 02:59:57 PM PDT 24 |
Mar 10 03:02:23 PM PDT 24 |
2046886826 ps |
| T399 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.4026348525 |
|
|
Mar 10 02:58:22 PM PDT 24 |
Mar 10 03:28:30 PM PDT 24 |
7814102760 ps |
| T156 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.533605333 |
|
|
Mar 10 03:01:25 PM PDT 24 |
Mar 10 03:11:33 PM PDT 24 |
9672609168 ps |
| T471 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.2871388625 |
|
|
Mar 10 03:27:54 PM PDT 24 |
Mar 10 03:35:39 PM PDT 24 |
3684690858 ps |
| T296 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_aes.757202510 |
|
|
Mar 10 03:16:16 PM PDT 24 |
Mar 10 03:26:42 PM PDT 24 |
4520847504 ps |
| T757 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.1843943196 |
|
|
Mar 10 02:59:07 PM PDT 24 |
Mar 10 05:58:03 PM PDT 24 |
58993012777 ps |
| T435 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.398851260 |
|
|
Mar 10 03:23:14 PM PDT 24 |
Mar 10 03:31:20 PM PDT 24 |
4042345928 ps |
| T87 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.3218318982 |
|
|
Mar 10 03:24:40 PM PDT 24 |
Mar 10 03:37:57 PM PDT 24 |
4851904812 ps |
| T758 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.80303613 |
|
|
Mar 10 03:04:21 PM PDT 24 |
Mar 10 03:38:38 PM PDT 24 |
8468547408 ps |
| T500 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.380058065 |
|
|
Mar 10 03:26:07 PM PDT 24 |
Mar 10 03:34:10 PM PDT 24 |
3243853340 ps |
| T759 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.715527722 |
|
|
Mar 10 02:59:18 PM PDT 24 |
Mar 10 03:01:51 PM PDT 24 |
3550846500 ps |
| T760 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3984151348 |
|
|
Mar 10 03:17:40 PM PDT 24 |
Mar 10 03:24:15 PM PDT 24 |
3533435564 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2134911629 |
|
|
Mar 10 03:09:49 PM PDT 24 |
Mar 10 03:15:08 PM PDT 24 |
2810863349 ps |
| T762 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.708140080 |
|
|
Mar 10 03:03:43 PM PDT 24 |
Mar 10 03:08:21 PM PDT 24 |
2539014748 ps |
| T763 |
/workspace/coverage/default/2.chip_sw_plic_sw_irq.3822884453 |
|
|
Mar 10 03:22:04 PM PDT 24 |
Mar 10 03:26:17 PM PDT 24 |
2740105176 ps |
| T764 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.2095682153 |
|
|
Mar 10 02:57:35 PM PDT 24 |
Mar 10 03:06:27 PM PDT 24 |
4273137478 ps |
| T501 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.276695022 |
|
|
Mar 10 03:26:44 PM PDT 24 |
Mar 10 03:38:56 PM PDT 24 |
5797329432 ps |
| T210 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2539783300 |
|
|
Mar 10 03:03:48 PM PDT 24 |
Mar 10 03:14:45 PM PDT 24 |
3431767994 ps |
| T181 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1283969061 |
|
|
Mar 10 03:21:32 PM PDT 24 |
Mar 10 03:31:25 PM PDT 24 |
3520507552 ps |
| T157 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.2931230404 |
|
|
Mar 10 03:20:32 PM PDT 24 |
Mar 10 03:29:47 PM PDT 24 |
9782185206 ps |
| T765 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.3309556495 |
|
|
Mar 10 03:26:21 PM PDT 24 |
Mar 10 03:35:47 PM PDT 24 |
4245737768 ps |
| T514 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2720426874 |
|
|
Mar 10 03:28:49 PM PDT 24 |
Mar 10 03:34:28 PM PDT 24 |
3227340108 ps |
| T766 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.566667716 |
|
|
Mar 10 03:00:06 PM PDT 24 |
Mar 10 03:09:06 PM PDT 24 |
2749697110 ps |
| T767 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.629952800 |
|
|
Mar 10 03:17:25 PM PDT 24 |
Mar 10 03:24:49 PM PDT 24 |
4556582584 ps |
| T502 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.941185669 |
|
|
Mar 10 03:25:44 PM PDT 24 |
Mar 10 03:32:59 PM PDT 24 |
3770137552 ps |
| T768 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3313316475 |
|
|
Mar 10 03:25:06 PM PDT 24 |
Mar 10 03:33:50 PM PDT 24 |
5129501750 ps |
| T769 |
/workspace/coverage/default/2.chip_sw_aes_entropy.47027368 |
|
|
Mar 10 03:15:55 PM PDT 24 |
Mar 10 03:21:58 PM PDT 24 |
2708237520 ps |
| T770 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.1302083760 |
|
|
Mar 10 03:15:03 PM PDT 24 |
Mar 10 03:51:12 PM PDT 24 |
9210737004 ps |
| T771 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.3231363099 |
|
|
Mar 10 03:06:31 PM PDT 24 |
Mar 10 03:15:52 PM PDT 24 |
4431451285 ps |
| T58 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.1478549478 |
|
|
Mar 10 03:11:35 PM PDT 24 |
Mar 10 03:21:08 PM PDT 24 |
5794647192 ps |
| T772 |
/workspace/coverage/default/0.chip_sw_example_concurrency.4206120932 |
|
|
Mar 10 03:01:13 PM PDT 24 |
Mar 10 03:06:12 PM PDT 24 |
2659773472 ps |
| T773 |
/workspace/coverage/default/3.chip_tap_straps_prod.3824254127 |
|
|
Mar 10 03:21:17 PM PDT 24 |
Mar 10 03:43:04 PM PDT 24 |
11580318095 ps |
| T179 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3061301060 |
|
|
Mar 10 03:00:05 PM PDT 24 |
Mar 10 03:11:33 PM PDT 24 |
7192845976 ps |
| T307 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.1425863359 |
|
|
Mar 10 03:16:00 PM PDT 24 |
Mar 10 03:21:59 PM PDT 24 |
3069953294 ps |
| T458 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.3527799566 |
|
|
Mar 10 03:27:07 PM PDT 24 |
Mar 10 03:37:34 PM PDT 24 |
4939706480 ps |
| T774 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.2534391482 |
|
|
Mar 10 03:15:50 PM PDT 24 |
Mar 10 03:23:10 PM PDT 24 |
3894306420 ps |
| T775 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.200083627 |
|
|
Mar 10 03:05:19 PM PDT 24 |
Mar 10 03:48:25 PM PDT 24 |
8822884322 ps |
| T776 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.1928864323 |
|
|
Mar 10 03:21:42 PM PDT 24 |
Mar 10 03:27:44 PM PDT 24 |
4440172045 ps |
| T466 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980712734 |
|
|
Mar 10 03:27:58 PM PDT 24 |
Mar 10 03:35:56 PM PDT 24 |
4145010466 ps |
| T777 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1649476855 |
|
|
Mar 10 03:15:25 PM PDT 24 |
Mar 10 04:09:58 PM PDT 24 |
18617747433 ps |
| T778 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3914782340 |
|
|
Mar 10 03:13:52 PM PDT 24 |
Mar 10 03:45:01 PM PDT 24 |
24863961345 ps |
| T779 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.4207981428 |
|
|
Mar 10 02:57:16 PM PDT 24 |
Mar 10 03:02:28 PM PDT 24 |
3500702528 ps |
| T780 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1887033274 |
|
|
Mar 10 03:30:37 PM PDT 24 |
Mar 10 03:37:11 PM PDT 24 |
3352948240 ps |
| T505 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.480557458 |
|
|
Mar 10 03:00:17 PM PDT 24 |
Mar 10 03:11:52 PM PDT 24 |
4740733120 ps |
| T480 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.618074148 |
|
|
Mar 10 03:31:42 PM PDT 24 |
Mar 10 03:40:24 PM PDT 24 |
5945499000 ps |
| T781 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.2439011200 |
|
|
Mar 10 03:05:09 PM PDT 24 |
Mar 10 03:18:28 PM PDT 24 |
4142478739 ps |
| T782 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.267121226 |
|
|
Mar 10 03:01:27 PM PDT 24 |
Mar 10 03:18:27 PM PDT 24 |
5718576324 ps |
| T783 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2877462952 |
|
|
Mar 10 03:21:31 PM PDT 24 |
Mar 10 03:35:31 PM PDT 24 |
5796238300 ps |
| T784 |
/workspace/coverage/default/0.chip_sw_aes_enc.2519045857 |
|
|
Mar 10 02:58:03 PM PDT 24 |
Mar 10 03:03:17 PM PDT 24 |
3224277896 ps |
| T785 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.2536087586 |
|
|
Mar 10 02:57:12 PM PDT 24 |
Mar 10 03:02:59 PM PDT 24 |
3232798520 ps |
| T786 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.2867567304 |
|
|
Mar 10 02:59:04 PM PDT 24 |
Mar 10 03:19:10 PM PDT 24 |
5595458900 ps |
| T451 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.2803934327 |
|
|
Mar 10 03:27:11 PM PDT 24 |
Mar 10 03:41:46 PM PDT 24 |
6035403108 ps |
| T787 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.1205432069 |
|
|
Mar 10 02:57:43 PM PDT 24 |
Mar 10 03:24:28 PM PDT 24 |
6429172000 ps |
| T364 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sensor_ctrl_deep_sleep_wake_up.1890585111 |
|
|
Mar 10 03:08:47 PM PDT 24 |
Mar 10 03:14:19 PM PDT 24 |
6042336870 ps |
| T788 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.2751044596 |
|
|
Mar 10 02:59:08 PM PDT 24 |
Mar 10 03:17:49 PM PDT 24 |
11024830925 ps |
| T789 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.4120194758 |
|
|
Mar 10 03:24:44 PM PDT 24 |
Mar 10 03:32:00 PM PDT 24 |
3528394156 ps |
| T472 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2031800613 |
|
|
Mar 10 03:29:18 PM PDT 24 |
Mar 10 03:36:13 PM PDT 24 |
4094223948 ps |
| T158 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1568266805 |
|
|
Mar 10 02:58:31 PM PDT 24 |
Mar 10 03:10:25 PM PDT 24 |
18841903400 ps |
| T790 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.1461614351 |
|
|
Mar 10 02:59:48 PM PDT 24 |
Mar 10 03:23:03 PM PDT 24 |
12018144328 ps |
| T791 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.4050014195 |
|
|
Mar 10 02:59:13 PM PDT 24 |
Mar 10 03:08:47 PM PDT 24 |
4697379281 ps |
| T792 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.653698534 |
|
|
Mar 10 03:06:10 PM PDT 24 |
Mar 10 04:01:24 PM PDT 24 |
11829005896 ps |
| T793 |
/workspace/coverage/default/2.chip_sival_flash_info_access.1237235223 |
|
|
Mar 10 03:14:11 PM PDT 24 |
Mar 10 03:19:01 PM PDT 24 |
2808345012 ps |
| T794 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.1665621737 |
|
|
Mar 10 02:58:27 PM PDT 24 |
Mar 10 03:07:59 PM PDT 24 |
4621378860 ps |
| T482 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.87992173 |
|
|
Mar 10 03:16:14 PM PDT 24 |
Mar 10 03:22:44 PM PDT 24 |
3755323610 ps |
| T297 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.3146373928 |
|
|
Mar 10 03:03:50 PM PDT 24 |
Mar 10 03:12:45 PM PDT 24 |
4846917128 ps |
| T795 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.2727628392 |
|
|
Mar 10 03:27:32 PM PDT 24 |
Mar 10 03:42:37 PM PDT 24 |
5411279240 ps |
| T796 |
/workspace/coverage/default/0.chip_sw_power_idle_load.3293148782 |
|
|
Mar 10 03:00:01 PM PDT 24 |
Mar 10 03:13:27 PM PDT 24 |
4555202848 ps |
| T797 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.3816326576 |
|
|
Mar 10 02:59:14 PM PDT 24 |
Mar 10 03:19:52 PM PDT 24 |
7176034992 ps |
| T798 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3893952237 |
|
|
Mar 10 02:58:55 PM PDT 24 |
Mar 10 03:21:37 PM PDT 24 |
8929106112 ps |
| T799 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.208240614 |
|
|
Mar 10 03:24:10 PM PDT 24 |
Mar 10 03:34:48 PM PDT 24 |
4885504504 ps |
| T800 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.503987129 |
|
|
Mar 10 03:00:04 PM PDT 24 |
Mar 10 03:13:18 PM PDT 24 |
6045503900 ps |
| T801 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.2069350426 |
|
|
Mar 10 03:14:07 PM PDT 24 |
Mar 10 03:34:07 PM PDT 24 |
5873645220 ps |
| T802 |
/workspace/coverage/default/0.rom_e2e_smoke.930025103 |
|
|
Mar 10 02:59:17 PM PDT 24 |
Mar 10 03:31:04 PM PDT 24 |
8982581880 ps |
| T803 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3259964177 |
|
|
Mar 10 03:18:26 PM PDT 24 |
Mar 10 03:27:49 PM PDT 24 |
5214922440 ps |
| T120 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2822991042 |
|
|
Mar 10 03:12:51 PM PDT 24 |
Mar 10 03:22:31 PM PDT 24 |
4252841019 ps |
| T467 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.650049634 |
|
|
Mar 10 03:30:08 PM PDT 24 |
Mar 10 03:39:43 PM PDT 24 |
5968843480 ps |
| T804 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2710780557 |
|
|
Mar 10 03:02:32 PM PDT 24 |
Mar 10 03:20:00 PM PDT 24 |
5966603067 ps |
| T805 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.407864083 |
|
|
Mar 10 03:13:53 PM PDT 24 |
Mar 10 03:48:18 PM PDT 24 |
8805201564 ps |
| T806 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.3175411134 |
|
|
Mar 10 03:23:28 PM PDT 24 |
Mar 10 03:42:31 PM PDT 24 |
11586617443 ps |
| T807 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.107190196 |
|
|
Mar 10 03:15:35 PM PDT 24 |
Mar 10 03:24:03 PM PDT 24 |
3686478728 ps |
| T171 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.168037246 |
|
|
Mar 10 03:07:01 PM PDT 24 |
Mar 10 03:21:52 PM PDT 24 |
5837377698 ps |
| T808 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.3635520689 |
|
|
Mar 10 03:15:54 PM PDT 24 |
Mar 10 03:23:01 PM PDT 24 |
4072492826 ps |
| T473 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.4024211230 |
|
|
Mar 10 03:30:04 PM PDT 24 |
Mar 10 03:43:51 PM PDT 24 |
5234602264 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.463400551 |
|
|
Mar 10 02:59:10 PM PDT 24 |
Mar 10 03:52:21 PM PDT 24 |
18464286337 ps |
| T809 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.1836795031 |
|
|
Mar 10 03:01:56 PM PDT 24 |
Mar 10 03:24:48 PM PDT 24 |
9215455600 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1466366084 |
|
|
Mar 10 03:03:16 PM PDT 24 |
Mar 10 03:13:03 PM PDT 24 |
19184624200 ps |
| T810 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_por_reset.3439927814 |
|
|
Mar 10 03:00:45 PM PDT 24 |
Mar 10 03:09:00 PM PDT 24 |
6438065552 ps |
| T811 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2858640122 |
|
|
Mar 10 03:10:58 PM PDT 24 |
Mar 10 03:13:46 PM PDT 24 |
2510397386 ps |
| T812 |
/workspace/coverage/default/2.chip_sw_aes_enc.2073743497 |
|
|
Mar 10 03:18:33 PM PDT 24 |
Mar 10 03:22:17 PM PDT 24 |
2637538120 ps |
| T813 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.937275410 |
|
|
Mar 10 03:04:36 PM PDT 24 |
Mar 10 03:24:52 PM PDT 24 |
5676980248 ps |
| T207 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2892214859 |
|
|
Mar 10 03:18:42 PM PDT 24 |
Mar 10 03:30:05 PM PDT 24 |
4568294226 ps |
| T814 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.2975800220 |
|
|
Mar 10 03:02:44 PM PDT 24 |
Mar 10 03:10:59 PM PDT 24 |
9109501800 ps |
| T815 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.968295040 |
|
|
Mar 10 03:03:42 PM PDT 24 |
Mar 10 03:40:25 PM PDT 24 |
8785530040 ps |
| T816 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.2779573059 |
|
|
Mar 10 03:03:04 PM PDT 24 |
Mar 10 03:23:13 PM PDT 24 |
10238243320 ps |
| T227 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.975953674 |
|
|
Mar 10 03:13:06 PM PDT 24 |
Mar 10 03:21:11 PM PDT 24 |
5229225316 ps |