Unified Coverage Report :: Module :: prim_fifo_sync

Module : prim_fifo_sync

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo	75.00	50.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo	100.00	100.00					100.00
tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo	100.00	100.00					100.00

Line Coverage for Module : prim_fifo_sync

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Module : prim_fifo_sync

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	2147483647	143807440	0	0
DepthKnown_A	2147483647	2147483647	0	0
RvalidKnown_A	2147483647	2147483647	0	0
WreadyKnown_A	2147483647	2147483647	0	0
gen_passthru_fifo.paramCheckPass	20896	20896	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	143807440	0	0
T1	2038050	73203	0	0
T2	1365590	47212	0	0
T3	1542520	54968	0	0
T4	6363640	316708	0	0
T5	1750610	37829	0	0
T6	0	275580	0	0
T32	1869790	62948	0	0
T49	1424930	149632	0	0
T53	380980	0	0	0
T79	1117510	35814	0	0
T80	723370	23243	0	0
T126	0	84	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2038050	2036890	0	0
T2	1365590	1365010	0	0
T3	1542520	1541900	0	0
T4	6363640	6363130	0	0
T5	1750610	1748960	0	0
T32	1869790	1868660	0	0
T49	1424930	1424870	0	0
T53	380980	380470	0	0
T79	1117510	1116930	0	0
T80	723370	722820	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2038050	2036890	0	0
T2	1365590	1365010	0	0
T3	1542520	1541900	0	0
T4	6363640	6363130	0	0
T5	1750610	1748960	0	0
T32	1869790	1868660	0	0
T49	1424930	1424870	0	0
T53	380980	380470	0	0
T79	1117510	1116930	0	0
T80	723370	722820	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	2038050	2036890	0	0
T2	1365590	1365010	0	0
T3	1542520	1541900	0	0
T4	6363640	6363130	0	0
T5	1750610	1748960	0	0
T32	1869790	1868660	0	0
T49	1424930	1424870	0	0
T53	380980	380470	0	0
T79	1117510	1116930	0	0
T80	723370	722820	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	20896	20896	0	0
T1	10	10	0	0
T2	10	10	0	0
T3	10	10	0	0
T4	10	10	0	0
T5	10	10	0	0
T32	10	10	0	0
T49	10	10	0	0
T53	10	10	0	0
T79	10	10	0	0
T80	10	10	0	0