Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431411107	46370302	0	0
DepthKnown_A	431411107	431310102	0	0
RvalidKnown_A	431411107	431310102	0	0
WreadyKnown_A	431411107	431310102	0	0
gen_passthru_fifo.paramCheckPass	955	955	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	46370302	0	0
T1	203805	24185	0	0
T2	136559	18928	0	0
T3	154252	21175	0	0
T4	636364	78905	0	0
T5	175061	13319	0	0
T6	0	166744	0	0
T32	186979	20523	0	0
T49	142493	43818	0	0
T53	38098	0	0	0
T79	111751	12284	0	0
T80	72337	8198	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431411107	35734608	0	0
DepthKnown_A	431411107	431310102	0	0
RvalidKnown_A	431411107	431310102	0	0
WreadyKnown_A	431411107	431310102	0	0
gen_passthru_fifo.paramCheckPass	955	955	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	35734608	0	0
T1	203805	18210	0	0
T2	136559	13487	0	0
T3	154252	15732	0	0
T4	636364	62387	0	0
T5	175061	9485	0	0
T6	0	83579	0	0
T32	186979	16797	0	0
T49	142493	39684	0	0
T53	38098	0	0	0
T79	111751	10205	0	0
T80	72337	5902	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431411107	33388041	0	0
DepthKnown_A	431411107	431310102	0	0
RvalidKnown_A	431411107	431310102	0	0
WreadyKnown_A	431411107	431310102	0	0
gen_passthru_fifo.paramCheckPass	955	955	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	33388041	0	0
T1	203805	15231	0	0
T2	136559	7486	0	0
T3	154252	9118	0	0
T4	636364	120522	0	0
T5	175061	7571	0	0
T6	0	12971	0	0
T32	186979	12879	0	0
T49	142493	33093	0	0
T53	38098	0	0	0
T79	111751	6703	0	0
T80	72337	4607	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	431411107	27943501	0	0
DepthKnown_A	431411107	431310102	0	0
RvalidKnown_A	431411107	431310102	0	0
WreadyKnown_A	431411107	431310102	0	0
gen_passthru_fifo.paramCheckPass	955	955	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	27943501	0	0
T1	203805	14745	0	0
T2	136559	7207	0	0
T3	154252	8839	0	0
T4	636364	54818	0	0
T5	175061	7318	0	0
T6	0	11994	0	0
T32	186979	12641	0	0
T49	142493	32921	0	0
T53	38098	0	0	0
T79	111751	6570	0	0
T80	72337	4484	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	431411107	431310102	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	955	955	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510362076	92228	0	0
DepthKnown_A	510362076	510249274	0	0
RvalidKnown_A	510362076	510249274	0	0
WreadyKnown_A	510362076	510249274	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	92228	0	0
T1	203805	208	0	0
T2	136559	26	0	0
T3	154252	26	0	0
T4	636364	19	0	0
T5	175061	34	0	0
T6	0	73	0	0
T32	186979	27	0	0
T49	142493	29	0	0
T53	38098	0	0	0
T79	111751	13	0	0
T80	72337	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510362076	93266	0	0
DepthKnown_A	510362076	510249274	0	0
RvalidKnown_A	510362076	510249274	0	0
WreadyKnown_A	510362076	510249274	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	93266	0	0
T1	203805	208	0	0
T2	136559	26	0	0
T3	154252	26	0	0
T4	636364	19	0	0
T5	175061	34	0	0
T6	0	73	0	0
T32	186979	27	0	0
T49	142493	29	0	0
T53	38098	0	0	0
T79	111751	13	0	0
T80	72337	13	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510362076	50043	0	0
DepthKnown_A	510362076	510249274	0	0
RvalidKnown_A	510362076	510249274	0	0
WreadyKnown_A	510362076	510249274	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	50043	0	0
T1	203805	202	0	0
T2	136559	23	0	0
T3	154252	23	0	0
T4	636364	0	0	0
T5	175061	32	0	0
T6	0	69	0	0
T32	186979	25	0	0
T49	142493	28	0	0
T53	38098	0	0	0
T79	111751	12	0	0
T80	72337	12	0	0
T126	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510362076	50043	0	0
DepthKnown_A	510362076	510249274	0	0
RvalidKnown_A	510362076	510249274	0	0
WreadyKnown_A	510362076	510249274	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	50043	0	0
T1	203805	202	0	0
T2	136559	23	0	0
T3	154252	23	0	0
T4	636364	0	0	0
T5	175061	32	0	0
T6	0	69	0	0
T32	186979	25	0	0
T49	142493	28	0	0
T53	38098	0	0	0
T79	111751	12	0	0
T80	72337	12	0	0
T126	0	42	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510362076	42185	0	0
DepthKnown_A	510362076	510249274	0	0
RvalidKnown_A	510362076	510249274	0	0
WreadyKnown_A	510362076	510249274	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	42185	0	0
T1	203805	6	0	0
T2	136559	3	0	0
T3	154252	3	0	0
T4	636364	19	0	0
T5	175061	2	0	0
T6	0	4	0	0
T32	186979	2	0	0
T49	142493	1	0	0
T53	38098	0	0	0
T79	111751	1	0	0
T80	72337	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	510362076	43223	0	0
DepthKnown_A	510362076	510249274	0	0
RvalidKnown_A	510362076	510249274	0	0
WreadyKnown_A	510362076	510249274	0	0
gen_passthru_fifo.paramCheckPass	2846	2846	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	43223	0	0
T1	203805	6	0	0
T2	136559	3	0	0
T3	154252	3	0	0
T4	636364	19	0	0
T5	175061	2	0	0
T6	0	4	0	0
T32	186979	2	0	0
T49	142493	1	0	0
T53	38098	0	0	0
T79	111751	1	0	0
T80	72337	1	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	510362076	510249274	0	0
T1	203805	203689	0	0
T2	136559	136501	0	0
T3	154252	154190	0	0
T4	636364	636313	0	0
T5	175061	174896	0	0
T32	186979	186866	0	0
T49	142493	142487	0	0
T53	38098	38047	0	0
T79	111751	111693	0	0
T80	72337	72282	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2846	2846	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T5	1	1	0	0
T32	1	1	0	0
T49	1	1	0	0
T53	1	1	0	0
T79	1	1	0	0
T80	1	1	0	0