Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=32}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
95.12	95.12	1	100	1	1	64	64

Source File(s) :
/workspace/pad_ctrl_test_mode/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg	95.12	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
95.12	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	38	1	37	97.37
Crosses	3	1	2	66.67

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	1	2	66.67	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	33	0	33	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_chip_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	1	2	66.67	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	14253	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

16011

1

T1

1486

T2

1432

T3

2007

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	1	2	66.67

User Defined Bins for cp_opcode

Uncovered bins

NAME	COUNT	AT LEAST	NUMBER	STATUS
values[0x4]	0	1	1

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

15231

1

T1

1370

T2

1324

T3

1955

values[0x1]

15033

1

T1

1310

T2

1368

T3

1925

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	9237	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

21027

1

T1

1944

T2

1909

T3

2634

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	33	0	33	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	1955	1			T1	91		T2	79		T3	53
valid_sources[0x01]	384	1			T1	30		T2	56		T3	63
valid_sources[0x02]	272	1			T1	37		T2	43		T3	65
valid_sources[0x03]	310	1			T2	42		T3	64		T5	42
valid_sources[0x04]	453	1			T1	23		T2	66		T3	58
valid_sources[0x05]	434	1			T1	56		T2	37		T3	74
valid_sources[0x06]	345	1			T1	57		T2	16		T3	72
valid_sources[0x07]	3710	1			T1	48		T2	92		T3	61
valid_sources[0x08]	341	1			T1	11		T2	62		T3	57
valid_sources[0x09]	285	1			T1	16		T2	30		T3	66
valid_sources[0x0a]	330	1			T1	43		T2	45		T3	66
valid_sources[0x0b]	456	1			T1	51		T2	35		T3	72
valid_sources[0x0c]	302	1			T1	22		T2	47		T3	72
valid_sources[0x0d]	390	1			T1	32		T2	61		T3	55
valid_sources[0x0e]	234	1			T1	29		T2	37		T3	61
valid_sources[0x0f]	261	1			T1	5		T2	34		T3	62
valid_sources[0x10]	324	1			T1	50		T2	23		T3	54
valid_sources[0x11]	309	1			T1	49		T2	58		T3	64
valid_sources[0x12]	336	1			T1	48		T2	46		T3	45
valid_sources[0x13]	296	1			T1	41		T2	50		T3	43
valid_sources[0x14]	263	1			T1	7		T2	16		T3	64
valid_sources[0x15]	306	1			T1	46		T2	32		T3	62
valid_sources[0x16]	383	1			T1	43		T2	28		T3	52
valid_sources[0x17]	395	1			T1	18		T2	47		T3	52
valid_sources[0x18]	311	1			T1	28		T2	38		T3	52
valid_sources[0x19]	440	1			T1	23		T2	49		T3	38
valid_sources[0x1a]	288	1			T1	88		T2	28		T3	37
valid_sources[0x1b]	305	1			T1	64		T2	49		T3	46
valid_sources[0x1c]	261	1			T1	20		T2	2		T3	87
valid_sources[0x1d]	315	1			T1	36		T2	54		T3	57
valid_sources[0x1e]	335	1			T1	62		T2	14		T3	59
valid_sources[0x1f]	335	1			T1	101		T2	11		T3	64
valid_sources[0x20]	347	1			T1	47		T2	72		T3	67

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	1	2	66.67	1

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Element holes

cp_opcode	cp_mask	cp_size	COUNT	AT LEAST	NUMBER	STATUS
[values[0x4]]	*	*	0	1	1

Covered bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x0]

all_enables

biggest_size

10540

1

T1

982

T2

937

T3

1327

values[0x1]

all_enables

biggest_size

5471

1

T1

504

T2

495

T3

680