Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
69.58	90.61	48.46	90.82		34.02	84.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
61.85	68.56	47.71	90.11		60.75	42.11

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.19	51.61		73.96			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
gen_alert_tx[0].u_prim_alert_sender	33.33			33.33
gen_wkup_detect[0].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[1].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[2].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[3].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[4].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[5].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[6].u_pinmux_wkup	45.45	50.00	31.82			54.55
gen_wkup_detect[7].u_pinmux_wkup	45.45	50.00	31.82			54.55
u_pinmux_strap_sampling	64.89	59.43	48.91			62.34	88.89
u_reg	51.91	67.81	47.65			65.08	27.10
u_usbdev_aon_wake	86.71	84.78	79.03			83.02	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Line No.	Total	Covered	Percent
TOTAL		895	811	90.61
CONT_ASSIGN	132	1	1	100.00
ALWAYS	161	41	41	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	242	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	0	0.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	243	1	1	100.00
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	244	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	245	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	246	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	247	0	0
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	248	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	249	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	250	1	0	0.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	250	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	251	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	264	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	265	1	1	100.00
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	266	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	267	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	268	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	269	0	0
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	270	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	271	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	272	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	273	1	1	100.00
CONT_ASSIGN	311	0	0
CONT_ASSIGN	312	1	1	100.00
CONT_ASSIGN	410	1	1	100.00
ALWAYS	413	15	11	73.33
CONT_ASSIGN	450	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	454	1	1	100.00
CONT_ASSIGN	464	1	1	100.00
CONT_ASSIGN	465	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	469	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	473	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	482	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	486	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	491	1	1	100.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	493	1	0	0.00
CONT_ASSIGN	501	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	0	0.00
CONT_ASSIGN	505	1	0	0.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	505	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	509	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	518	1	0	0.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	518	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	522	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	527	1	1	100.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	529	1	0	0.00
CONT_ASSIGN	541	1	1	100.00
CONT_ASSIGN	546	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	551	1	1	100.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	572	1	0	0.00
CONT_ASSIGN	576	1	0	0.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
132	1	1
161	1	1
162	1	1
163	1	1
166	1	1
167	1	1
168	1	1
			MISSING_ELSE
170	1	1
171	1	1
			MISSING_ELSE
173	1	1
174	1	1
			MISSING_ELSE
176	1	1
177	1	1
			MISSING_ELSE
179	1	1
180	1	1
			MISSING_ELSE
182	1	1
183	1	1
			MISSING_ELSE
185	1	1
186	1	1
			MISSING_ELSE
188	1	1
189	1	1
			MISSING_ELSE
191	1	1
192	1	1
			MISSING_ELSE
196	1	1
197	1	1
198	1	1
			MISSING_ELSE
200	1	1
201	1	1
			MISSING_ELSE
203	1	1
204	1	1
			MISSING_ELSE
206	1	1
207	1	1
			MISSING_ELSE
209	1	1
210	1	1
			MISSING_ELSE
212	1	1
213	1	1
			MISSING_ELSE
215	1	1
216	1	1
			MISSING_ELSE
218	1	1
219	1	1
			MISSING_ELSE
221	1	1
222	1	1
			MISSING_ELSE
242	16	16
243	14	16
244		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
245		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
246		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
247		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
248	16	16
249	16	16
250	14	16
251	16	16
264	47	47
265	47	47
266		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
267		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
268		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
269		excluded
			Exclude Annotation 0: vcs_gen_start:k=0:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 1: vcs_gen_start:k=1:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 2: vcs_gen_start:k=2:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 3: vcs_gen_start:k=3:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 4: vcs_gen_start:k=4:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 5: vcs_gen_start:k=5:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 6: vcs_gen_start:k=6:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 7: vcs_gen_start:k=7:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 8: vcs_gen_start:k=8:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 9: vcs_gen_start:k=9:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 10: vcs_gen_start:k=10:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 11: vcs_gen_start:k=11:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 12: vcs_gen_start:k=12:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 13: vcs_gen_start:k=13:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 14: vcs_gen_start:k=14:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 15: vcs_gen_start:k=15:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 16: vcs_gen_start:k=16:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 17: vcs_gen_start:k=17:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 18: vcs_gen_start:k=18:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 19: vcs_gen_start:k=19:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 20: vcs_gen_start:k=20:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 21: vcs_gen_start:k=21:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 22: vcs_gen_start:k=22:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 23: vcs_gen_start:k=23:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 24: vcs_gen_start:k=24:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 25: vcs_gen_start:k=25:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 26: vcs_gen_start:k=26:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 27: vcs_gen_start:k=27:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 28: vcs_gen_start:k=28:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 29: vcs_gen_start:k=29:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 30: vcs_gen_start:k=30:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 31: vcs_gen_start:k=31:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 32: vcs_gen_start:k=32:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 33: vcs_gen_start:k=33:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 34: vcs_gen_start:k=34:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 35: vcs_gen_start:k=35:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 36: vcs_gen_start:k=36:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 37: vcs_gen_start:k=37:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 38: vcs_gen_start:k=38:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 39: vcs_gen_start:k=39:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 40: vcs_gen_start:k=40:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 41: vcs_gen_start:k=41:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 42: vcs_gen_start:k=42:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 43: vcs_gen_start:k=43:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 44: vcs_gen_start:k=44:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 45: vcs_gen_start:k=45:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
			Exclude Annotation 46: vcs_gen_start:k=46:vcs_gen_end:[UNR] Cannot be exercised due to warl_mask value.
270	47	47
271	47	47
272	47	47
273	47	47
311		unreachable
312	1	1
410	1	1
413	1	1
414	1	1
415	1	1
416	1	1
417	1	1
418	1	1
420	1	1
423	1	1
424	1	1
425	0	1
426	0	1
			MISSING_ELSE
431	1	1
432	1	1
433	0	1
434	0	1
			MISSING_ELSE
450	1	1
454	57	57
464	1	1
465	1	1
469	47	47
473	47	47
482	47	47
486	47	47
491	47	47
493	0	47
501	1	1
505	14	16
509	16	16
518	14	16
522	16	16
527	16	16
529	0	16
541	1	1
546	1	1
551	8	8
572	0	8
576	0	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Total	Covered	Percent
Conditions	1975	957	48.46
Logical	1975	957	48.46
Non-Logical	0	0
Event	0	0

This module contains a very large number of conditions, so the report has been split into multiple pages, by source line number. Click on the line number range in the table below to see the condition coverage for that section of the module.

Line numbers	Percent
132-482	50.20
482-486	50.00
486-518	45.59
518-551	48.21

---

Toggle Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Total	Covered	Percent
Totals	399	341	85.46
Total Bits	1938	1760	90.82
Total Bits 0->1	969	880	90.82
Total Bits 1->0	969	880	90.82

Ports	399	341	85.46
Port Bits	1938	1760	90.82
Port Bits 0->1	969	880	90.82
Port Bits 1->0	969	880	90.82

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction	Exclude Annotation
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_sys_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
scanmode_i[3:0]	Unreachable	Unreachable		Unreachable		INPUT
clk_aon_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_aon_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
pin_wkup_req_o	No	No		No		OUTPUT
usb_wkup_req_o	No	No		No		OUTPUT
sleep_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
strap_en_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
strap_en_override_i	Unreachable	Unreachable		Unreachable		INPUT
lc_dft_en_i[3:0]	No	No		No		INPUT
lc_hw_debug_en_i[3:0]	No	No		No		INPUT
lc_check_byp_en_i[3:0]	No	No		No		INPUT
lc_escalate_en_i[3:0]	No	No		No		INPUT
pinmux_hw_debug_en_o[3:0]	No	No		No		OUTPUT
dft_strap_test_o.straps[1:0]	No	No		No		OUTPUT
dft_strap_test_o.valid	No	No		No		OUTPUT
dft_hold_tap_sel_i	Unreachable	Unreachable		Unreachable		INPUT
lc_jtag_o.tdi	No	No		No		OUTPUT
lc_jtag_o.trst_n	No	No		No		OUTPUT
lc_jtag_o.tms	No	No		No		OUTPUT
lc_jtag_o.tck	No	No		No		OUTPUT
lc_jtag_i.tdo_oe	No	No		No		INPUT
lc_jtag_i.tdo	No	No		No		INPUT
rv_jtag_o.tdi	No	No		No		OUTPUT
rv_jtag_o.trst_n	No	No		No		OUTPUT
rv_jtag_o.tms	No	No		No		OUTPUT
rv_jtag_o.tck	No	No		No		OUTPUT
rv_jtag_i.tdo_oe	No	No		No		INPUT
rv_jtag_i.tdo	No	No		No		INPUT
dft_jtag_o.tdi	No	No		No		OUTPUT
dft_jtag_o.trst_n	No	No		No		OUTPUT
dft_jtag_o.tms	No	No		No		OUTPUT
dft_jtag_o.tck	No	No		No		OUTPUT
dft_jtag_i.tdo_oe	No	No		No		INPUT
dft_jtag_i.tdo	No	No		No		INPUT
usbdev_dppullup_en_i	No	No		No		INPUT
usbdev_dnpullup_en_i	No	No		No		INPUT
usb_dppullup_en_o	No	No		No		OUTPUT
usb_dnpullup_en_o	No	No		No		OUTPUT
usbdev_suspend_req_i	No	No		No		INPUT
usbdev_wake_ack_i	No	No		No		INPUT
usbdev_bus_reset_o	No	No		No		OUTPUT
usbdev_sense_lost_o	No	No		No		OUTPUT
usbdev_wake_detect_active_o	No	No		No		OUTPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.cmd_intg[6:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.instr_type[2:1]	No	No		No		INPUT
tl_i.a_user.instr_type[3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_mask[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[1:0]	No	No		No		INPUT
tl_i.a_address[10:2]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[11]	No	No		No		INPUT
tl_i.a_address[16:12]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18:17]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[21:19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[29:23]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[0]	No	No		No		INPUT
tl_i.a_source[5:1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
tl_i.a_opcode[2:1]	No	No		No		INPUT
tl_i.a_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_o.a_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[2]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[4:3]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_user.rsp_intg[6:5]	No	No		No		OUTPUT
tl_o.d_data[31:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[0]	No	No		No		OUTPUT
tl_o.d_source[5:1]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	No	No		No		OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	No	No		No		INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	No	No		No		OUTPUT
periph_to_mio_i[74:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
periph_to_mio_oe_i[74:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
mio_to_periph_o[56:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
periph_to_dio_i[11:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
periph_to_dio_i[13:12]	No	No		No		INPUT
periph_to_dio_i[15:14]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
periph_to_dio_oe_i[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dio_to_periph_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[0].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[0].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[0].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[0].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[0].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[0].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[1].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[1].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[1].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[1].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[2].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[2].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[2].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[2].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[3].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[3].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[3].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[3].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[4].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[4].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[4].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[4].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[5].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[5].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[5].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[5].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[6].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[6].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[6].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[6].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[7].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[7].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[7].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[7].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[8].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[8].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[8].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[8].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[9].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[9].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[9].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[9].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[10].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[10].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[10].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[10].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[11].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[11].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[11].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[11].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[12].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[12].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[12].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[12].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[13].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[13].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[13].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[13].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[14].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[14].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[14].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[14].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[15].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[15].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[15].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[15].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[16].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[16].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[16].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[16].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[16].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[16].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[17].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[17].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[17].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[17].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[17].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[17].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[18].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[18].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[18].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[18].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[18].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[18].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[19].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[19].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[19].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[19].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[19].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[19].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[20].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[20].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[20].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[20].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[20].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[20].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[21].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[21].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[21].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[21].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[21].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[21].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[22].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[22].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[22].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[22].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[22].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[22].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[23].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[23].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[23].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[23].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[23].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[23].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[24].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[24].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[24].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[24].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[24].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[24].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[25].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[25].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[26].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[26].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[26].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[26].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[26].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[26].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[27].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[27].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[27].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[27].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[27].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[27].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[28].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[28].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[28].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[28].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[28].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[28].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[29].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[29].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[29].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[29].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[29].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[29].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[30].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[30].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[30].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[30].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[30].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[30].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[31].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[31].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[31].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[31].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[31].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[31].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[32].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[32].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[32].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[32].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[32].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[32].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[33].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[33].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[33].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[33].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[33].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[33].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[34].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[34].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[34].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[34].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[34].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[34].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[35].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[35].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[35].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[35].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[35].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[35].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[36].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[36].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[36].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[36].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[36].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[36].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[37].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[37].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[37].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[37].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[37].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[37].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[38].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[38].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[38].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[38].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[38].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[38].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[39].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[39].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[39].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[39].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[39].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[39].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[40].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[40].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[40].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[40].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[40].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[40].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[41].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[41].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[41].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[41].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[41].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[41].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[42].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[42].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[42].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[42].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[42].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[42].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[43].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[43].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[43].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[43].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[43].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[43].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[44].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[44].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[44].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[44].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[44].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[44].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[45].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[45].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[45].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[45].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[45].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[45].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[46].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[46].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[46].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[46].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_attr_o[46].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
mio_attr_o[46].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
mio_out_o[46:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_oe_o[46:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
mio_in_i[46:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
dio_attr_o[0].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].keep_en	No	No		No		OUTPUT
dio_attr_o[0].schmitt_en	No	No		No		OUTPUT
dio_attr_o[0].od_en	No	No		No		OUTPUT
dio_attr_o[0].slew_rate[1:0]	No	No		No		OUTPUT
dio_attr_o[0].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[0].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[1].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[1].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[2].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[2].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[2].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[2].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[2].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[2].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[3].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[3].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[3].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[3].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[3].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[3].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[4].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[4].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[4].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[4].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[4].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[4].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[5].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[5].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[5].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[5].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[5].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[5].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[6].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[6].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[6].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[6].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[6].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[6].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[7].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[7].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[7].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[7].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[7].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[7].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[8].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[8].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[8].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[8].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[8].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[8].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[9].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[9].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[9].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[9].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[9].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[9].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[10].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[10].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[10].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[10].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[10].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[10].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[11].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[11].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[11].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[11].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[11].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[11].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[12].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[12].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[12].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[12].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[12].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[13].virt_od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[13].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[13].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[13].drive_strength[0]	No	No		No		OUTPUT
dio_attr_o[13].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[14].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[14].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[14].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[14].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[14].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[14].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].invert	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[15].virt_od_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[15].pull_en	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[15].pull_select	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[15].keep_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].schmitt_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].od_en[0:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].slew_rate[1:0]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_attr_o[15].drive_strength[0]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	OUTPUT
dio_attr_o[15].drive_strength[3:1]	Excluded	Excluded		Excluded		OUTPUT	[UNR] Tie offs.
dio_out_o[11:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_out_o[13:12]	No	No		No		OUTPUT
dio_out_o[15:14]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_oe_o[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
dio_in_i[15:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT

*Tests covering at least one bit in the range

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Line No.	Total	Covered	Percent
Branches		776	264	34.02
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	469	2	1	50.00
TERNARY	473	2	1	50.00
TERNARY	482	4	1	25.00
TERNARY	486	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	505	2	1	50.00
TERNARY	509	2	1	50.00
TERNARY	518	4	1	25.00
TERNARY	522	4	1	25.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
TERNARY	551	2	1	50.00
IF	161	2	2	100.00
IF	413	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv' or '../src/lowrisc_ip_pinmux_component_0.1/rtl/pinmux.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[16].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[16].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[16].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[16].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[16].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[17].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[17].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[17].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[17].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[17].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[18].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[18].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[18].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[18].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[18].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[19].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[19].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[19].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[19].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[19].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[20].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[20].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[20].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[20].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[20].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[21].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[21].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[21].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[21].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[21].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[22].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[22].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[22].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[22].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[22].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[23].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[23].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[23].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[23].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[23].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[24].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[24].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[24].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[24].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[24].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[25].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[25].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[25].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[25].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[25].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[26].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[26].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[26].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[26].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[26].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[27].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[27].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[27].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[27].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[27].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[28].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[28].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[28].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[28].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[28].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[29].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[29].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[29].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[29].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[29].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[30].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[30].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[30].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[30].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[30].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[31].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[31].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[31].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[31].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[31].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[32].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[32].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[32].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[32].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[32].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[33].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[33].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[33].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[33].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[33].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[34].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[34].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[34].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[34].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[34].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[35].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[35].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[35].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[35].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[35].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[36].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[36].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[36].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[36].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[36].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[37].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[37].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[37].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[37].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[37].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[38].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[38].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[38].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[38].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[38].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[39].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[39].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[39].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[39].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[39].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[40].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[40].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[40].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[40].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[40].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[41].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[41].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[41].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[41].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[41].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[42].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[42].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[42].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[42].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[42].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[43].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[43].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[43].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[43].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[43].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[44].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[44].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[44].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[44].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[44].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[45].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[45].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[45].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[45].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[45].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	469	(reg2hw.mio_pad_sleep_status[46].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	473	(reg2hw.mio_pad_sleep_status[46].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	482	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	482	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	482	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	486	((reg2hw.mio_pad_sleep_mode[46].q == 2'b0)) ? 
-2-:	486	((reg2hw.mio_pad_sleep_mode[46].q == 2'b1)) ? 
-3-:	486	((reg2hw.mio_pad_sleep_mode[46].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[0].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[0].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[0].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[0].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[1].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[1].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[1].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[1].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[2].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[2].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[2].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[2].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[3].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[3].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[3].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[3].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[4].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[4].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[4].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[4].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[5].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[5].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[5].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[5].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[6].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[6].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[6].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[6].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[7].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[7].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[7].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[7].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[8].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[8].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[8].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[8].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[9].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[9].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[9].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[9].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[10].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[10].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[10].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[10].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[11].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[11].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[11].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[11].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[12].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[12].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[12].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[12].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[13].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[13].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[13].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[13].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[14].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[14].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[14].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[14].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	505	(reg2hw.dio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	509	(reg2hw.dio_pad_sleep_status[15].q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	518	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	518	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	518	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	522	((reg2hw.dio_pad_sleep_mode[15].q == 2'b0)) ? 
-2-:	522	((reg2hw.dio_pad_sleep_mode[15].q == 2'b1)) ? 
-3-:	522	((reg2hw.dio_pad_sleep_mode[15].q == 2'h2)) ? 

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Not Covered
0	1	-	Not Covered
0	0	1	Covered	T1,T2,T3
0	0	0	Not Covered

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[0].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[1].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[2].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[3].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[4].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[5].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[6].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	551	(reg2hw.wkup_detector[7].miodio.q) ? 

Branches:

-1-	Status	Tests
1	Not Covered
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	161	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	413	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	25	25	100.00	21	84.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	25	25	100.00	21	84.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AlertsKnown_A	102433	92966	0	0
AonWkupReqKnownO_A	3531	1284	0	0
DftJtagTckKnown_A	102433	92966	0	0
DftJtagTmsKnown_A	102433	92966	0	0
DftJtagTrstKnown_A	102433	92966	0	0
DftStrapsKnown_A	102433	92966	0	0
DioKnownO_A	102433	92966	0	0
DioOeKnownO_A	102433	92966	0	0
FpvSecCmBusIntegrity_A	102433	0	0	0
FpvSecCmRegWeOnehotCheck_A	102433	0	0	0
LcJtagTckKnown_A	102433	92966	0	0
LcJtagTmsKnown_A	102433	92966	0	0
LcJtagTrstKnown_A	102433	92966	0	0
MioKnownO_A	102433	92966	0	0
MioOeKnownO_A	102433	92966	0	0
PinmuxWkupStable_A	3531	0	0	0
PwrMgrStrapSampleOnce0_A	102433	10	0	0
PwrMgrStrapSampleOnce1_A	102433	0	0	0
RvJtagTckKnown_A	102433	92966	0	0
RvJtagTmsKnown_A	102433	92966	0	0
RvJtagTrstKnown_A	102433	92966	0	0
TlAReadyKnownO_A	102433	92966	0	0
TlDValidKnownO_A	102433	92966	0	0
UsbWakeDetectActiveKnownO_A	3531	1284	0	0
UsbWkupReqKnownO_A	3531	1284	0	0

AlertsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

AonWkupReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3531	1284	0	0
T1	346	120	0	0
T2	349	125	0	0
T3	369	147	0	0
T4	304	79	0	0
T5	303	79	0	0
T6	372	146	0	0
T7	333	107	0	0
T8	347	124	0	0
T9	380	156	0	0
T10	428	201	0	0

DftJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

DftJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

DftJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

DftStrapsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

DioKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

DioOeKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

FpvSecCmBusIntegrity_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	0	0	0

FpvSecCmRegWeOnehotCheck_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	0	0	0

LcJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

LcJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

LcJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

MioKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

MioOeKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

PinmuxWkupStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3531	0	0	0

PwrMgrStrapSampleOnce0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	10	0	0
T1	10179	1	0	0
T2	10337	1	0	0
T3	10004	1	0	0
T4	10694	1	0	0
T5	10719	1	0	0
T6	10094	1	0	0
T7	10199	1	0	0
T8	10401	1	0	0
T9	9759	1	0	0
T10	10047	1	0	0

PwrMgrStrapSampleOnce1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	0	0	0

RvJtagTckKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

RvJtagTmsKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

RvJtagTrstKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

TlAReadyKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

TlDValidKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	102433	92966	0	0
T1	10179	9273	0	0
T2	10337	9417	0	0
T3	10004	9306	0	0
T4	10694	9316	0	0
T5	10719	9316	0	0
T6	10094	9317	0	0
T7	10199	9194	0	0
T8	10401	9393	0	0
T9	9759	9052	0	0
T10	10047	9382	0	0

UsbWakeDetectActiveKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3531	1284	0	0
T1	346	120	0	0
T2	349	125	0	0
T3	369	147	0	0
T4	304	79	0	0
T5	303	79	0	0
T6	372	146	0	0
T7	333	107	0	0
T8	347	124	0	0
T9	380	156	0	0
T10	428	201	0	0

UsbWkupReqKnownO_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	3531	1284	0	0
T1	346	120	0	0
T2	349	125	0	0
T3	369	147	0	0
T4	304	79	0	0
T5	303	79	0	0
T6	372	146	0	0
T7	333	107	0	0
T8	347	124	0	0
T9	380	156	0	0
T10	428	201	0	0