Unified Coverage Report :: Module :: keymgr

Module : keymgr

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
11.72			11.72

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_keymgr_0.1/rtl/keymgr.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_keymgr	11.72			11.72

---

Module Instance : tb.dut.top_earlgrey.u_keymgr

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
11.72			11.72

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
11.72			11.72

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
75.19	51.61		73.96			100.00	top_earlgrey

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Toggle Coverage for Module : keymgr

	Total	Covered	Percent
Totals	72	14	19.44
Total Bits	10014	1174	11.72
Total Bits 0->1	5007	587	11.72
Total Bits 1->0	5007	587	11.72

Ports	72	14	19.44
Port Bits	10014	1174	11.72
Port Bits 0->1	5007	587	11.72
Port Bits 1->0	5007	587	11.72

Port Details

Name	Toggle	Toggle 1->0	Tests	Toggle 0->1	Tests	Direction
clk_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_shadowed_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
clk_edn_i	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rst_edn_ni	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.d_ready	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
tl_i.a_user.data_intg[6:0]	No	No		No		INPUT
tl_i.a_user.cmd_intg[6:0]	No	No		No		INPUT
tl_i.a_user.instr_type[3:0]	No	No		No		INPUT
tl_i.a_user.rsvd[4:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_data[31:0]	No	No		No		INPUT
tl_i.a_mask[3:0]	No	No		No		INPUT
tl_i.a_address[7:0]	No	No		No		INPUT
tl_i.a_address[17:8]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[18]	No	No		No		INPUT
tl_i.a_address[19]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[20]	No	No		No		INPUT
tl_i.a_address[23:21]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[24]	No	No		No		INPUT
tl_i.a_address[29:25]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_address[30]	No	No		No		INPUT
tl_i.a_address[31]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_source[5:0]	No	No		No		INPUT
tl_i.a_source[7:6]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_size[1:0]	No	No		No		INPUT
tl_i.a_param[2:0]	Unreachable	Unreachable		Unreachable		INPUT
tl_i.a_opcode[2:0]	No	No		No		INPUT
tl_i.a_valid	No	No		No		INPUT
tl_o.a_ready	No	No		No		OUTPUT
tl_o.d_error	No	No		No		OUTPUT
tl_o.d_user.data_intg[6:0]	No	No		No		OUTPUT
tl_o.d_user.rsp_intg[6:0]	No	No		No		OUTPUT
tl_o.d_data[31:0]	No	No		No		OUTPUT
tl_o.d_sink	No	No		No		OUTPUT
tl_o.d_source[5:0]	No	No		No		OUTPUT
tl_o.d_source[7:6]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_size[1:0]	No	No		No		OUTPUT
tl_o.d_param[2:0]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_opcode[0]	No	No		No		OUTPUT
tl_o.d_opcode[2:1]	Unreachable	Unreachable		Unreachable		OUTPUT
tl_o.d_valid	No	No		No		OUTPUT
aes_key_o.key[1:0][255:0]	No	No		No		OUTPUT
aes_key_o.valid	No	No		No		OUTPUT
kmac_key_o.key[1:0][255:0]	No	No		No		OUTPUT
kmac_key_o.valid	No	No		No		OUTPUT
otbn_key_o.key[1:0][383:0]	No	No		No		OUTPUT
otbn_key_o.valid	No	No		No		OUTPUT
kmac_data_o.last	No	No		No		OUTPUT
kmac_data_o.strb[7:0]	No	No		No		OUTPUT
kmac_data_o.data[63:0]	No	No		No		OUTPUT
kmac_data_o.valid	No	No		No		OUTPUT
kmac_data_i.error	No	No		No		INPUT
kmac_data_i.digest_share1[383:0]	No	No		No		INPUT
kmac_data_i.digest_share0[383:0]	No	No		No		INPUT
kmac_data_i.done	No	No		No		INPUT
kmac_data_i.ready	No	No		No		INPUT
kmac_en_masking_i	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_en_i[3:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[1:0]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[2]	No	No		No		INPUT
lc_keymgr_div_i[3]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[4]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[6:5]	No	No		No		INPUT
lc_keymgr_div_i[7]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[10:8]	No	No		No		INPUT
lc_keymgr_div_i[12:11]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[14:13]	No	No		No		INPUT
lc_keymgr_div_i[15]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[16]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[17]	No	No		No		INPUT
lc_keymgr_div_i[18]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[19]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[20]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[21]	No	No		No		INPUT
lc_keymgr_div_i[22]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[23]	No	No		No		INPUT
lc_keymgr_div_i[26:24]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[27]	No	No		No		INPUT
lc_keymgr_div_i[28]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[29]	No	No		No		INPUT
lc_keymgr_div_i[30]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[32:31]	No	No		No		INPUT
lc_keymgr_div_i[34:33]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[35]	No	No		No		INPUT
lc_keymgr_div_i[36]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[38:37]	No	No		No		INPUT
lc_keymgr_div_i[40:39]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[41]	No	No		No		INPUT
lc_keymgr_div_i[44:42]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[45]	No	No		No		INPUT
lc_keymgr_div_i[46]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[47]	No	No		No		INPUT
lc_keymgr_div_i[48]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[49]	No	No		No		INPUT
lc_keymgr_div_i[50]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[53:51]	No	No		No		INPUT
lc_keymgr_div_i[56:54]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[57]	No	No		No		INPUT
lc_keymgr_div_i[58]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[59]	No	No		No		INPUT
lc_keymgr_div_i[60]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[61]	No	No		No		INPUT
lc_keymgr_div_i[62]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[64:63]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[71:65]	No	No		No		INPUT
lc_keymgr_div_i[72]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[73]	No	No		No		INPUT
lc_keymgr_div_i[77:74]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[78]	No	No		No		INPUT
lc_keymgr_div_i[85:79]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[88:86]	No	No		No		INPUT
lc_keymgr_div_i[89]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[90]	No	No		No		INPUT
lc_keymgr_div_i[96:91]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[97]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[98]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[99]	Unreachable	Unreachable		Unreachable		INPUT
lc_keymgr_div_i[103:100]	No	No		No		INPUT
lc_keymgr_div_i[108:104]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[118:109]	No	No		No		INPUT
lc_keymgr_div_i[119]	Yes	Yes	*T1,*T2,*T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[120]	No	No		No		INPUT
lc_keymgr_div_i[122:121]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[123]	No	No		No		INPUT
lc_keymgr_div_i[125:124]	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
lc_keymgr_div_i[127:126]	No	No		No		INPUT
otp_key_i.owner_seed_valid	No	No		No		INPUT
otp_key_i.owner_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_seed_valid	No	No		No		INPUT
otp_key_i.creator_seed[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share1_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share1[255:0]	No	No		No		INPUT
otp_key_i.creator_root_key_share0_valid	No	No		No		INPUT
otp_key_i.creator_root_key_share0[255:0]	No	No		No		INPUT
otp_device_id_i[255:0]	Yes	Yes	T4,T5,T6	Yes	T4,T5,T6	INPUT
flash_i.seeds[1:0][255:0]	No	No		No		INPUT
edn_o.edn_req	No	No		No		OUTPUT
edn_i.edn_bus[31:0]	No	No		No		INPUT
edn_i.edn_fips	No	No		No		INPUT
edn_i.edn_ack	No	No		No		INPUT
rom_digest_i.valid	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
rom_digest_i.data[255:0]	Yes	Yes	T2,T3,T4	Yes	T2,T3,T4	INPUT
intr_op_done_o	No	No		No		OUTPUT
alert_rx_i[0].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[0].ack_p	No	No		No		INPUT
alert_rx_i[0].ping_n	No	No		No		INPUT
alert_rx_i[0].ping_p	No	No		No		INPUT
alert_rx_i[1].ack_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	INPUT
alert_rx_i[1].ack_p	No	No		No		INPUT
alert_rx_i[1].ping_n	No	No		No		INPUT
alert_rx_i[1].ping_p	No	No		No		INPUT
alert_tx_o[0].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[0].alert_p	No	No		No		OUTPUT
alert_tx_o[1].alert_n	Yes	Yes	T1,T2,T3	Yes	T1,T2,T3	OUTPUT
alert_tx_o[1].alert_p	No	No		No		OUTPUT

*Tests covering at least one bit in the range