Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_uart0.uart_core.u_uart_txfifo

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
75.00	50.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_i

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		fifo_h

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[0].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00					100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00		100.00			100.00		gen_dfifo[1].fifo_d

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415001954	44453003	0	0
DepthKnown_A	415001954	414900945	0	0
RvalidKnown_A	415001954	414900945	0	0
WreadyKnown_A	415001954	414900945	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	44453003	0	0
T1	217797	27464	0	0
T2	95990	56406	0	0
T3	220929	19822	0	0
T4	627535	78931	0	0
T32	273302	34556	0	0
T39	489610	70884	0	0
T49	156805	20883	0	0
T83	91942	10674	0	0
T84	113996	12796	0	0
T85	371269	51496	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	2	50.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	0	0.00
CONT_ASSIGN	49	1	0	0.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	0	1
49	0	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_i.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415001954	33844036	0	0
DepthKnown_A	415001954	414900945	0	0
RvalidKnown_A	415001954	414900945	0	0
WreadyKnown_A	415001954	414900945	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	33844036	0	0
T1	217797	23581	0	0
T2	95990	27773	0	0
T3	220929	15531	0	0
T4	627535	62464	0	0
T32	273302	25343	0	0
T39	489610	53515	0	0
T49	156805	15756	0	0
T83	91942	8380	0	0
T84	113996	10140	0	0
T85	371269	48260	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415001954	29888676	0	0
DepthKnown_A	415001954	414900945	0	0
RvalidKnown_A	415001954	414900945	0	0
WreadyKnown_A	415001954	414900945	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	29888676	0	0
T1	217797	13230	0	0
T2	95990	6617	0	0
T3	220929	11469	0	0
T4	627535	112091	0	0
T32	273302	18725	0	0
T39	489610	107566	0	0
T49	156805	9413	0	0
T83	91942	6406	0	0
T84	113996	5765	0	0
T85	371269	7667	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	415001954	24665149	0	0
DepthKnown_A	415001954	414900945	0	0
RvalidKnown_A	415001954	414900945	0	0
WreadyKnown_A	415001954	414900945	0	0
gen_passthru_fifo.paramCheckPass	942	942	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	24665149	0	0
T1	217797	13031	0	0
T2	95990	5961	0	0
T3	220929	11224	0	0
T4	627535	54802	0	0
T32	273302	18340	0	0
T39	489610	44707	0	0
T49	156805	9136	0	0
T83	91942	6281	0	0
T84	113996	5622	0	0
T85	371269	7492	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	414900945	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481828093	82682	0	0
DepthKnown_A	481828093	481715285	0	0
RvalidKnown_A	481828093	481715285	0	0
WreadyKnown_A	481828093	481715285	0	0
gen_passthru_fifo.paramCheckPass	2831	2831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	82682	0	0
T1	217797	101	0	0
T2	95990	34	0	0
T3	220929	30	0	0
T4	627535	19	0	0
T32	273302	151	0	0
T39	489610	26	0	0
T49	156805	26	0	0
T83	91942	13	0	0
T84	113996	18	0	0
T85	371269	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2831	2831	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.fifo_h.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481828093	85194	0	0
DepthKnown_A	481828093	481715285	0	0
RvalidKnown_A	481828093	481715285	0	0
WreadyKnown_A	481828093	481715285	0	0
gen_passthru_fifo.paramCheckPass	2831	2831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	85194	0	0
T1	217797	101	0	0
T2	95990	34	0	0
T3	220929	30	0	0
T4	627535	19	0	0
T32	273302	151	0	0
T39	489610	26	0	0
T49	156805	26	0	0
T83	91942	13	0	0
T84	113996	18	0	0
T85	371269	23	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2831	2831	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481828093	49026	0	0
DepthKnown_A	481828093	481715285	0	0
RvalidKnown_A	481828093	481715285	0	0
WreadyKnown_A	481828093	481715285	0	0
gen_passthru_fifo.paramCheckPass	2831	2831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	49026	0	0
T1	217797	16	0	0
T2	95990	31	0	0
T3	220929	28	0	0
T4	627535	0	0	0
T5	0	64	0	0
T32	273302	95	0	0
T39	489610	5	0	0
T49	156805	23	0	0
T83	91942	12	0	0
T84	113996	17	0	0
T85	371269	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2831	2831	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[0].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481828093	49026	0	0
DepthKnown_A	481828093	481715285	0	0
RvalidKnown_A	481828093	481715285	0	0
WreadyKnown_A	481828093	481715285	0	0
gen_passthru_fifo.paramCheckPass	2831	2831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	49026	0	0
T1	217797	16	0	0
T2	95990	31	0	0
T3	220929	28	0	0
T4	627535	0	0	0
T5	0	64	0	0
T32	273302	95	0	0
T39	489610	5	0	0
T49	156805	23	0	0
T83	91942	12	0	0
T84	113996	17	0	0
T85	371269	20	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2831	2831	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.reqfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481828093	33656	0	0
DepthKnown_A	481828093	481715285	0	0
RvalidKnown_A	481828093	481715285	0	0
WreadyKnown_A	481828093	481715285	0	0
gen_passthru_fifo.paramCheckPass	2831	2831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	33656	0	0
T1	217797	85	0	0
T2	95990	3	0	0
T3	220929	2	0	0
T4	627535	19	0	0
T32	273302	56	0	0
T39	489610	21	0	0
T49	156805	3	0	0
T83	91942	1	0	0
T84	113996	1	0	0
T85	371269	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2831	2831	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	44	1	1	100.00
CONT_ASSIGN	45	1	1	100.00
CONT_ASSIGN	48	1	1	100.00
CONT_ASSIGN	49	1	1	100.00
CONT_ASSIGN	53	0	0

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' or '../src/lowrisc_prim_fifo_0/rtl/prim_fifo_sync.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
44	1	1
45	1	1
48	1	1
49	1	1
53		unreachable

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_reg_cfg.u_socket.gen_dfifo[1].fifo_d.rspfifo

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	5	5	100.00	5	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	5	5	100.00	5	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
DataKnown_A	481828093	36168	0	0
DepthKnown_A	481828093	481715285	0	0
RvalidKnown_A	481828093	481715285	0	0
WreadyKnown_A	481828093	481715285	0	0
gen_passthru_fifo.paramCheckPass	2831	2831	0	0

DataKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	36168	0	0
T1	217797	85	0	0
T2	95990	3	0	0
T3	220929	2	0	0
T4	627535	19	0	0
T32	273302	56	0	0
T39	489610	21	0	0
T49	156805	3	0	0
T83	91942	1	0	0
T84	113996	1	0	0
T85	371269	3	0	0

DepthKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

RvalidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

WreadyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	481828093	481715285	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_passthru_fifo.paramCheckPass

Name	Attempts	Real Successes	Failures	Incomplete
Total	2831	2831	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0