Line Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 21 | 91.30 |
ALWAYS | 69 | 3 | 3 | 100.00 |
ALWAYS | 77 | 5 | 5 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
ALWAYS | 131 | 4 | 3 | 75.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
ALWAYS | 166 | 0 | 0 | |
ALWAYS | 176 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
115 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
0 |
1 |
|
|
|
MISSING_ELSE |
140 |
1 |
1 |
144 |
1 |
1 |
148 |
0 |
1 |
152 |
1 |
1 |
166 |
|
unreachable |
168 |
|
unreachable |
169 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
176 |
|
unreachable |
177 |
|
unreachable |
179 |
|
unreachable |
Line Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 69 | 3 | 3 | 100.00 |
ALWAYS | 77 | 5 | 5 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 0 | 0 | |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
ALWAYS | 131 | 4 | 3 | 75.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
ALWAYS | 166 | 0 | 0 | |
ALWAYS | 176 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
93 |
|
unreachable |
95 |
1 |
1 |
115 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
0 |
1 |
|
|
|
MISSING_ELSE |
140 |
1 |
1 |
144 |
1 |
1 |
148 |
0 |
1 |
152 |
1 |
1 |
166 |
|
unreachable |
168 |
|
unreachable |
169 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
176 |
|
unreachable |
177 |
|
unreachable |
179 |
|
unreachable |
Cond Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 13 | 9 | 69.23 |
Logical | 13 | 9 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 79
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
--------------------------------------------1-------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 140
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T32,T202,T203 |
LINE 144
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Cond Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
Conditions | 17 | 14 | 82.35 |
Logical | 17 | 14 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 79
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T72,T74,T75 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T32,T58,T204 |
LINE 144
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=2,EnableDataIntgGen=1,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 + MAX_REQS=2,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=2,g_multiple_reqs.ReqNumW=1 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
IF |
131 |
3 |
2 |
66.67 |
IF |
69 |
2 |
2 |
100.00 |
IF |
79 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 93 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 131 if ((!rst_ni))
-2-: 133 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 79 if ((req_i && gnt_o))
-2-: 80 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Branch Coverage for Module :
tlul_adapter_host ( parameter MAX_REQS=8,EnableDataIntgGen=0,EnableRspDataIntgCheck=0,WordSize=2,OutstandingReqCntW=4,g_multiple_reqs.ReqNumW=3 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
8 |
88.89 |
TERNARY |
93 |
1 |
1 |
100.00 |
IF |
131 |
3 |
2 |
66.67 |
IF |
69 |
2 |
2 |
100.00 |
IF |
79 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 93 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 131 if ((!rst_ni))
-2-: 133 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 79 if ((req_i && gnt_o))
-2-: 80 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Module :
tlul_adapter_host
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
830003908 |
74298899 |
0 |
0 |
T1 |
435594 |
40694 |
0 |
0 |
T2 |
191980 |
63023 |
0 |
0 |
T3 |
441858 |
31291 |
0 |
0 |
T4 |
1255070 |
191022 |
0 |
0 |
T32 |
546604 |
53281 |
0 |
0 |
T39 |
979220 |
178450 |
0 |
0 |
T49 |
313610 |
30296 |
0 |
0 |
T83 |
183884 |
17080 |
0 |
0 |
T84 |
227992 |
18561 |
0 |
0 |
T85 |
742538 |
59163 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Line No. | Total | Covered | Percent |
TOTAL | | 22 | 20 | 90.91 |
ALWAYS | 69 | 3 | 3 | 100.00 |
ALWAYS | 77 | 5 | 5 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 0 | 0 | |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
ALWAYS | 131 | 4 | 3 | 75.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
ALWAYS | 166 | 0 | 0 | |
ALWAYS | 176 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
93 |
|
unreachable |
95 |
1 |
1 |
115 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
0 |
1 |
|
|
|
MISSING_ELSE |
140 |
1 |
1 |
144 |
1 |
1 |
148 |
0 |
1 |
152 |
1 |
1 |
166 |
|
unreachable |
168 |
|
unreachable |
169 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
176 |
|
unreachable |
177 |
|
unreachable |
179 |
|
unreachable |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Total | Covered | Percent |
Conditions | 13 | 9 | 69.23 |
Logical | 13 | 9 | 69.23 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 79
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Not Covered | |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0])
--------------------------------------------1-------------------------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Unreachable | |
1 | Unreachable | |
LINE 140
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T32,T202,T203 |
LINE 144
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
| Line No. | Total | Covered | Percent |
Branches |
|
9 |
8 |
88.89 |
TERNARY |
93 |
1 |
1 |
100.00 |
IF |
131 |
3 |
2 |
66.67 |
IF |
69 |
2 |
2 |
100.00 |
IF |
79 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 93 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Unreachable |
|
LineNo. Expression
-1-: 131 if ((!rst_ni))
-2-: 133 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 79 if ((req_i && gnt_o))
-2-: 80 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[(g_multiple_reqs.ReqNumW - 1):0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_i_ibex
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415001954 |
44453003 |
0 |
0 |
T1 |
217797 |
27464 |
0 |
0 |
T2 |
95990 |
56406 |
0 |
0 |
T3 |
220929 |
19822 |
0 |
0 |
T4 |
627535 |
78931 |
0 |
0 |
T32 |
273302 |
34556 |
0 |
0 |
T39 |
489610 |
70884 |
0 |
0 |
T49 |
156805 |
20883 |
0 |
0 |
T83 |
91942 |
10674 |
0 |
0 |
T84 |
113996 |
12796 |
0 |
0 |
T85 |
371269 |
51496 |
0 |
0 |
Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Line No. | Total | Covered | Percent |
TOTAL | | 23 | 21 | 91.30 |
ALWAYS | 69 | 3 | 3 | 100.00 |
ALWAYS | 77 | 5 | 5 | 100.00 |
CONT_ASSIGN | 88 | 1 | 1 | 100.00 |
CONT_ASSIGN | 93 | 1 | 1 | 100.00 |
CONT_ASSIGN | 95 | 1 | 1 | 100.00 |
CONT_ASSIGN | 115 | 1 | 1 | 100.00 |
CONT_ASSIGN | 117 | 1 | 1 | 100.00 |
CONT_ASSIGN | 118 | 1 | 1 | 100.00 |
CONT_ASSIGN | 119 | 1 | 1 | 100.00 |
ALWAYS | 131 | 4 | 3 | 75.00 |
CONT_ASSIGN | 140 | 1 | 1 | 100.00 |
CONT_ASSIGN | 144 | 1 | 1 | 100.00 |
CONT_ASSIGN | 148 | 1 | 0 | 0.00 |
CONT_ASSIGN | 152 | 1 | 1 | 100.00 |
ALWAYS | 166 | 0 | 0 | |
ALWAYS | 176 | 0 | 0 | |
WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' was not found, so annotated line coverage report could not be generated.
Line No. | Covered | Statements | |
69 |
1 |
1 |
70 |
1 |
1 |
72 |
1 |
1 |
77 |
1 |
1 |
79 |
1 |
1 |
80 |
1 |
1 |
81 |
1 |
1 |
83 |
1 |
1 |
|
|
|
MISSING_ELSE |
88 |
1 |
1 |
93 |
1 |
1 |
95 |
1 |
1 |
115 |
1 |
1 |
117 |
1 |
1 |
118 |
1 |
1 |
119 |
1 |
1 |
131 |
1 |
1 |
132 |
1 |
1 |
133 |
1 |
1 |
134 |
0 |
1 |
|
|
|
MISSING_ELSE |
140 |
1 |
1 |
144 |
1 |
1 |
148 |
0 |
1 |
152 |
1 |
1 |
166 |
|
unreachable |
168 |
|
unreachable |
169 |
|
unreachable |
170 |
|
unreachable |
171 |
|
unreachable |
|
|
|
==> MISSING_ELSE |
176 |
|
unreachable |
177 |
|
unreachable |
179 |
|
unreachable |
Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Total | Covered | Percent |
Conditions | 17 | 14 | 82.35 |
Logical | 17 | 14 | 82.35 |
Non-Logical | 0 | 0 | |
Event | 0 | 0 | |
LINE 79
EXPRESSION (req_i && gnt_o)
--1-- --2--
-1- | -2- | Status | Tests |
0 | 1 | Covered | T72,T74,T75 |
1 | 0 | Covered | T1,T2,T3 |
1 | 1 | Covered | T1,T2,T3 |
LINE 80
EXPRESSION (g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0])
-----------------------------1----------------------------
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 93
EXPRESSION (((~we_i)) ? ({top_pkg::TL_DBW {1'b1}}) : be_i)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 95
EXPRESSION (((~we_i)) ? Get : (((&be_i)) ? PutFullData : PutPartialData))
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 95
SUB-EXPRESSION (((&be_i)) ? PutFullData : PutPartialData)
----1----
-1- | Status | Tests |
0 | Covered | T1,T2,T3 |
1 | Covered | T1,T2,T3 |
LINE 140
EXPRESSION (tl_i.d_error | intg_err)
------1----- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Covered | T32,T58,T204 |
LINE 144
EXPRESSION (intg_err_q | intg_err)
-----1---- ----2---
-1- | -2- | Status | Tests |
0 | 0 | Covered | T1,T2,T3 |
0 | 1 | Not Covered | |
1 | 0 | Not Covered | |
Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
| Line No. | Total | Covered | Percent |
Branches |
|
10 |
9 |
90.00 |
TERNARY |
93 |
2 |
2 |
100.00 |
IF |
131 |
3 |
2 |
66.67 |
IF |
69 |
2 |
2 |
100.00 |
IF |
79 |
3 |
3 |
100.00 |
WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv' or '../src/lowrisc_tlul_adapter_host_0.1/rtl/tlul_adapter_host.sv was not found/opened, so annotated branch coverage report could not be generated.
LineNo. Expression
-1-: 93 ((~we_i)) ?
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 131 if ((!rst_ni))
-2-: 133 if (intg_err)
Branches:
-1- | -2- | Status | Tests |
1 |
- |
Covered |
T1,T2,T3 |
0 |
1 |
Not Covered |
|
0 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 69 if ((!rst_ni))
Branches:
-1- | Status | Tests |
1 |
Covered |
T1,T2,T3 |
0 |
Covered |
T1,T2,T3 |
LineNo. Expression
-1-: 79 if ((req_i && gnt_o))
-2-: 80 if ((g_multiple_reqs.source_q == g_multiple_reqs.MaxSource[0]))
Branches:
-1- | -2- | Status | Tests |
1 |
1 |
Covered |
T1,T2,T3 |
1 |
0 |
Covered |
T1,T2,T3 |
0 |
- |
Covered |
T1,T2,T3 |
Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.tl_adapter_host_d_ibex
Assertion Details
DontExceeedMaxReqs
Name | Attempts | Real Successes | Failures | Incomplete |
Total |
415001954 |
29845896 |
0 |
0 |
T1 |
217797 |
13230 |
0 |
0 |
T2 |
95990 |
6617 |
0 |
0 |
T3 |
220929 |
11469 |
0 |
0 |
T4 |
627535 |
112091 |
0 |
0 |
T32 |
273302 |
18725 |
0 |
0 |
T39 |
489610 |
107566 |
0 |
0 |
T49 |
156805 |
9413 |
0 |
0 |
T83 |
91942 |
6406 |
0 |
0 |
T84 |
113996 |
5765 |
0 |
0 |
T85 |
371269 |
7667 |
0 |
0 |