Unified Coverage Report :: Module :: prim_arbiter_fixed

Module : prim_arbiter_fixed

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86
tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region	94.88	100.00	86.67			100.00	92.86

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_ibus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Module Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.88	100.00	86.67			100.00	92.86

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_dbus_trans

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Module : prim_arbiter_fixed

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T137,T138,T139
0	1	Covered	T137,T138,T139
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T137,T138,T139
1	Covered	T137,T138,T139

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T137,T138,T139
1	Covered	T137,T138,T139

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T137,T138,T139
1	1	Covered	T137,T138,T139

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T137,T138,T139
1	0	Covered	T137,T138,T139
1	1	Covered	T137,T138,T139

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T137,T138,T139

---

Branch Coverage for Module : prim_arbiter_fixed

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T137,T138,T139
0	Covered	T137,T138,T139

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T137,T138,T139
0	Covered	T137,T138,T139

---

Assert Coverage for Module : prim_arbiter_fixed

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	830003908	811061618	0	0
CheckNGreaterZero_A	1884	1884	0	0
GntImpliesReady_A	830003908	5441	0	0
GntImpliesValid_A	830003908	5441	0	0
GrantKnown_A	830003908	811061618	0	0
IdxKnown_A	830003908	811061618	0	0
IndexIsCorrect_A	830003908	5441	0	0
NoReadyValidNoGrant_A	830003908	0	0	0
Priority_A	830003908	5441	0	0
ReadyAndValidImplyGrant_A	830003908	5441	0	0
ReqAndReadyImplyGrant_A	830003908	5441	0	0
ReqImpliesValid_A	830003908	5441	0	0
ValidKnown_A	830003908	811061618	0	0
gen_data_port_assertion.DataFlow_A	830003908	5441	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	811061618	0	0
T1	435594	435470	0	0
T2	191980	191856	0	0
T3	441858	441654	0	0
T4	1255070	1254844	0	0
T32	546604	546370	0	0
T39	979220	979110	0	0
T49	313610	313508	0	0
T83	183884	183782	0	0
T84	227992	227876	0	0
T85	742538	742422	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1884	1884	0	0
T1	2	2	0	0
T2	2	2	0	0
T3	2	2	0	0
T4	2	2	0	0
T32	2	2	0	0
T39	2	2	0	0
T49	2	2	0	0
T83	2	2	0	0
T84	2	2	0	0
T85	2	2	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	811061618	0	0
T1	435594	435470	0	0
T2	191980	191856	0	0
T3	441858	441654	0	0
T4	1255070	1254844	0	0
T32	546604	546370	0	0
T39	979220	979110	0	0
T49	313610	313508	0	0
T83	183884	183782	0	0
T84	227992	227876	0	0
T85	742538	742422	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	811061618	0	0
T1	435594	435470	0	0
T2	191980	191856	0	0
T3	441858	441654	0	0
T4	1255070	1254844	0	0
T32	546604	546370	0	0
T39	979220	979110	0	0
T49	313610	313508	0	0
T83	183884	183782	0	0
T84	227992	227876	0	0
T85	742538	742422	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	811061618	0	0
T1	435594	435470	0	0
T2	191980	191856	0	0
T3	441858	441654	0	0
T4	1255070	1254844	0	0
T32	546604	546370	0	0
T39	979220	979110	0	0
T49	313610	313508	0	0
T83	183884	183782	0	0
T84	227992	227876	0	0
T85	742538	742422	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	830003908	5441	0	0
T135	329894	0	0	0
T137	176070	1813	0	0
T138	0	1817	0	0
T139	0	1811	0	0
T275	706818	0	0	0
T276	123802	0	0	0
T277	1317920	0	0	0
T278	719030	0	0	0
T279	808972	0	0	0
T280	182722	0	0	0
T281	296216	0	0	0
T282	402518	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T137,T138,T139
0	1	Covered	T137,T138,T139
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T137,T138,T139
1	Covered	T137,T138,T139

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T137,T138,T139
1	Covered	T137,T138,T139

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T137,T138,T139
1	1	Covered	T137,T138,T139

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T137,T138,T139
1	0	Covered	T137,T138,T139
1	1	Covered	T137,T138,T139

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T137,T138,T139

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T137,T138,T139
0	Covered	T137,T138,T139

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T137,T138,T139
0	Covered	T137,T138,T139

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_ibus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415001954	405530809	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	415001954	4403	0	0
GntImpliesValid_A	415001954	4403	0	0
GrantKnown_A	415001954	405530809	0	0
IdxKnown_A	415001954	405530809	0	0
IndexIsCorrect_A	415001954	4403	0	0
NoReadyValidNoGrant_A	415001954	0	0	0
Priority_A	415001954	4403	0	0
ReadyAndValidImplyGrant_A	415001954	4403	0	0
ReqAndReadyImplyGrant_A	415001954	4403	0	0
ReqImpliesValid_A	415001954	4403	0	0
ValidKnown_A	415001954	405530809	0	0
gen_data_port_assertion.DataFlow_A	415001954	4403	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	4403	0	0
T135	164947	0	0	0
T137	88035	1467	0	0
T138	0	1471	0	0
T139	0	1465	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
TOTAL		16	16	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	85	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	87	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	89	1	1	100.00
ALWAYS	105	6	6	100.00
CONT_ASSIGN	121	1	1	100.00
CONT_ASSIGN	128	1	1	100.00
CONT_ASSIGN	129	1	1	100.00
CONT_ASSIGN	132	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	2	2
87	2	2
89	2	2
105	1	1
107	1	1
109	1	1
110	1	1
112	1	1
113	1	1
121	1	1
128	1	1
129	1	1
132	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Covered	Percent
Conditions	15	13	86.67
Logical	15	13	86.67
Non-Logical	0	0
Event	0	0

 LINE       107
 EXPRESSION (gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C0] | gen_normal_case.req_tree[gen_normal_case.gen_tree[0].gen_level[0].C1])
             ----------------------------------1----------------------------------   ----------------------------------2----------------------------------

-1-	-2-	Status	Tests
0	0	Covered	T137,T138,T139
0	1	Covered	T137,T138,T139
1	0	Not Covered

 LINE       109
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.idx_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T137,T138,T139
1	Covered	T137,T138,T139

 LINE       110
 EXPRESSION 
 Number  Term
      1  gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel ? gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C1] : gen_normal_case.data_tree[gen_normal_case.gen_tree[0].gen_level[0].C0])

-1-	Status	Tests
0	Covered	T137,T138,T139
1	Covered	T137,T138,T139

 LINE       112
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & ((~gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)))
             ----------------------------------1----------------------------------   -----------------------------2-----------------------------

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T137,T138,T139
1	1	Covered	T137,T138,T139

 LINE       113
 EXPRESSION (gen_normal_case.gnt_tree[gen_normal_case.gen_tree[0].gen_level[0].Pa] & gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel)
             ----------------------------------1----------------------------------   ---------------------------2--------------------------

-1-	-2-	Status	Tests
0	1	Covered	T137,T138,T139
1	0	Covered	T137,T138,T139
1	1	Covered	T137,T138,T139

 LINE       132
 EXPRESSION (valid_o & ready_i)
             ---1---   ---2---

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Covered	T137,T138,T139

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Line No.	Total	Covered	Percent
Branches		4	4	100.00
TERNARY	109	2	2	100.00
TERNARY	110	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv' or '../src/lowrisc_prim_arbiter_0/rtl/prim_arbiter_fixed.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	109	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T137,T138,T139
0	Covered	T137,T138,T139

	LineNo.	Expression
-1-:	110	(gen_normal_case.gen_tree[0].gen_level[0].gen_nodes.sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T137,T138,T139
0	Covered	T137,T138,T139

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_rv_core_ibex.u_dbus_trans.u_sel_region

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	14	14	100.00	13	92.86
Cover properties	0	0		0
Cover sequences	0	0		0
Total	14	14	100.00	13	92.86

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CheckHotOne_A	415001954	405530809	0	0
CheckNGreaterZero_A	942	942	0	0
GntImpliesReady_A	415001954	1038	0	0
GntImpliesValid_A	415001954	1038	0	0
GrantKnown_A	415001954	405530809	0	0
IdxKnown_A	415001954	405530809	0	0
IndexIsCorrect_A	415001954	1038	0	0
NoReadyValidNoGrant_A	415001954	0	0	0
Priority_A	415001954	1038	0	0
ReadyAndValidImplyGrant_A	415001954	1038	0	0
ReqAndReadyImplyGrant_A	415001954	1038	0	0
ReqImpliesValid_A	415001954	1038	0	0
ValidKnown_A	415001954	405530809	0	0
gen_data_port_assertion.DataFlow_A	415001954	1038	0	0

CheckHotOne_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

CheckNGreaterZero_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	942	942	0	0
T1	1	1	0	0
T2	1	1	0	0
T3	1	1	0	0
T4	1	1	0	0
T32	1	1	0	0
T39	1	1	0	0
T49	1	1	0	0
T83	1	1	0	0
T84	1	1	0	0
T85	1	1	0	0

GntImpliesReady_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

GntImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

GrantKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

IdxKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

IndexIsCorrect_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

NoReadyValidNoGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	0	0	0

Priority_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ReadyAndValidImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ReqAndReadyImplyGrant_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ReqImpliesValid_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0

ValidKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	405530809	0	0
T1	217797	217735	0	0
T2	95990	95928	0	0
T3	220929	220827	0	0
T4	627535	627422	0	0
T32	273302	273185	0	0
T39	489610	489555	0	0
T49	156805	156754	0	0
T83	91942	91891	0	0
T84	113996	113938	0	0
T85	371269	371211	0	0

gen_data_port_assertion.DataFlow_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	415001954	1038	0	0
T135	164947	0	0	0
T137	88035	346	0	0
T138	0	346	0	0
T139	0	346	0	0
T275	353409	0	0	0
T276	61901	0	0	0
T277	658960	0	0	0
T278	359515	0	0	0
T279	404486	0	0	0
T280	91361	0	0	0
T281	148108	0	0	0
T282	201259	0	0	0