Unified Coverage Report :: Module Instance :: tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.73	100.00	90.91			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.17	100.00	96.67			100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	100.00	100.00	100.00			100.00	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Module Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.43	100.00	85.71			100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.68	96.99	84.51			93.22	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.22	99.71	97.19			100.00	100.00	u_reg

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_arb	92.06	95.92	81.63			90.70	100.00
u_src_to_dst_req	100.00	100.00	100.00			100.00	100.00

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T391

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_2_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	86702	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	215	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	86702	0	0
T166	88854	766	0	0
T167	85066	791	0	0
T168	46367	286	0	0
T325	584195	6525	0	0
T326	293363	3771	0	0
T327	320364	3630	0	0
T328	80973	752	0	0
T353	705542	5668	0	0
T363	44376	356	0	0
T364	305909	2095	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	215	0	0
T166	88854	2	0	0
T167	85066	2	0	0
T168	46367	1	0	0
T325	584195	16	0	0
T326	293363	9	0	0
T327	320364	8	0	0
T328	80973	2	0	0
T353	705542	14	0	0
T363	44376	1	0	0
T364	305909	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T392,T166

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_3_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	87642	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	219	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	87642	0	0
T166	88854	778	0	0
T167	85066	720	0	0
T168	46367	291	0	0
T325	584195	5440	0	0
T326	293363	2488	0	0
T327	320364	3588	0	0
T328	80973	762	0	0
T353	705542	4614	0	0
T363	44376	335	0	0
T364	305909	3998	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	219	0	0
T166	88854	2	0	0
T167	85066	2	0	0
T168	46367	1	0	0
T325	584195	14	0	0
T326	293363	6	0	0
T327	320364	8	0	0
T328	80973	2	0	0
T353	705542	11	0	0
T363	44376	1	0	0
T364	305909	10	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_4_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	97319	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	241	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	97319	0	0
T166	88854	717	0	0
T167	85066	763	0	0
T168	46367	299	0	0
T325	584195	4257	0	0
T326	293363	4979	0	0
T327	320364	5042	0	0
T328	80973	758	0	0
T353	705542	4474	0	0
T363	44376	319	0	0
T364	305909	396	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	241	0	0
T166	88854	2	0	0
T167	85066	2	0	0
T168	46367	1	0	0
T325	584195	11	0	0
T326	293363	12	0	0
T327	320364	11	0	0
T328	80973	2	0	0
T353	705542	11	0	0
T363	44376	1	0	0
T364	305909	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_5_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	90619	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	227	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	90619	0	0
T166	88854	692	0	0
T167	85066	689	0	0
T168	46367	300	0	0
T325	584195	8980	0	0
T326	293363	728	0	0
T327	320364	3187	0	0
T328	80973	706	0	0
T353	705542	6082	0	0
T363	44376	314	0	0
T364	305909	2119	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	227	0	0
T166	88854	2	0	0
T167	85066	2	0	0
T168	46367	1	0	0
T325	584195	22	0	0
T326	293363	2	0	0
T327	320364	7	0	0
T328	80973	2	0	0
T353	705542	15	0	0
T363	44376	1	0	0
T364	305909	5	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T393,T166

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_6_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	98782	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	248	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	98782	0	0
T166	88854	719	0	0
T167	85066	704	0	0
T168	46367	272	0	0
T325	584195	3704	0	0
T326	293363	260	0	0
T327	320364	2703	0	0
T328	80973	769	0	0
T353	705542	5297	0	0
T363	44376	247	0	0
T364	305909	789	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	248	0	0
T166	88854	2	0	0
T167	85066	2	0	0
T168	46367	1	0	0
T325	584195	10	0	0
T326	293363	1	0	0
T327	320364	6	0	0
T328	80973	2	0	0
T353	705542	13	0	0
T363	44376	1	0	0
T364	305909	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Covered	Percent
Conditions	11	10	90.91
Logical	11	10	90.91
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T372,T166

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T168,T166,T157
1	1	Covered	T168,T166,T157

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Unreachable
1	1	Unreachable

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T168,T166,T157
0	0	1	Covered	T168,T166,T157
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_detector_cnt_th_7_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	79264	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	198	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	79264	0	0
T166	88854	754	0	0
T167	85066	750	0	0
T168	46367	270	0	0
T325	584195	2753	0	0
T327	320364	1687	0	0
T328	80973	736	0	0
T353	705542	1176	0	0
T363	44376	344	0	0
T364	305909	2592	0	0
T394	50784	443	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	198	0	0
T166	88854	2	0	0
T167	85066	2	0	0
T168	46367	1	0	0
T325	584195	7	0	0
T327	320364	4	0	0
T328	80973	2	0	0
T353	705542	3	0	0
T363	44376	1	0	0
T364	305909	6	0	0
T394	50784	1	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0

Line Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
TOTAL		22	22	100.00
CONT_ASSIGN	54	1	1	100.00
ALWAYS	60	6	6	100.00
CONT_ASSIGN	74	1	1	100.00
CONT_ASSIGN	98	1	1	100.00
ALWAYS	104	9	9	100.00
CONT_ASSIGN	139	1	1	100.00
CONT_ASSIGN	144	1	1	100.00
CONT_ASSIGN	145	1	1	100.00
CONT_ASSIGN	187	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
54	1	1
60	1	1
61	1	1
62	1	1
63	1	1
64	1	1
65	1	1
			MISSING_ELSE
74	1	1
98	1	1
104	1	1
105	1	1
106	1	1
107	1	1
112	1	1
113	1	1
114	1	1
123	1	1
124	1	1
			MISSING_ELSE
139	1	1
144	1	1
145	1	1
187	1	1

---

Cond Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Covered	Percent
Conditions	14	12	85.71
Logical	14	12	85.71
Non-Logical	0	0
Event	0	0

 LINE       54
 EXPRESSION (src_we_i | src_re_i)
             ----1---   ----2---

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Unreachable
1	0	Covered	T16,T17,T18

 LINE       98
 EXPRESSION (src_busy_q & ((!src_ack)))
             -----1----   ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       114
 EXPRESSION ((src_busy_q && src_ack) || (src_update && ((!busy))))
             -----------1-----------    ------------2------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T16,T17,T40
1	0	Covered	T16,T17,T18

 LINE       114
 SUB-EXPRESSION (src_busy_q && src_ack)
                 -----1----    ---2---

-1-	-2-	Status	Tests
0	1	Not Covered
1	0	Covered	T16,T17,T18
1	1	Covered	T16,T17,T18

 LINE       114
 SUB-EXPRESSION (src_update && ((!busy)))
                 -----1----    ----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Not Covered
1	1	Covered	T16,T17,T40

---

Branch Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Line No.	Total	Covered	Percent
Branches		8	8	100.00
IF	60	4	4	100.00
IF	104	4	4	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv' or '../src/lowrisc_prim_subreg_0/rtl/prim_reg_cdc.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	60	if ((!rst_src_ni))
-2-:	62	if (src_req)
-3-:	64	if (src_ack)

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T17,T18
0	0	1	Covered	T16,T17,T18
0	0	0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	104	if ((!rst_src_ni))
-2-:	107	if (src_req)
-3-:	114	if (((src_busy_q && src_ack) || (src_update && (!busy))))

Branches:

-1-	-2-	-3-	Status	Tests
1	-	-	Covered	T1,T2,T3
0	1	-	Covered	T16,T17,T18
0	0	1	Covered	T16,T17,T40
0	0	0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.top_earlgrey.u_pinmux_aon.u_reg.u_wkup_cause_cdc

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	4	4	100.00	4	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	4	4	100.00	4	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
BusySrcReqChk_A	120917485	111970	0	0
DstReqKnown_A	1529871	1334054	0	0
SrcAckBusyChk_A	120917485	243	0	0
SrcBusyKnown_A	120917485	120175384	0	0

BusySrcReqChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	111970	0	0
T6	231342	0	0	0
T16	46313	780	0	0
T17	0	904	0	0
T18	0	764	0	0
T26	0	1047	0	0
T43	0	1439	0	0
T44	0	1600	0	0
T45	0	1789	0	0
T48	0	1507	0	0
T56	11652	0	0	0
T59	193799	0	0	0
T63	56462	0	0	0
T65	111198	0	0	0
T98	0	743	0	0
T99	69277	0	0	0
T100	34958	0	0	0
T101	68648	0	0	0
T102	93874	0	0	0
T362	0	735	0	0

DstReqKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1529871	1334054	0	0
T1	682	617	0	0
T2	424	260	0	0
T3	740	577	0	0
T4	1542	1319	0	0
T32	892	727	0	0
T39	1197	1035	0	0
T49	586	425	0	0
T83	406	244	0	0
T84	490	326	0	0
T85	1013	849	0	0

SrcAckBusyChk_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	243	0	0
T6	231342	0	0	0
T16	46313	2	0	0
T17	0	2	0	0
T18	0	2	0	0
T26	0	3	0	0
T43	0	4	0	0
T44	0	4	0	0
T45	0	5	0	0
T48	0	4	0	0
T56	11652	0	0	0
T59	193799	0	0	0
T63	56462	0	0	0
T65	111198	0	0	0
T98	0	2	0	0
T99	69277	0	0	0
T100	34958	0	0	0
T101	68648	0	0	0
T102	93874	0	0	0
T362	0	2	0	0

SrcBusyKnown_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	120917485	120175384	0	0
T1	52923	52641	0	0
T2	23905	23405	0	0
T3	54388	53774	0	0
T4	151781	150975	0	0
T32	66854	66332	0	0
T39	118418	117884	0	0
T49	42386	41891	0	0
T83	22960	22436	0	0
T84	28144	27727	0	0
T85	89876	89477	0	0