| T277 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3650879190 |
|
|
Mar 17 04:03:38 PM PDT 24 |
Mar 17 04:31:46 PM PDT 24 |
8293602095 ps |
| T278 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.3805152543 |
|
|
Mar 17 03:52:21 PM PDT 24 |
Mar 17 04:05:36 PM PDT 24 |
8850208687 ps |
| T279 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.1521723678 |
|
|
Mar 17 03:51:15 PM PDT 24 |
Mar 17 04:10:27 PM PDT 24 |
7484621678 ps |
| T280 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1191246431 |
|
|
Mar 17 04:01:08 PM PDT 24 |
Mar 17 04:05:20 PM PDT 24 |
2911192920 ps |
| T281 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1536144229 |
|
|
Mar 17 04:16:52 PM PDT 24 |
Mar 17 04:21:53 PM PDT 24 |
3014842240 ps |
| T282 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.658184304 |
|
|
Mar 17 03:52:04 PM PDT 24 |
Mar 17 04:03:55 PM PDT 24 |
4231920620 ps |
| T136 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.932636161 |
|
|
Mar 17 03:46:51 PM PDT 24 |
Mar 17 03:56:18 PM PDT 24 |
4756542072 ps |
| T942 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.2608180193 |
|
|
Mar 17 03:56:09 PM PDT 24 |
Mar 17 04:14:03 PM PDT 24 |
7941783892 ps |
| T943 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1005564704 |
|
|
Mar 17 03:50:36 PM PDT 24 |
Mar 17 04:13:40 PM PDT 24 |
5351447660 ps |
| T944 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.159402856 |
|
|
Mar 17 03:54:04 PM PDT 24 |
Mar 17 03:57:35 PM PDT 24 |
2861762088 ps |
| T945 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.635263414 |
|
|
Mar 17 03:48:18 PM PDT 24 |
Mar 17 04:05:19 PM PDT 24 |
5576891128 ps |
| T182 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.4280455499 |
|
|
Mar 17 04:02:31 PM PDT 24 |
Mar 17 04:06:03 PM PDT 24 |
2381595016 ps |
| T946 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.2350262295 |
|
|
Mar 17 03:54:17 PM PDT 24 |
Mar 17 04:20:30 PM PDT 24 |
6835949728 ps |
| T335 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2967819359 |
|
|
Mar 17 03:54:46 PM PDT 24 |
Mar 17 04:29:10 PM PDT 24 |
7920700048 ps |
| T256 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.4232307482 |
|
|
Mar 17 03:51:29 PM PDT 24 |
Mar 17 04:00:44 PM PDT 24 |
4027462408 ps |
| T720 |
/workspace/coverage/default/1.chip_sw_sleep_pwm_pulses.579833625 |
|
|
Mar 17 03:55:05 PM PDT 24 |
Mar 17 04:19:37 PM PDT 24 |
7937139320 ps |
| T947 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.813487630 |
|
|
Mar 17 03:58:29 PM PDT 24 |
Mar 17 04:07:50 PM PDT 24 |
4025017866 ps |
| T948 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.453368118 |
|
|
Mar 17 04:02:13 PM PDT 24 |
Mar 17 04:13:11 PM PDT 24 |
4936095400 ps |
| T949 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.114869707 |
|
|
Mar 17 03:47:03 PM PDT 24 |
Mar 17 04:08:28 PM PDT 24 |
10179433594 ps |
| T198 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.1918005909 |
|
|
Mar 17 03:46:10 PM PDT 24 |
Mar 17 05:07:06 PM PDT 24 |
48347666206 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.39063906 |
|
|
Mar 17 03:49:13 PM PDT 24 |
Mar 17 04:18:27 PM PDT 24 |
11670459526 ps |
| T316 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2206690648 |
|
|
Mar 17 04:15:32 PM PDT 24 |
Mar 17 04:23:56 PM PDT 24 |
6020613212 ps |
| T951 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.3157443473 |
|
|
Mar 17 03:50:07 PM PDT 24 |
Mar 17 03:54:20 PM PDT 24 |
2572083170 ps |
| T952 |
/workspace/coverage/default/1.chip_sw_otbn_randomness.2614398980 |
|
|
Mar 17 03:53:11 PM PDT 24 |
Mar 17 04:10:54 PM PDT 24 |
6104413532 ps |
| T175 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_in_irq.2754033760 |
|
|
Mar 17 03:52:22 PM PDT 24 |
Mar 17 04:02:09 PM PDT 24 |
4710382578 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.3428281553 |
|
|
Mar 17 03:49:11 PM PDT 24 |
Mar 17 04:02:38 PM PDT 24 |
6224548602 ps |
| T245 |
/workspace/coverage/default/5.chip_sw_data_integrity_escalation.1297189556 |
|
|
Mar 17 04:09:43 PM PDT 24 |
Mar 17 04:20:57 PM PDT 24 |
5865501320 ps |
| T248 |
/workspace/coverage/default/1.rom_e2e_smoke.1079222642 |
|
|
Mar 17 04:00:00 PM PDT 24 |
Mar 17 04:26:00 PM PDT 24 |
8847674976 ps |
| T249 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3416587456 |
|
|
Mar 17 03:52:36 PM PDT 24 |
Mar 17 04:00:04 PM PDT 24 |
3812119758 ps |
| T250 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.2278265822 |
|
|
Mar 17 04:04:24 PM PDT 24 |
Mar 17 04:11:21 PM PDT 24 |
3624780944 ps |
| T251 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2089564356 |
|
|
Mar 17 04:14:40 PM PDT 24 |
Mar 17 04:25:12 PM PDT 24 |
5952014610 ps |
| T189 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq.4177127308 |
|
|
Mar 17 04:08:43 PM PDT 24 |
Mar 17 05:03:05 PM PDT 24 |
23203609647 ps |
| T252 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.1709021886 |
|
|
Mar 17 03:50:23 PM PDT 24 |
Mar 17 03:54:08 PM PDT 24 |
2515090776 ps |
| T253 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.2332969963 |
|
|
Mar 17 03:52:56 PM PDT 24 |
Mar 17 04:02:52 PM PDT 24 |
5354820608 ps |
| T254 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.4180772958 |
|
|
Mar 17 04:04:35 PM PDT 24 |
Mar 17 04:08:18 PM PDT 24 |
2182483550 ps |
| T255 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.203420154 |
|
|
Mar 17 03:57:30 PM PDT 24 |
Mar 17 04:46:33 PM PDT 24 |
12646185000 ps |
| T954 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3335164400 |
|
|
Mar 17 03:51:36 PM PDT 24 |
Mar 17 03:57:44 PM PDT 24 |
3152129084 ps |
| T955 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.1752370928 |
|
|
Mar 17 03:55:55 PM PDT 24 |
Mar 17 04:32:28 PM PDT 24 |
8460550468 ps |
| T197 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.3329341003 |
|
|
Mar 17 04:11:36 PM PDT 24 |
Mar 17 04:21:32 PM PDT 24 |
5615391151 ps |
| T956 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.3523271654 |
|
|
Mar 17 04:05:48 PM PDT 24 |
Mar 17 04:12:51 PM PDT 24 |
4458684652 ps |
| T154 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.1527549345 |
|
|
Mar 17 04:05:35 PM PDT 24 |
Mar 17 04:18:26 PM PDT 24 |
4771951596 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.1233769156 |
|
|
Mar 17 03:47:48 PM PDT 24 |
Mar 17 03:59:10 PM PDT 24 |
5217093050 ps |
| T957 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_rma.1394122207 |
|
|
Mar 17 03:56:49 PM PDT 24 |
Mar 17 04:44:44 PM PDT 24 |
11976940175 ps |
| T118 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.2465595008 |
|
|
Mar 17 04:15:38 PM PDT 24 |
Mar 17 04:24:18 PM PDT 24 |
5997026840 ps |
| T958 |
/workspace/coverage/default/0.chip_sw_aes_entropy.2082362476 |
|
|
Mar 17 03:49:15 PM PDT 24 |
Mar 17 03:53:21 PM PDT 24 |
2698380050 ps |
| T300 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx2.1289462370 |
|
|
Mar 17 04:11:36 PM PDT 24 |
Mar 17 04:25:22 PM PDT 24 |
5706331092 ps |
| T334 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_test_unlocked0.4056731414 |
|
|
Mar 17 03:56:05 PM PDT 24 |
Mar 17 04:41:28 PM PDT 24 |
9398161740 ps |
| T336 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2805057007 |
|
|
Mar 17 04:07:53 PM PDT 24 |
Mar 17 04:11:26 PM PDT 24 |
2216210700 ps |
| T194 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.824228725 |
|
|
Mar 17 04:12:59 PM PDT 24 |
Mar 17 04:22:49 PM PDT 24 |
5818145288 ps |
| T176 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.4248989 |
|
|
Mar 17 04:04:02 PM PDT 24 |
Mar 17 04:15:48 PM PDT 24 |
4967571570 ps |
| T959 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.2172583156 |
|
|
Mar 17 04:00:49 PM PDT 24 |
Mar 17 04:54:49 PM PDT 24 |
12334719952 ps |
| T171 |
/workspace/coverage/default/0.chip_sw_power_idle_load.1719493311 |
|
|
Mar 17 03:50:32 PM PDT 24 |
Mar 17 04:02:41 PM PDT 24 |
4289767928 ps |
| T960 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.225511137 |
|
|
Mar 17 03:52:41 PM PDT 24 |
Mar 17 03:59:57 PM PDT 24 |
4068474780 ps |
| T961 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.1050716240 |
|
|
Mar 17 03:55:27 PM PDT 24 |
Mar 17 04:27:59 PM PDT 24 |
8700143952 ps |
| T690 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1534583378 |
|
|
Mar 17 04:07:19 PM PDT 24 |
Mar 17 04:21:10 PM PDT 24 |
7011041256 ps |
| T962 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.1604727904 |
|
|
Mar 17 03:57:25 PM PDT 24 |
Mar 17 04:28:33 PM PDT 24 |
8632914991 ps |
| T963 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx.3519705077 |
|
|
Mar 17 04:10:39 PM PDT 24 |
Mar 17 04:24:27 PM PDT 24 |
5623425028 ps |
| T708 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.297163857 |
|
|
Mar 17 03:55:59 PM PDT 24 |
Mar 17 04:00:20 PM PDT 24 |
3249170880 ps |
| T106 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.386540852 |
|
|
Mar 17 03:46:36 PM PDT 24 |
Mar 17 06:39:48 PM PDT 24 |
58730907230 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.3826093007 |
|
|
Mar 17 04:06:22 PM PDT 24 |
Mar 17 04:16:26 PM PDT 24 |
5093663544 ps |
| T965 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2236160846 |
|
|
Mar 17 04:04:41 PM PDT 24 |
Mar 17 04:35:43 PM PDT 24 |
8984402696 ps |
| T688 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1658832074 |
|
|
Mar 17 04:01:24 PM PDT 24 |
Mar 17 04:12:24 PM PDT 24 |
5241388138 ps |
| T74 |
/workspace/coverage/default/2.chip_jtag_csr_rw.1854098472 |
|
|
Mar 17 03:59:20 PM PDT 24 |
Mar 17 04:36:18 PM PDT 24 |
20865805240 ps |
| T966 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.2239505945 |
|
|
Mar 17 04:01:03 PM PDT 24 |
Mar 17 04:50:34 PM PDT 24 |
24247319990 ps |
| T397 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.636596671 |
|
|
Mar 17 04:09:52 PM PDT 24 |
Mar 17 04:20:35 PM PDT 24 |
4823566130 ps |
| T967 |
/workspace/coverage/default/1.chip_tap_straps_prod.741583462 |
|
|
Mar 17 03:59:26 PM PDT 24 |
Mar 17 04:02:51 PM PDT 24 |
3169513554 ps |
| T968 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.1988828442 |
|
|
Mar 17 04:01:52 PM PDT 24 |
Mar 17 04:04:02 PM PDT 24 |
2946383379 ps |
| T181 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.3576990569 |
|
|
Mar 17 03:45:56 PM PDT 24 |
Mar 17 04:02:13 PM PDT 24 |
4783925750 ps |
| T969 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.189519876 |
|
|
Mar 17 03:55:32 PM PDT 24 |
Mar 17 04:29:21 PM PDT 24 |
8810928562 ps |
| T970 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3367046976 |
|
|
Mar 17 03:55:58 PM PDT 24 |
Mar 17 04:07:00 PM PDT 24 |
7176129550 ps |
| T761 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1626037679 |
|
|
Mar 17 04:17:37 PM PDT 24 |
Mar 17 04:28:04 PM PDT 24 |
5639062024 ps |
| T971 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.3487869160 |
|
|
Mar 17 03:54:25 PM PDT 24 |
Mar 17 04:25:59 PM PDT 24 |
7265914016 ps |
| T763 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.2092112902 |
|
|
Mar 17 04:12:21 PM PDT 24 |
Mar 17 04:26:59 PM PDT 24 |
5737862800 ps |
| T732 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.4144282545 |
|
|
Mar 17 03:53:31 PM PDT 24 |
Mar 17 03:58:58 PM PDT 24 |
2425178680 ps |
| T972 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.2800741187 |
|
|
Mar 17 04:10:48 PM PDT 24 |
Mar 17 04:19:37 PM PDT 24 |
5657333220 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.37822980 |
|
|
Mar 17 03:45:35 PM PDT 24 |
Mar 17 03:48:39 PM PDT 24 |
2708525673 ps |
| T974 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.2777858899 |
|
|
Mar 17 04:08:07 PM PDT 24 |
Mar 17 04:11:53 PM PDT 24 |
2624766153 ps |
| T820 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.57208332 |
|
|
Mar 17 04:14:01 PM PDT 24 |
Mar 17 04:19:46 PM PDT 24 |
3432871050 ps |
| T975 |
/workspace/coverage/default/1.chip_tap_straps_dev.788344558 |
|
|
Mar 17 03:56:54 PM PDT 24 |
Mar 17 04:02:51 PM PDT 24 |
4003536820 ps |
| T976 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.3772479731 |
|
|
Mar 17 03:46:57 PM PDT 24 |
Mar 17 04:47:05 PM PDT 24 |
18854085293 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.1940056106 |
|
|
Mar 17 04:03:00 PM PDT 24 |
Mar 17 04:07:37 PM PDT 24 |
2988183865 ps |
| T977 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1452084660 |
|
|
Mar 17 03:52:27 PM PDT 24 |
Mar 17 04:02:49 PM PDT 24 |
3931356696 ps |
| T764 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.2605701299 |
|
|
Mar 17 04:13:44 PM PDT 24 |
Mar 17 04:21:14 PM PDT 24 |
3435444200 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_prod.155821737 |
|
|
Mar 17 04:02:49 PM PDT 24 |
Mar 17 04:25:05 PM PDT 24 |
7063752166 ps |
| T257 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.2803975499 |
|
|
Mar 17 03:47:52 PM PDT 24 |
Mar 17 03:57:53 PM PDT 24 |
4252224687 ps |
| T759 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.642101885 |
|
|
Mar 17 04:17:06 PM PDT 24 |
Mar 17 04:24:12 PM PDT 24 |
5587192884 ps |
| T675 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1117972745 |
|
|
Mar 17 04:15:33 PM PDT 24 |
Mar 17 04:26:16 PM PDT 24 |
5638594640 ps |
| T979 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.3328947852 |
|
|
Mar 17 03:47:50 PM PDT 24 |
Mar 17 03:53:51 PM PDT 24 |
3158277760 ps |
| T980 |
/workspace/coverage/default/4.chip_tap_straps_prod.2834610579 |
|
|
Mar 17 04:10:05 PM PDT 24 |
Mar 17 04:12:00 PM PDT 24 |
2328344330 ps |
| T128 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_dev.3221884786 |
|
|
Mar 17 04:02:56 PM PDT 24 |
Mar 17 05:23:29 PM PDT 24 |
47190402824 ps |
| T425 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.3871318712 |
|
|
Mar 17 04:02:05 PM PDT 24 |
Mar 17 04:09:20 PM PDT 24 |
5117440216 ps |
| T981 |
/workspace/coverage/default/2.chip_sw_kmac_mode_cshake.3006874425 |
|
|
Mar 17 04:04:56 PM PDT 24 |
Mar 17 04:09:04 PM PDT 24 |
2819859666 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.372294953 |
|
|
Mar 17 03:58:45 PM PDT 24 |
Mar 17 04:18:20 PM PDT 24 |
5236664600 ps |
| T807 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.3009702042 |
|
|
Mar 17 04:12:17 PM PDT 24 |
Mar 17 04:21:53 PM PDT 24 |
5021214570 ps |
| T66 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.104651915 |
|
|
Mar 17 03:47:19 PM PDT 24 |
Mar 17 03:51:57 PM PDT 24 |
2900484072 ps |
| T293 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4007570069 |
|
|
Mar 17 03:57:57 PM PDT 24 |
Mar 17 04:11:19 PM PDT 24 |
5131871099 ps |
| T983 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.1532243076 |
|
|
Mar 17 03:57:28 PM PDT 24 |
Mar 17 04:29:47 PM PDT 24 |
8813394056 ps |
| T122 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.717527333 |
|
|
Mar 17 03:50:13 PM PDT 24 |
Mar 17 03:53:26 PM PDT 24 |
2593134681 ps |
| T231 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.3976596165 |
|
|
Mar 17 03:56:13 PM PDT 24 |
Mar 17 04:00:25 PM PDT 24 |
2848947910 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2878195498 |
|
|
Mar 17 03:48:10 PM PDT 24 |
Mar 17 04:44:57 PM PDT 24 |
17332399240 ps |
| T985 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.3553939216 |
|
|
Mar 17 04:04:18 PM PDT 24 |
Mar 17 04:09:23 PM PDT 24 |
2947258294 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.3086878771 |
|
|
Mar 17 03:52:18 PM PDT 24 |
Mar 17 03:56:51 PM PDT 24 |
3032747350 ps |
| T986 |
/workspace/coverage/default/2.chip_tap_straps_rma.4178751287 |
|
|
Mar 17 04:07:10 PM PDT 24 |
Mar 17 04:22:53 PM PDT 24 |
10951061400 ps |
| T758 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.3176573635 |
|
|
Mar 17 03:59:17 PM PDT 24 |
Mar 17 04:12:03 PM PDT 24 |
5787664520 ps |
| T987 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.3149080043 |
|
|
Mar 17 03:49:52 PM PDT 24 |
Mar 17 04:01:04 PM PDT 24 |
5027872600 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2791856219 |
|
|
Mar 17 04:09:27 PM PDT 24 |
Mar 17 04:13:01 PM PDT 24 |
2820759770 ps |
| T119 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.2898851075 |
|
|
Mar 17 04:12:26 PM PDT 24 |
Mar 17 04:21:25 PM PDT 24 |
5293251782 ps |
| T301 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2132044072 |
|
|
Mar 17 03:54:14 PM PDT 24 |
Mar 17 04:11:15 PM PDT 24 |
5275019018 ps |
| T989 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.50326846 |
|
|
Mar 17 03:57:16 PM PDT 24 |
Mar 17 04:03:29 PM PDT 24 |
3508630336 ps |
| T210 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3414630455 |
|
|
Mar 17 03:47:43 PM PDT 24 |
Mar 17 04:41:54 PM PDT 24 |
11242462702 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.1745708719 |
|
|
Mar 17 03:57:56 PM PDT 24 |
Mar 17 04:19:55 PM PDT 24 |
12192036408 ps |
| T991 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_kmac_trans.1056231172 |
|
|
Mar 17 04:07:36 PM PDT 24 |
Mar 17 04:16:55 PM PDT 24 |
4801043216 ps |
| T398 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.273546116 |
|
|
Mar 17 03:54:59 PM PDT 24 |
Mar 17 03:57:56 PM PDT 24 |
2656836280 ps |
| T992 |
/workspace/coverage/default/0.rom_raw_unlock.2249216225 |
|
|
Mar 17 03:51:08 PM PDT 24 |
Mar 17 04:29:43 PM PDT 24 |
15210785966 ps |
| T993 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3462712014 |
|
|
Mar 17 04:11:21 PM PDT 24 |
Mar 17 04:26:59 PM PDT 24 |
11704960636 ps |
| T733 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ulp_z3_wakeup.991914889 |
|
|
Mar 17 04:04:06 PM PDT 24 |
Mar 17 04:12:42 PM PDT 24 |
4761658480 ps |
| T994 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.1699353808 |
|
|
Mar 17 04:08:45 PM PDT 24 |
Mar 17 04:13:23 PM PDT 24 |
3405522730 ps |
| T790 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2088273806 |
|
|
Mar 17 04:14:36 PM PDT 24 |
Mar 17 04:23:22 PM PDT 24 |
5699665736 ps |
| T750 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.427731830 |
|
|
Mar 17 04:17:03 PM PDT 24 |
Mar 17 04:27:19 PM PDT 24 |
6243006056 ps |
| T177 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1476346863 |
|
|
Mar 17 03:47:07 PM PDT 24 |
Mar 17 03:56:34 PM PDT 24 |
4589136403 ps |
| T823 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.3801872220 |
|
|
Mar 17 04:16:11 PM PDT 24 |
Mar 17 04:22:20 PM PDT 24 |
3195725608 ps |
| T698 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.2988633401 |
|
|
Mar 17 04:14:21 PM PDT 24 |
Mar 17 04:22:37 PM PDT 24 |
3514339816 ps |
| T754 |
/workspace/coverage/default/79.chip_sw_all_escalation_resets.2317660536 |
|
|
Mar 17 04:18:41 PM PDT 24 |
Mar 17 04:26:08 PM PDT 24 |
4648318216 ps |
| T162 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.2494185149 |
|
|
Mar 17 03:46:46 PM PDT 24 |
Mar 17 03:55:34 PM PDT 24 |
7729511110 ps |
| T995 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2216019908 |
|
|
Mar 17 04:09:37 PM PDT 24 |
Mar 17 04:19:27 PM PDT 24 |
5267497842 ps |
| T155 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.2831671233 |
|
|
Mar 17 03:53:58 PM PDT 24 |
Mar 17 04:03:28 PM PDT 24 |
6085158840 ps |
| T217 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_lc_rw_en.2622450678 |
|
|
Mar 17 04:03:30 PM PDT 24 |
Mar 17 04:12:19 PM PDT 24 |
3932388671 ps |
| T216 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2956519667 |
|
|
Mar 17 03:47:54 PM PDT 24 |
Mar 17 04:25:59 PM PDT 24 |
25078451342 ps |
| T140 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.233982002 |
|
|
Mar 17 03:59:33 PM PDT 24 |
Mar 17 04:31:17 PM PDT 24 |
10812086688 ps |
| T195 |
/workspace/coverage/default/65.chip_sw_all_escalation_resets.1055922324 |
|
|
Mar 17 04:17:32 PM PDT 24 |
Mar 17 04:26:38 PM PDT 24 |
5266081552 ps |
| T806 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.2727219722 |
|
|
Mar 17 04:17:07 PM PDT 24 |
Mar 17 04:22:29 PM PDT 24 |
3078702704 ps |
| T678 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.2152104180 |
|
|
Mar 17 04:08:05 PM PDT 24 |
Mar 17 04:19:25 PM PDT 24 |
4593579346 ps |
| T689 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.2115682893 |
|
|
Mar 17 03:48:34 PM PDT 24 |
Mar 17 03:58:52 PM PDT 24 |
5328812002 ps |
| T996 |
/workspace/coverage/default/1.chip_sw_example_rom.1597625246 |
|
|
Mar 17 03:50:11 PM PDT 24 |
Mar 17 03:52:34 PM PDT 24 |
2867077900 ps |
| T401 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.3450196593 |
|
|
Mar 17 04:14:36 PM PDT 24 |
Mar 17 04:21:02 PM PDT 24 |
3795990206 ps |
| T752 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.3022111759 |
|
|
Mar 17 03:53:02 PM PDT 24 |
Mar 17 04:04:40 PM PDT 24 |
5654869844 ps |
| T997 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3665763723 |
|
|
Mar 17 03:54:02 PM PDT 24 |
Mar 17 04:38:49 PM PDT 24 |
9901298050 ps |
| T753 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.2803875504 |
|
|
Mar 17 04:16:14 PM PDT 24 |
Mar 17 04:22:53 PM PDT 24 |
4128311000 ps |
| T998 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.2530296964 |
|
|
Mar 17 03:58:24 PM PDT 24 |
Mar 17 04:03:18 PM PDT 24 |
2852778944 ps |
| T258 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1154222167 |
|
|
Mar 17 04:08:14 PM PDT 24 |
Mar 17 04:19:45 PM PDT 24 |
5555032140 ps |
| T218 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.3549207097 |
|
|
Mar 17 03:51:19 PM PDT 24 |
Mar 17 05:15:45 PM PDT 24 |
46008444380 ps |
| T82 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.554779374 |
|
|
Mar 17 03:53:02 PM PDT 24 |
Mar 17 04:16:28 PM PDT 24 |
12790794204 ps |
| T199 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.1599495647 |
|
|
Mar 17 04:17:39 PM PDT 24 |
Mar 17 04:25:14 PM PDT 24 |
4046208952 ps |
| T999 |
/workspace/coverage/default/0.chip_sw_edn_kat.1050413091 |
|
|
Mar 17 03:49:05 PM PDT 24 |
Mar 17 03:59:25 PM PDT 24 |
3196457536 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_aes_idle.3052827974 |
|
|
Mar 17 03:53:51 PM PDT 24 |
Mar 17 03:56:39 PM PDT 24 |
2318560720 ps |
| T75 |
/workspace/coverage/default/2.chip_jtag_mem_access.3497063286 |
|
|
Mar 17 03:59:23 PM PDT 24 |
Mar 17 04:26:13 PM PDT 24 |
13702562100 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.1408277782 |
|
|
Mar 17 04:05:28 PM PDT 24 |
Mar 17 04:10:11 PM PDT 24 |
3065005348 ps |
| T27 |
/workspace/coverage/default/1.chip_sw_gpio.3699915877 |
|
|
Mar 17 03:51:08 PM PDT 24 |
Mar 17 03:58:15 PM PDT 24 |
4445857768 ps |
| T21 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_ec_rst_l.4003335441 |
|
|
Mar 17 04:04:18 PM PDT 24 |
Mar 17 04:53:32 PM PDT 24 |
20373396600 ps |
| T1002 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.1919552761 |
|
|
Mar 17 03:55:16 PM PDT 24 |
Mar 17 04:26:11 PM PDT 24 |
8845077160 ps |
| T822 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.453653642 |
|
|
Mar 17 04:12:18 PM PDT 24 |
Mar 17 04:24:47 PM PDT 24 |
4994808400 ps |
| T1003 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.3252753543 |
|
|
Mar 17 03:56:44 PM PDT 24 |
Mar 17 04:06:52 PM PDT 24 |
3748520950 ps |
| T200 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3921910744 |
|
|
Mar 17 03:48:48 PM PDT 24 |
Mar 17 04:20:19 PM PDT 24 |
8899327672 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.1828758514 |
|
|
Mar 17 03:52:49 PM PDT 24 |
Mar 17 06:46:14 PM PDT 24 |
57844510726 ps |
| T1004 |
/workspace/coverage/default/0.chip_sw_example_rom.64796037 |
|
|
Mar 17 03:45:45 PM PDT 24 |
Mar 17 03:47:50 PM PDT 24 |
1724844400 ps |
| T815 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.1711637549 |
|
|
Mar 17 04:17:06 PM PDT 24 |
Mar 17 04:27:04 PM PDT 24 |
5506450856 ps |
| T123 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.4235142961 |
|
|
Mar 17 03:53:30 PM PDT 24 |
Mar 17 03:55:30 PM PDT 24 |
2108107791 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.1733221813 |
|
|
Mar 17 03:46:44 PM PDT 24 |
Mar 17 04:36:30 PM PDT 24 |
12068236088 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3762395837 |
|
|
Mar 17 03:51:23 PM PDT 24 |
Mar 17 03:55:56 PM PDT 24 |
2852243556 ps |
| T749 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1731625167 |
|
|
Mar 17 04:13:16 PM PDT 24 |
Mar 17 04:18:54 PM PDT 24 |
3143413256 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.636978769 |
|
|
Mar 17 04:09:07 PM PDT 24 |
Mar 17 04:15:53 PM PDT 24 |
3752148700 ps |
| T1007 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3470276330 |
|
|
Mar 17 04:07:38 PM PDT 24 |
Mar 17 04:16:59 PM PDT 24 |
6109142920 ps |
| T1008 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_bootstrap.961359232 |
|
|
Mar 17 03:52:13 PM PDT 24 |
Mar 17 07:29:30 PM PDT 24 |
78825839308 ps |
| T1009 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2343976649 |
|
|
Mar 17 03:47:16 PM PDT 24 |
Mar 17 04:36:33 PM PDT 24 |
34992065800 ps |
| T1010 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.1330363472 |
|
|
Mar 17 04:13:03 PM PDT 24 |
Mar 17 04:18:46 PM PDT 24 |
3810331680 ps |
| T747 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.451889072 |
|
|
Mar 17 04:11:55 PM PDT 24 |
Mar 17 04:17:18 PM PDT 24 |
3085794968 ps |
| T1011 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.2757215134 |
|
|
Mar 17 04:06:37 PM PDT 24 |
Mar 17 04:14:18 PM PDT 24 |
3782182344 ps |
| T1012 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.2127322718 |
|
|
Mar 17 04:11:48 PM PDT 24 |
Mar 17 04:26:09 PM PDT 24 |
11700766584 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.285214060 |
|
|
Mar 17 04:01:22 PM PDT 24 |
Mar 17 04:08:31 PM PDT 24 |
3177252504 ps |
| T43 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.1313174160 |
|
|
Mar 17 04:08:30 PM PDT 24 |
Mar 17 04:34:52 PM PDT 24 |
23132037976 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.1737606778 |
|
|
Mar 17 03:48:15 PM PDT 24 |
Mar 17 04:07:30 PM PDT 24 |
6196108484 ps |
| T402 |
/workspace/coverage/default/11.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174552412 |
|
|
Mar 17 04:11:39 PM PDT 24 |
Mar 17 04:16:44 PM PDT 24 |
3748171460 ps |
| T825 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.1357507837 |
|
|
Mar 17 04:13:14 PM PDT 24 |
Mar 17 04:25:42 PM PDT 24 |
5146023880 ps |
| T1015 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2758988728 |
|
|
Mar 17 03:56:39 PM PDT 24 |
Mar 17 04:05:50 PM PDT 24 |
4063601048 ps |
| T767 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.3862083213 |
|
|
Mar 17 03:47:11 PM PDT 24 |
Mar 17 03:59:18 PM PDT 24 |
5523297972 ps |
| T816 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.676941567 |
|
|
Mar 17 04:15:26 PM PDT 24 |
Mar 17 04:25:27 PM PDT 24 |
5237951192 ps |
| T297 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.3754028267 |
|
|
Mar 17 03:46:24 PM PDT 24 |
Mar 17 04:16:29 PM PDT 24 |
7846023190 ps |
| T1016 |
/workspace/coverage/default/0.chip_sw_plic_sw_irq.2313555727 |
|
|
Mar 17 03:50:48 PM PDT 24 |
Mar 17 03:57:03 PM PDT 24 |
2665386616 ps |
| T8 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.1586894811 |
|
|
Mar 17 03:46:38 PM PDT 24 |
Mar 17 03:51:53 PM PDT 24 |
3313500890 ps |
| T1017 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_idx1.4080618729 |
|
|
Mar 17 04:10:29 PM PDT 24 |
Mar 17 04:22:52 PM PDT 24 |
5903212241 ps |
| T1018 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.3875345574 |
|
|
Mar 17 04:10:38 PM PDT 24 |
Mar 17 04:25:30 PM PDT 24 |
11340021508 ps |
| T756 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.4102282246 |
|
|
Mar 17 03:46:43 PM PDT 24 |
Mar 17 03:51:48 PM PDT 24 |
3399209735 ps |
| T782 |
/workspace/coverage/default/7.chip_sw_all_escalation_resets.3521317112 |
|
|
Mar 17 04:11:36 PM PDT 24 |
Mar 17 04:22:57 PM PDT 24 |
6302960556 ps |
| T1019 |
/workspace/coverage/default/1.rom_keymgr_functest.2375647732 |
|
|
Mar 17 04:01:34 PM PDT 24 |
Mar 17 04:11:11 PM PDT 24 |
4095175980 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1092773446 |
|
|
Mar 17 04:07:18 PM PDT 24 |
Mar 17 04:12:49 PM PDT 24 |
3515989050 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.1274772671 |
|
|
Mar 17 03:51:53 PM PDT 24 |
Mar 17 04:00:58 PM PDT 24 |
4435570846 ps |
| T373 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sysrst_ctrl_reset.3733501889 |
|
|
Mar 17 03:48:06 PM PDT 24 |
Mar 17 04:01:53 PM PDT 24 |
6972588780 ps |
| T374 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.1453426090 |
|
|
Mar 17 04:02:26 PM PDT 24 |
Mar 17 04:14:23 PM PDT 24 |
6569056644 ps |
| T50 |
/workspace/coverage/default/2.chip_sw_alert_test.4222260228 |
|
|
Mar 17 04:03:24 PM PDT 24 |
Mar 17 04:07:09 PM PDT 24 |
3045630576 ps |
| T375 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1812337958 |
|
|
Mar 17 04:16:06 PM PDT 24 |
Mar 17 04:23:57 PM PDT 24 |
4057726440 ps |
| T376 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.3734510923 |
|
|
Mar 17 04:05:17 PM PDT 24 |
Mar 17 04:37:48 PM PDT 24 |
9437590608 ps |
| T377 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.2974191173 |
|
|
Mar 17 04:14:09 PM PDT 24 |
Mar 17 04:20:58 PM PDT 24 |
4487181016 ps |
| T378 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.274311434 |
|
|
Mar 17 04:18:31 PM PDT 24 |
Mar 17 04:24:56 PM PDT 24 |
3518610760 ps |
| T379 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.3086038548 |
|
|
Mar 17 04:19:03 PM PDT 24 |
Mar 17 04:26:44 PM PDT 24 |
4272861420 ps |
| T380 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.3706741460 |
|
|
Mar 17 04:02:37 PM PDT 24 |
Mar 17 04:25:18 PM PDT 24 |
8180357100 ps |
| T1020 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1486479726 |
|
|
Mar 17 04:05:00 PM PDT 24 |
Mar 17 04:10:36 PM PDT 24 |
2688332037 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3520558572 |
|
|
Mar 17 04:05:10 PM PDT 24 |
Mar 17 05:05:35 PM PDT 24 |
35253227112 ps |
| T409 |
/workspace/coverage/default/1.chip_jtag_mem_access.2530071273 |
|
|
Mar 17 03:49:06 PM PDT 24 |
Mar 17 04:10:19 PM PDT 24 |
12786448952 ps |
| T302 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.2247322956 |
|
|
Mar 17 03:46:23 PM PDT 24 |
Mar 17 04:01:54 PM PDT 24 |
4652109304 ps |
| T219 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.2804869824 |
|
|
Mar 17 03:47:15 PM PDT 24 |
Mar 17 03:57:17 PM PDT 24 |
5102579675 ps |
| T173 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through.2259312770 |
|
|
Mar 17 03:46:09 PM PDT 24 |
Mar 17 04:00:10 PM PDT 24 |
8141947731 ps |
| T86 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2174138131 |
|
|
Mar 17 04:19:05 PM PDT 24 |
Mar 17 04:26:13 PM PDT 24 |
3907159860 ps |
| T1022 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.1112430102 |
|
|
Mar 17 03:52:34 PM PDT 24 |
Mar 17 04:11:14 PM PDT 24 |
5224620816 ps |
| T1023 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.2449417799 |
|
|
Mar 17 04:00:19 PM PDT 24 |
Mar 17 04:07:00 PM PDT 24 |
5188077880 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.3826203577 |
|
|
Mar 17 03:51:24 PM PDT 24 |
Mar 17 04:09:17 PM PDT 24 |
12494937870 ps |
| T1025 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2245073091 |
|
|
Mar 17 03:53:56 PM PDT 24 |
Mar 17 03:58:22 PM PDT 24 |
2618663120 ps |
| T1026 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1846286084 |
|
|
Mar 17 03:49:21 PM PDT 24 |
Mar 17 03:54:19 PM PDT 24 |
2729640836 ps |
| T220 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.1071593886 |
|
|
Mar 17 03:54:52 PM PDT 24 |
Mar 17 04:02:42 PM PDT 24 |
4319476840 ps |
| T679 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.314774053 |
|
|
Mar 17 03:48:57 PM PDT 24 |
Mar 17 03:58:13 PM PDT 24 |
5663735574 ps |
| T308 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.84323748 |
|
|
Mar 17 04:10:21 PM PDT 24 |
Mar 17 04:21:52 PM PDT 24 |
4974861711 ps |
| T1027 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.2215854927 |
|
|
Mar 17 03:47:05 PM PDT 24 |
Mar 17 03:55:50 PM PDT 24 |
6691011462 ps |
| T1028 |
/workspace/coverage/default/1.chip_sw_example_flash.3843175613 |
|
|
Mar 17 03:50:42 PM PDT 24 |
Mar 17 03:53:49 PM PDT 24 |
2494608224 ps |
| T1029 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.3642745354 |
|
|
Mar 17 04:14:32 PM PDT 24 |
Mar 17 04:27:59 PM PDT 24 |
5311714504 ps |
| T1030 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.341076706 |
|
|
Mar 17 04:02:24 PM PDT 24 |
Mar 17 04:12:05 PM PDT 24 |
5950267675 ps |
| T801 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3267067451 |
|
|
Mar 17 04:13:25 PM PDT 24 |
Mar 17 04:21:05 PM PDT 24 |
3461782212 ps |
| T812 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2141947023 |
|
|
Mar 17 04:17:51 PM PDT 24 |
Mar 17 04:26:06 PM PDT 24 |
5600849530 ps |
| T1031 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.14187323 |
|
|
Mar 17 03:54:40 PM PDT 24 |
Mar 17 04:03:24 PM PDT 24 |
4560329760 ps |
| T286 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.1740041387 |
|
|
Mar 17 04:02:32 PM PDT 24 |
Mar 17 04:19:10 PM PDT 24 |
6328244112 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.3261521439 |
|
|
Mar 17 03:45:53 PM PDT 24 |
Mar 17 03:54:13 PM PDT 24 |
4355663352 ps |
| T1033 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2703921974 |
|
|
Mar 17 03:55:11 PM PDT 24 |
Mar 17 03:59:04 PM PDT 24 |
2443983656 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.214336861 |
|
|
Mar 17 03:47:49 PM PDT 24 |
Mar 17 04:49:59 PM PDT 24 |
20706173615 ps |
| T1034 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2731834543 |
|
|
Mar 17 03:52:52 PM PDT 24 |
Mar 17 03:57:03 PM PDT 24 |
2576298773 ps |
| T315 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.1773399926 |
|
|
Mar 17 03:47:32 PM PDT 24 |
Mar 17 03:52:21 PM PDT 24 |
3179682314 ps |
| T359 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.693275927 |
|
|
Mar 17 04:05:16 PM PDT 24 |
Mar 17 04:12:40 PM PDT 24 |
5780394640 ps |
| T1035 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.1597490472 |
|
|
Mar 17 04:03:10 PM PDT 24 |
Mar 17 04:20:14 PM PDT 24 |
5725435768 ps |
| T211 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.452149303 |
|
|
Mar 17 03:57:42 PM PDT 24 |
Mar 17 04:56:25 PM PDT 24 |
17983568610 ps |
| T41 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.1951359469 |
|
|
Mar 17 03:58:19 PM PDT 24 |
Mar 17 04:03:30 PM PDT 24 |
3342159776 ps |
| T384 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.1103838237 |
|
|
Mar 17 04:10:39 PM PDT 24 |
Mar 17 04:15:03 PM PDT 24 |
3367582037 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3361882035 |
|
|
Mar 17 03:49:00 PM PDT 24 |
Mar 17 04:12:26 PM PDT 24 |
19547719180 ps |
| T385 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2456774585 |
|
|
Mar 17 03:56:22 PM PDT 24 |
Mar 17 04:05:40 PM PDT 24 |
3932941492 ps |
| T386 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_disabled.1869074396 |
|
|
Mar 17 04:03:14 PM PDT 24 |
Mar 17 04:09:10 PM PDT 24 |
3210064948 ps |
| T387 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.3162466109 |
|
|
Mar 17 04:18:07 PM PDT 24 |
Mar 17 04:27:12 PM PDT 24 |
5129761872 ps |
| T388 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.288295909 |
|
|
Mar 17 04:04:34 PM PDT 24 |
Mar 17 04:12:09 PM PDT 24 |
4420233910 ps |
| T389 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3448238055 |
|
|
Mar 17 04:18:56 PM PDT 24 |
Mar 17 04:30:31 PM PDT 24 |
5468450200 ps |
| T390 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.3638785775 |
|
|
Mar 17 04:15:25 PM PDT 24 |
Mar 17 04:22:03 PM PDT 24 |
3715435512 ps |
| T141 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.2219541883 |
|
|
Mar 17 04:09:35 PM PDT 24 |
Mar 17 04:35:31 PM PDT 24 |
12932304711 ps |
| T1036 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.2163953779 |
|
|
Mar 17 03:54:32 PM PDT 24 |
Mar 17 04:27:43 PM PDT 24 |
8164305231 ps |
| T1037 |
/workspace/coverage/default/0.rom_e2e_asm_init_test_unlocked0.4205657567 |
|
|
Mar 17 03:54:33 PM PDT 24 |
Mar 17 04:19:53 PM PDT 24 |
7673079960 ps |
| T259 |
/workspace/coverage/default/2.chip_sw_data_integrity_escalation.2982762241 |
|
|
Mar 17 04:01:43 PM PDT 24 |
Mar 17 04:13:03 PM PDT 24 |
5118691360 ps |
| T1038 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.4251670534 |
|
|
Mar 17 04:10:33 PM PDT 24 |
Mar 17 04:22:32 PM PDT 24 |
8639633138 ps |
| T340 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.2867259188 |
|
|
Mar 17 04:16:23 PM PDT 24 |
Mar 17 04:25:27 PM PDT 24 |
4311791120 ps |
| T1039 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.4214547569 |
|
|
Mar 17 04:18:23 PM PDT 24 |
Mar 17 04:25:47 PM PDT 24 |
4049102318 ps |
| T751 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.3725098264 |
|
|
Mar 17 04:14:13 PM PDT 24 |
Mar 17 04:19:24 PM PDT 24 |
3322565190 ps |
| T1040 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.1537455659 |
|
|
Mar 17 04:10:25 PM PDT 24 |
Mar 17 04:26:13 PM PDT 24 |
5644694920 ps |
| T1041 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.638312515 |
|
|
Mar 17 04:12:47 PM PDT 24 |
Mar 17 04:21:39 PM PDT 24 |
3527400360 ps |
| T98 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2534307887 |
|
|
Mar 17 04:07:00 PM PDT 24 |
Mar 17 04:35:19 PM PDT 24 |
22434684624 ps |
| T1042 |
/workspace/coverage/default/2.rom_keymgr_functest.2984422630 |
|
|
Mar 17 04:09:43 PM PDT 24 |
Mar 17 04:19:38 PM PDT 24 |
5066556296 ps |
| T1043 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.3548996607 |
|
|
Mar 17 03:51:34 PM PDT 24 |
Mar 17 03:59:44 PM PDT 24 |
4979136572 ps |
| T1044 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3064362913 |
|
|
Mar 17 04:06:51 PM PDT 24 |
Mar 17 04:19:32 PM PDT 24 |
5156212761 ps |
| T1045 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.3870253703 |
|
|
Mar 17 04:13:31 PM PDT 24 |
Mar 17 04:21:48 PM PDT 24 |
4207726340 ps |