| T1192 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.2222279971 |
|
|
Mar 17 04:03:57 PM PDT 24 |
Mar 17 04:11:12 PM PDT 24 |
7403570276 ps |
| T1193 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.2196410817 |
|
|
Mar 17 04:13:30 PM PDT 24 |
Mar 17 04:19:01 PM PDT 24 |
3419609576 ps |
| T1194 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.3024427932 |
|
|
Mar 17 04:11:06 PM PDT 24 |
Mar 17 04:24:14 PM PDT 24 |
13070803192 ps |
| T1195 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1141443638 |
|
|
Mar 17 04:04:20 PM PDT 24 |
Mar 17 04:10:29 PM PDT 24 |
3464250900 ps |
| T800 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.3615229577 |
|
|
Mar 17 04:21:21 PM PDT 24 |
Mar 17 04:29:07 PM PDT 24 |
5155724050 ps |
| T1196 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.1435311398 |
|
|
Mar 17 04:02:36 PM PDT 24 |
Mar 17 04:17:46 PM PDT 24 |
10862867593 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.250444625 |
|
|
Mar 17 04:08:07 PM PDT 24 |
Mar 17 04:25:47 PM PDT 24 |
7262764378 ps |
| T1198 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.3127083759 |
|
|
Mar 17 03:53:35 PM PDT 24 |
Mar 17 04:05:08 PM PDT 24 |
6057706970 ps |
| T1199 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4009696348 |
|
|
Mar 17 04:04:59 PM PDT 24 |
Mar 17 04:21:25 PM PDT 24 |
5553862189 ps |
| T1200 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.601906913 |
|
|
Mar 17 03:47:06 PM PDT 24 |
Mar 17 03:51:20 PM PDT 24 |
3136079170 ps |
| T1201 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3953952253 |
|
|
Mar 17 04:05:57 PM PDT 24 |
Mar 17 04:37:40 PM PDT 24 |
8663406693 ps |
| T1202 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.2417479420 |
|
|
Mar 17 03:46:09 PM PDT 24 |
Mar 17 05:04:30 PM PDT 24 |
47258521834 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1324742809 |
|
|
Mar 17 04:03:54 PM PDT 24 |
Mar 17 04:19:54 PM PDT 24 |
5606572536 ps |
| T9 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.2672322124 |
|
|
Mar 17 03:51:13 PM PDT 24 |
Mar 17 03:56:56 PM PDT 24 |
3264080742 ps |
| T324 |
/workspace/coverage/default/1.chip_sw_hmac_enc.3972831161 |
|
|
Mar 17 03:53:56 PM PDT 24 |
Mar 17 03:58:41 PM PDT 24 |
2666284848 ps |
| T1204 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.1021491758 |
|
|
Mar 17 04:13:38 PM PDT 24 |
Mar 17 04:21:08 PM PDT 24 |
4184549228 ps |
| T1205 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.2257828110 |
|
|
Mar 17 04:15:34 PM PDT 24 |
Mar 17 04:21:16 PM PDT 24 |
3709048496 ps |
| T775 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.3033214138 |
|
|
Mar 17 04:13:03 PM PDT 24 |
Mar 17 04:19:52 PM PDT 24 |
4127869880 ps |
| T1206 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.3427806929 |
|
|
Mar 17 04:11:44 PM PDT 24 |
Mar 17 04:21:17 PM PDT 24 |
4693666237 ps |
| T1207 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.3700137463 |
|
|
Mar 17 03:45:48 PM PDT 24 |
Mar 17 03:57:58 PM PDT 24 |
5480645478 ps |
| T1208 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3050621109 |
|
|
Mar 17 03:57:15 PM PDT 24 |
Mar 17 04:03:15 PM PDT 24 |
2717748428 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.786178283 |
|
|
Mar 17 03:52:15 PM PDT 24 |
Mar 17 03:56:20 PM PDT 24 |
3165465080 ps |
| T1209 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.277296987 |
|
|
Mar 17 03:49:40 PM PDT 24 |
Mar 17 03:55:04 PM PDT 24 |
3984488832 ps |
| T299 |
/workspace/coverage/default/1.chip_sw_entropy_src_csrng.791640970 |
|
|
Mar 17 03:55:39 PM PDT 24 |
Mar 17 04:16:09 PM PDT 24 |
5400393320 ps |
| T1210 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_bootstrap.116673690 |
|
|
Mar 17 04:02:09 PM PDT 24 |
Mar 17 07:38:53 PM PDT 24 |
77912573660 ps |
| T1211 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1587248681 |
|
|
Mar 17 03:54:32 PM PDT 24 |
Mar 17 04:08:52 PM PDT 24 |
6861807542 ps |
| T1212 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.218087997 |
|
|
Mar 17 04:03:11 PM PDT 24 |
Mar 17 04:26:21 PM PDT 24 |
8927933000 ps |
| T793 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.2347606150 |
|
|
Mar 17 04:14:20 PM PDT 24 |
Mar 17 04:23:07 PM PDT 24 |
4622438412 ps |
| T1213 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.1042490772 |
|
|
Mar 17 03:56:58 PM PDT 24 |
Mar 17 04:00:08 PM PDT 24 |
2118592474 ps |
| T273 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.3724880617 |
|
|
Mar 17 04:07:04 PM PDT 24 |
Mar 17 04:12:18 PM PDT 24 |
2553498563 ps |
| T672 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.724702170 |
|
|
Mar 17 04:06:00 PM PDT 24 |
Mar 17 04:21:44 PM PDT 24 |
4194115810 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.4262613207 |
|
|
Mar 17 03:51:42 PM PDT 24 |
Mar 17 03:58:30 PM PDT 24 |
5418814843 ps |
| T789 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.1464579530 |
|
|
Mar 17 04:13:20 PM PDT 24 |
Mar 17 04:20:43 PM PDT 24 |
3795956136 ps |
| T813 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.674507696 |
|
|
Mar 17 04:12:44 PM PDT 24 |
Mar 17 04:24:05 PM PDT 24 |
5239422900 ps |
| T1215 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs.3082722824 |
|
|
Mar 17 03:48:29 PM PDT 24 |
Mar 17 04:08:03 PM PDT 24 |
4961508884 ps |
| T1216 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.3707818225 |
|
|
Mar 17 03:48:55 PM PDT 24 |
Mar 17 04:28:15 PM PDT 24 |
20435580313 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.1722820237 |
|
|
Mar 17 03:47:45 PM PDT 24 |
Mar 17 04:18:57 PM PDT 24 |
11566988360 ps |
| T1217 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.765050295 |
|
|
Mar 17 03:49:27 PM PDT 24 |
Mar 17 03:59:55 PM PDT 24 |
3356536232 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3626356369 |
|
|
Mar 17 04:05:16 PM PDT 24 |
Mar 17 04:15:14 PM PDT 24 |
2913776186 ps |
| T808 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3684961071 |
|
|
Mar 17 04:13:51 PM PDT 24 |
Mar 17 04:19:56 PM PDT 24 |
3277731956 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.861928980 |
|
|
Mar 17 03:52:12 PM PDT 24 |
Mar 17 06:56:00 PM PDT 24 |
65871613952 ps |
| T156 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.2018791530 |
|
|
Mar 17 03:47:38 PM PDT 24 |
Mar 17 03:55:43 PM PDT 24 |
3655383936 ps |
| T1219 |
/workspace/coverage/default/2.chip_sw_example_concurrency.3828490755 |
|
|
Mar 17 04:02:02 PM PDT 24 |
Mar 17 04:06:21 PM PDT 24 |
2280429166 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.1413970333 |
|
|
Mar 17 03:50:25 PM PDT 24 |
Mar 17 03:54:27 PM PDT 24 |
2681174290 ps |
| T778 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.2362351411 |
|
|
Mar 17 04:16:31 PM PDT 24 |
Mar 17 04:24:48 PM PDT 24 |
4877032520 ps |
| T1221 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.3109774266 |
|
|
Mar 17 04:05:56 PM PDT 24 |
Mar 17 04:36:25 PM PDT 24 |
10614104080 ps |
| T1222 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.1980403070 |
|
|
Mar 17 04:19:19 PM PDT 24 |
Mar 17 04:23:40 PM PDT 24 |
3240656104 ps |
| T37 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.3609424416 |
|
|
Mar 17 04:04:35 PM PDT 24 |
Mar 17 04:10:34 PM PDT 24 |
3598825126 ps |
| T1223 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.2561199084 |
|
|
Mar 17 03:56:20 PM PDT 24 |
Mar 17 04:47:31 PM PDT 24 |
11468990840 ps |
| T1224 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3030455898 |
|
|
Mar 17 04:13:57 PM PDT 24 |
Mar 17 04:45:51 PM PDT 24 |
9402219895 ps |
| T1225 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.2738906264 |
|
|
Mar 17 03:57:45 PM PDT 24 |
Mar 17 04:01:35 PM PDT 24 |
2948518203 ps |
| T1226 |
/workspace/coverage/default/3.chip_tap_straps_rma.1144522985 |
|
|
Mar 17 04:08:30 PM PDT 24 |
Mar 17 04:17:26 PM PDT 24 |
5187212697 ps |
| T1227 |
/workspace/coverage/default/0.chip_sw_hmac_enc.3891250677 |
|
|
Mar 17 03:48:27 PM PDT 24 |
Mar 17 03:55:41 PM PDT 24 |
3205109252 ps |
| T1228 |
/workspace/coverage/default/0.chip_sw_example_concurrency.4160347023 |
|
|
Mar 17 03:46:49 PM PDT 24 |
Mar 17 03:50:31 PM PDT 24 |
2164309024 ps |
| T1229 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2607278404 |
|
|
Mar 17 03:49:11 PM PDT 24 |
Mar 17 03:53:29 PM PDT 24 |
2238932576 ps |
| T1230 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3026654438 |
|
|
Mar 17 04:05:06 PM PDT 24 |
Mar 17 04:24:24 PM PDT 24 |
13157412540 ps |
| T332 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.3103136880 |
|
|
Mar 17 03:51:05 PM PDT 24 |
Mar 17 03:59:29 PM PDT 24 |
3103610572 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.837887310 |
|
|
Mar 17 04:03:45 PM PDT 24 |
Mar 17 04:12:28 PM PDT 24 |
5106077360 ps |
| T735 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.976647818 |
|
|
Mar 17 03:48:10 PM PDT 24 |
Mar 17 04:25:03 PM PDT 24 |
21937599456 ps |
| T1231 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.3280864753 |
|
|
Mar 17 03:59:05 PM PDT 24 |
Mar 17 04:53:11 PM PDT 24 |
12003661136 ps |
| T311 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.2059210006 |
|
|
Mar 17 04:03:31 PM PDT 24 |
Mar 17 04:15:13 PM PDT 24 |
3777054758 ps |
| T1232 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3800397364 |
|
|
Mar 17 04:16:23 PM PDT 24 |
Mar 17 04:24:54 PM PDT 24 |
3812671792 ps |
| T1233 |
/workspace/coverage/default/4.chip_sw_uart_rand_baudrate.316853426 |
|
|
Mar 17 04:10:14 PM PDT 24 |
Mar 17 04:43:13 PM PDT 24 |
13999163152 ps |
| T770 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.3709814990 |
|
|
Mar 17 04:15:49 PM PDT 24 |
Mar 17 04:24:29 PM PDT 24 |
5276493454 ps |
| T246 |
/workspace/coverage/default/4.chip_sw_data_integrity_escalation.3326129405 |
|
|
Mar 17 04:10:30 PM PDT 24 |
Mar 17 04:21:41 PM PDT 24 |
4536615492 ps |
| T212 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.2265513923 |
|
|
Mar 17 04:12:30 PM PDT 24 |
Mar 17 04:57:31 PM PDT 24 |
12113638788 ps |
| T1234 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_bootstrap.1749314115 |
|
|
Mar 17 03:51:11 PM PDT 24 |
Mar 17 07:24:06 PM PDT 24 |
77969280913 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3818482551 |
|
|
Mar 17 03:56:58 PM PDT 24 |
Mar 17 04:03:18 PM PDT 24 |
4976584016 ps |
| T1235 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.3662126176 |
|
|
Mar 17 03:51:49 PM PDT 24 |
Mar 17 04:03:09 PM PDT 24 |
6082520639 ps |
| T295 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.1497865913 |
|
|
Mar 17 04:07:02 PM PDT 24 |
Mar 17 04:23:47 PM PDT 24 |
6402073386 ps |
| T1236 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.3230061478 |
|
|
Mar 17 04:11:31 PM PDT 24 |
Mar 17 04:19:52 PM PDT 24 |
4879658723 ps |
| T1237 |
/workspace/coverage/default/0.rom_e2e_static_critical.787457468 |
|
|
Mar 17 04:00:06 PM PDT 24 |
Mar 17 04:48:16 PM PDT 24 |
10514645718 ps |
| T1238 |
/workspace/coverage/default/2.chip_sw_pwrmgr_wdog_reset.1837618227 |
|
|
Mar 17 04:03:27 PM PDT 24 |
Mar 17 04:12:52 PM PDT 24 |
3912353912 ps |
| T1239 |
/workspace/coverage/default/0.chip_sw_aes_enc.185073971 |
|
|
Mar 17 03:47:05 PM PDT 24 |
Mar 17 03:50:58 PM PDT 24 |
2962822034 ps |
| T1240 |
/workspace/coverage/default/6.chip_sw_alert_handler_lpg_sleep_mode_alerts.150524923 |
|
|
Mar 17 04:11:32 PM PDT 24 |
Mar 17 04:17:09 PM PDT 24 |
3534556052 ps |
| T818 |
/workspace/coverage/default/87.chip_sw_all_escalation_resets.2287852411 |
|
|
Mar 17 04:19:15 PM PDT 24 |
Mar 17 04:28:53 PM PDT 24 |
6020602596 ps |
| T1241 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.26944802 |
|
|
Mar 17 04:14:13 PM PDT 24 |
Mar 17 04:25:57 PM PDT 24 |
5756226182 ps |
| T1242 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.1682353670 |
|
|
Mar 17 04:07:10 PM PDT 24 |
Mar 17 04:14:08 PM PDT 24 |
3989615202 ps |
| T42 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.564530608 |
|
|
Mar 17 04:07:03 PM PDT 24 |
Mar 17 04:14:02 PM PDT 24 |
4203614060 ps |
| T817 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.4196356339 |
|
|
Mar 17 04:19:24 PM PDT 24 |
Mar 17 04:30:05 PM PDT 24 |
4950815764 ps |
| T742 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.1912485535 |
|
|
Mar 17 03:52:25 PM PDT 24 |
Mar 17 04:53:11 PM PDT 24 |
20949121112 ps |
| T1243 |
/workspace/coverage/default/0.chip_sw_aon_timer_irq.2576755519 |
|
|
Mar 17 03:46:52 PM PDT 24 |
Mar 17 03:53:50 PM PDT 24 |
3147275640 ps |
| T1244 |
/workspace/coverage/default/2.chip_sw_aon_timer_sleep_wdog_sleep_pause.4264619675 |
|
|
Mar 17 04:05:05 PM PDT 24 |
Mar 17 04:14:55 PM PDT 24 |
7466654696 ps |
| T1245 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.2887125533 |
|
|
Mar 17 04:10:01 PM PDT 24 |
Mar 17 04:16:04 PM PDT 24 |
4643398492 ps |
| T1246 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.84021035 |
|
|
Mar 17 04:09:46 PM PDT 24 |
Mar 17 04:13:56 PM PDT 24 |
2551348186 ps |
| T1247 |
/workspace/coverage/default/0.chip_tap_straps_prod.3858982303 |
|
|
Mar 17 03:51:39 PM PDT 24 |
Mar 17 04:13:17 PM PDT 24 |
11958940884 ps |
| T1248 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.2879003317 |
|
|
Mar 17 03:47:30 PM PDT 24 |
Mar 17 03:51:45 PM PDT 24 |
3131233728 ps |
| T1249 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2866498927 |
|
|
Mar 17 03:54:03 PM PDT 24 |
Mar 17 04:24:36 PM PDT 24 |
8670355246 ps |
| T1250 |
/workspace/coverage/default/3.chip_sw_aon_timer_sleep_wdog_sleep_pause.1021434611 |
|
|
Mar 17 04:09:46 PM PDT 24 |
Mar 17 04:18:03 PM PDT 24 |
7032224648 ps |
| T1251 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.4240393337 |
|
|
Mar 17 04:01:59 PM PDT 24 |
Mar 17 04:17:36 PM PDT 24 |
5217579712 ps |
| T1252 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.1518532644 |
|
|
Mar 17 04:02:29 PM PDT 24 |
Mar 17 06:35:31 PM PDT 24 |
57032775544 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.3966255368 |
|
|
Mar 17 03:58:44 PM PDT 24 |
Mar 17 04:02:39 PM PDT 24 |
2686189549 ps |
| T730 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.2640700424 |
|
|
Mar 17 03:55:25 PM PDT 24 |
Mar 17 04:11:42 PM PDT 24 |
5186627850 ps |
| T1254 |
/workspace/coverage/default/0.chip_tap_straps_rma.3453035826 |
|
|
Mar 17 03:47:48 PM PDT 24 |
Mar 17 03:54:40 PM PDT 24 |
5136335016 ps |
| T1255 |
/workspace/coverage/default/2.chip_sw_power_idle_load.586385650 |
|
|
Mar 17 04:09:28 PM PDT 24 |
Mar 17 04:17:59 PM PDT 24 |
4703452650 ps |
| T1256 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1325150732 |
|
|
Mar 17 03:57:24 PM PDT 24 |
Mar 17 04:06:21 PM PDT 24 |
5781081010 ps |
| T1257 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.204892271 |
|
|
Mar 17 03:47:26 PM PDT 24 |
Mar 17 04:09:45 PM PDT 24 |
9712917582 ps |
| T341 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.1160318755 |
|
|
Mar 17 04:17:32 PM PDT 24 |
Mar 17 04:26:48 PM PDT 24 |
4651463768 ps |
| T1258 |
/workspace/coverage/default/2.chip_sw_flash_init.3718069536 |
|
|
Mar 17 04:03:27 PM PDT 24 |
Mar 17 04:34:38 PM PDT 24 |
24060725800 ps |
| T1259 |
/workspace/coverage/default/5.chip_sw_uart_rand_baudrate.1952815654 |
|
|
Mar 17 04:15:41 PM PDT 24 |
Mar 17 04:27:14 PM PDT 24 |
5646449108 ps |
| T53 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.1955326162 |
|
|
Mar 17 04:02:44 PM PDT 24 |
Mar 17 04:09:23 PM PDT 24 |
5770090560 ps |
| T1260 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_por_reset.4148180416 |
|
|
Mar 17 03:47:03 PM PDT 24 |
Mar 17 04:00:52 PM PDT 24 |
8628539990 ps |
| T779 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.2206632042 |
|
|
Mar 17 04:16:12 PM PDT 24 |
Mar 17 04:26:21 PM PDT 24 |
6104754680 ps |
| T1261 |
/workspace/coverage/default/3.chip_tap_straps_prod.2331976449 |
|
|
Mar 17 04:11:05 PM PDT 24 |
Mar 17 04:29:53 PM PDT 24 |
12473229112 ps |
| T303 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.876000645 |
|
|
Mar 17 04:07:30 PM PDT 24 |
Mar 17 04:20:41 PM PDT 24 |
5161530628 ps |
| T28 |
/workspace/coverage/default/0.chip_sw_gpio.1689423530 |
|
|
Mar 17 03:47:06 PM PDT 24 |
Mar 17 03:54:23 PM PDT 24 |
3978669909 ps |
| T1262 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.751390040 |
|
|
Mar 17 03:53:10 PM PDT 24 |
Mar 17 03:57:00 PM PDT 24 |
2758531548 ps |
| T1263 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.138755633 |
|
|
Mar 17 03:49:27 PM PDT 24 |
Mar 17 04:00:41 PM PDT 24 |
8187549173 ps |
| T1264 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en_reduced_freq.101417684 |
|
|
Mar 17 03:51:24 PM PDT 24 |
Mar 17 03:55:44 PM PDT 24 |
2763330077 ps |
| T1265 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.4143119768 |
|
|
Mar 17 04:02:16 PM PDT 24 |
Mar 17 04:23:52 PM PDT 24 |
8370724932 ps |
| T1266 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.1642136377 |
|
|
Mar 17 04:00:01 PM PDT 24 |
Mar 17 04:18:06 PM PDT 24 |
8518148904 ps |
| T1267 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2859175649 |
|
|
Mar 17 04:12:26 PM PDT 24 |
Mar 17 04:41:50 PM PDT 24 |
8760688102 ps |
| T34 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.1073253326 |
|
|
Mar 17 03:53:32 PM PDT 24 |
Mar 17 04:00:01 PM PDT 24 |
3540831276 ps |
| T1268 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.1437202483 |
|
|
Mar 17 04:09:34 PM PDT 24 |
Mar 17 04:22:59 PM PDT 24 |
5255226862 ps |
| T342 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.323565381 |
|
|
Mar 17 04:16:13 PM PDT 24 |
Mar 17 04:23:53 PM PDT 24 |
4133699080 ps |
| T1269 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.3703431918 |
|
|
Mar 17 03:52:01 PM PDT 24 |
Mar 17 04:05:45 PM PDT 24 |
6002575780 ps |
| T1270 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.1933691846 |
|
|
Mar 17 03:50:02 PM PDT 24 |
Mar 17 03:55:36 PM PDT 24 |
4585766060 ps |
| T1271 |
/workspace/coverage/default/2.chip_sw_alert_handler_entropy.2971650739 |
|
|
Mar 17 04:06:17 PM PDT 24 |
Mar 17 04:11:45 PM PDT 24 |
3401326473 ps |
| T88 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.475121178 |
|
|
Mar 17 04:20:01 PM PDT 24 |
Mar 17 04:30:41 PM PDT 24 |
5526799680 ps |
| T827 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1117968132 |
|
|
Mar 17 04:19:08 PM PDT 24 |
Mar 17 04:27:53 PM PDT 24 |
4981664622 ps |
| T322 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.3077180325 |
|
|
Mar 17 03:54:32 PM PDT 24 |
Mar 17 04:03:25 PM PDT 24 |
3833264186 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.4016468273 |
|
|
Mar 17 04:09:36 PM PDT 24 |
Mar 17 04:13:38 PM PDT 24 |
3404259740 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx.2447043020 |
|
|
Mar 17 03:47:23 PM PDT 24 |
Mar 17 03:58:45 PM PDT 24 |
5342135994 ps |
| T783 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.1264327285 |
|
|
Mar 17 04:11:03 PM PDT 24 |
Mar 17 04:23:42 PM PDT 24 |
5636691082 ps |
| T236 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1121670319 |
|
|
Mar 17 03:51:09 PM PDT 24 |
Mar 17 04:02:27 PM PDT 24 |
5331483136 ps |
| T1274 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2589760229 |
|
|
Mar 17 03:49:56 PM PDT 24 |
Mar 17 03:53:48 PM PDT 24 |
2865675780 ps |
| T1275 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.237852886 |
|
|
Mar 17 03:59:39 PM PDT 24 |
Mar 17 04:30:09 PM PDT 24 |
20838266714 ps |
| T89 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.1092676395 |
|
|
Mar 17 04:18:39 PM PDT 24 |
Mar 17 04:29:44 PM PDT 24 |
5511361622 ps |
| T323 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.4180059024 |
|
|
Mar 17 04:01:06 PM PDT 24 |
Mar 17 04:12:02 PM PDT 24 |
4631416571 ps |
| T1276 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.2925607008 |
|
|
Mar 17 03:55:55 PM PDT 24 |
Mar 17 04:28:56 PM PDT 24 |
8110686570 ps |
| T1277 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.1258485362 |
|
|
Mar 17 03:52:57 PM PDT 24 |
Mar 17 03:57:16 PM PDT 24 |
2680643000 ps |
| T1278 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3000911179 |
|
|
Mar 17 03:58:11 PM PDT 24 |
Mar 17 04:26:14 PM PDT 24 |
6922127784 ps |
| T1279 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.2642714786 |
|
|
Mar 17 04:01:03 PM PDT 24 |
Mar 17 04:06:23 PM PDT 24 |
2746095996 ps |
| T1280 |
/workspace/coverage/default/0.chip_sw_gpio_smoketest.3575600873 |
|
|
Mar 17 03:52:43 PM PDT 24 |
Mar 17 03:57:39 PM PDT 24 |
2576765432 ps |
| T1281 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.2913702693 |
|
|
Mar 17 03:49:03 PM PDT 24 |
Mar 17 05:00:45 PM PDT 24 |
18401085614 ps |
| T1282 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2314134287 |
|
|
Mar 17 03:48:04 PM PDT 24 |
Mar 17 03:52:14 PM PDT 24 |
3074058372 ps |
| T1283 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.4065820508 |
|
|
Mar 17 03:51:19 PM PDT 24 |
Mar 17 04:08:09 PM PDT 24 |
5808545120 ps |
| T1284 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.1422214894 |
|
|
Mar 17 04:04:20 PM PDT 24 |
Mar 17 04:33:04 PM PDT 24 |
27117066749 ps |
| T1285 |
/workspace/coverage/default/0.rom_e2e_smoke.86052779 |
|
|
Mar 17 03:50:27 PM PDT 24 |
Mar 17 04:25:52 PM PDT 24 |
8991402468 ps |
| T1286 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.1011585849 |
|
|
Mar 17 03:50:36 PM PDT 24 |
Mar 17 03:52:46 PM PDT 24 |
2482020582 ps |
| T1287 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.3326904938 |
|
|
Mar 17 04:12:03 PM PDT 24 |
Mar 17 04:25:52 PM PDT 24 |
5283911824 ps |
| T274 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.2718161890 |
|
|
Mar 17 03:58:29 PM PDT 24 |
Mar 17 04:03:25 PM PDT 24 |
2992897059 ps |
| T765 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.2077487871 |
|
|
Mar 17 04:04:39 PM PDT 24 |
Mar 17 04:23:43 PM PDT 24 |
9161729440 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.1281650878 |
|
|
Mar 17 04:05:49 PM PDT 24 |
Mar 17 04:10:46 PM PDT 24 |
3420700410 ps |
| T1289 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.4221643375 |
|
|
Mar 17 03:55:08 PM PDT 24 |
Mar 17 04:11:39 PM PDT 24 |
4982662939 ps |
| T1290 |
/workspace/coverage/default/1.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.3156823368 |
|
|
Mar 17 03:54:16 PM PDT 24 |
Mar 17 04:16:02 PM PDT 24 |
10344202889 ps |
| T247 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.1922528897 |
|
|
Mar 17 04:10:45 PM PDT 24 |
Mar 17 04:23:24 PM PDT 24 |
5202206180 ps |
| T1291 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.3149096538 |
|
|
Mar 17 03:51:21 PM PDT 24 |
Mar 17 04:00:02 PM PDT 24 |
3825493568 ps |
| T1292 |
/workspace/coverage/default/1.chip_sw_pwrmgr_b2b_sleep_reset_req.116312434 |
|
|
Mar 17 03:56:27 PM PDT 24 |
Mar 17 04:41:14 PM PDT 24 |
21642735851 ps |
| T1293 |
/workspace/coverage/default/1.chip_sw_aes_smoketest.1719578654 |
|
|
Mar 17 04:02:03 PM PDT 24 |
Mar 17 04:06:51 PM PDT 24 |
3212540854 ps |
| T1294 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.1551877744 |
|
|
Mar 17 04:05:17 PM PDT 24 |
Mar 17 04:36:10 PM PDT 24 |
8367309283 ps |
| T1295 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.3547791007 |
|
|
Mar 17 03:47:14 PM PDT 24 |
Mar 17 03:48:59 PM PDT 24 |
2636235373 ps |
| T1296 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.915219560 |
|
|
Mar 17 03:49:48 PM PDT 24 |
Mar 17 04:00:54 PM PDT 24 |
4433380890 ps |
| T1297 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.1437858146 |
|
|
Mar 17 03:56:37 PM PDT 24 |
Mar 17 04:03:36 PM PDT 24 |
4007458948 ps |
| T1298 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.3744851775 |
|
|
Mar 17 04:05:06 PM PDT 24 |
Mar 17 04:13:25 PM PDT 24 |
4021536736 ps |
| T1299 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.2603280540 |
|
|
Mar 17 03:54:27 PM PDT 24 |
Mar 17 04:28:17 PM PDT 24 |
8531883800 ps |
| T1300 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3650891235 |
|
|
Mar 17 03:55:33 PM PDT 24 |
Mar 17 04:06:25 PM PDT 24 |
4258693826 ps |
| T1301 |
/workspace/coverage/default/0.chip_sw_otbn_randomness.3556656540 |
|
|
Mar 17 03:48:17 PM PDT 24 |
Mar 17 04:05:36 PM PDT 24 |
5941318500 ps |
| T1302 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2960765859 |
|
|
Mar 17 04:07:19 PM PDT 24 |
Mar 17 04:18:11 PM PDT 24 |
4306924476 ps |
| T201 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1435709096 |
|
|
Mar 17 03:50:42 PM PDT 24 |
Mar 17 03:56:58 PM PDT 24 |
4136993255 ps |
| T1303 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.984317062 |
|
|
Mar 17 03:54:33 PM PDT 24 |
Mar 17 04:22:59 PM PDT 24 |
7419630264 ps |
| T1304 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.3617111924 |
|
|
Mar 17 04:04:50 PM PDT 24 |
Mar 17 04:09:54 PM PDT 24 |
2976784932 ps |
| T1305 |
/workspace/coverage/default/0.chip_sw_flash_init.1761487389 |
|
|
Mar 17 03:46:02 PM PDT 24 |
Mar 17 04:21:42 PM PDT 24 |
15899268400 ps |
| T746 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_alerts.3422142155 |
|
|
Mar 17 04:03:48 PM PDT 24 |
Mar 17 04:11:14 PM PDT 24 |
3653897746 ps |
| T1306 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.4135021840 |
|
|
Mar 17 03:58:50 PM PDT 24 |
Mar 17 04:48:40 PM PDT 24 |
12320505048 ps |
| T700 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2556647046 |
|
|
Mar 17 04:18:49 PM PDT 24 |
Mar 17 04:26:48 PM PDT 24 |
5242004250 ps |
| T743 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.3098330395 |
|
|
Mar 17 04:17:03 PM PDT 24 |
Mar 17 04:24:18 PM PDT 24 |
3430018930 ps |
| T1307 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.1239330624 |
|
|
Mar 17 03:50:35 PM PDT 24 |
Mar 17 03:56:13 PM PDT 24 |
2582320374 ps |
| T1308 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2714419447 |
|
|
Mar 17 03:56:05 PM PDT 24 |
Mar 17 04:12:11 PM PDT 24 |
7409583432 ps |
| T1309 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2106237945 |
|
|
Mar 17 03:52:52 PM PDT 24 |
Mar 17 04:00:08 PM PDT 24 |
4383871554 ps |
| T1310 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.1240434542 |
|
|
Mar 17 03:55:38 PM PDT 24 |
Mar 17 04:29:42 PM PDT 24 |
9914130920 ps |
| T745 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.3206303568 |
|
|
Mar 17 04:13:25 PM PDT 24 |
Mar 17 04:18:53 PM PDT 24 |
3060785972 ps |
| T1311 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.1917691626 |
|
|
Mar 17 03:55:43 PM PDT 24 |
Mar 17 04:08:21 PM PDT 24 |
4405978544 ps |
| T1312 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2487746157 |
|
|
Mar 17 04:12:47 PM PDT 24 |
Mar 17 04:18:56 PM PDT 24 |
3860588722 ps |
| T1313 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.4232714803 |
|
|
Mar 17 03:46:26 PM PDT 24 |
Mar 17 03:50:33 PM PDT 24 |
2842953800 ps |
| T1314 |
/workspace/coverage/default/70.chip_sw_all_escalation_resets.3064687666 |
|
|
Mar 17 04:17:15 PM PDT 24 |
Mar 17 04:26:43 PM PDT 24 |
5704633760 ps |
| T786 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.273023414 |
|
|
Mar 17 04:17:27 PM PDT 24 |
Mar 17 04:23:27 PM PDT 24 |
3494832432 ps |
| T1315 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.2249967100 |
|
|
Mar 17 03:50:05 PM PDT 24 |
Mar 17 04:09:22 PM PDT 24 |
7996906477 ps |
| T338 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.2419658533 |
|
|
Mar 17 03:58:28 PM PDT 24 |
Mar 17 04:01:20 PM PDT 24 |
2614671400 ps |
| T824 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.31980481 |
|
|
Mar 17 03:49:17 PM PDT 24 |
Mar 17 03:57:33 PM PDT 24 |
4546290728 ps |
| T1316 |
/workspace/coverage/default/2.chip_sw_example_flash.3030712556 |
|
|
Mar 17 04:01:08 PM PDT 24 |
Mar 17 04:05:12 PM PDT 24 |
2732085048 ps |
| T1317 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.3514383527 |
|
|
Mar 17 03:52:12 PM PDT 24 |
Mar 17 03:57:00 PM PDT 24 |
3199283606 ps |
| T69 |
/workspace/coverage/cover_reg_top/54.xbar_random_large_delays.3364274576 |
|
|
Mar 17 03:31:50 PM PDT 24 |
Mar 17 03:48:32 PM PDT 24 |
88204045770 ps |
| T70 |
/workspace/coverage/cover_reg_top/56.xbar_smoke_slow_rsp.286066388 |
|
|
Mar 17 03:32:10 PM PDT 24 |
Mar 17 03:33:49 PM PDT 24 |
5584048325 ps |
| T71 |
/workspace/coverage/cover_reg_top/17.chip_tl_errors.2536942434 |
|
|
Mar 17 03:25:22 PM PDT 24 |
Mar 17 03:28:35 PM PDT 24 |
3050196680 ps |
| T76 |
/workspace/coverage/cover_reg_top/78.xbar_smoke_large_delays.2993910593 |
|
|
Mar 17 03:35:27 PM PDT 24 |
Mar 17 03:36:57 PM PDT 24 |
7871650050 ps |
| T77 |
/workspace/coverage/cover_reg_top/34.xbar_smoke_slow_rsp.104602331 |
|
|
Mar 17 03:28:38 PM PDT 24 |
Mar 17 03:30:11 PM PDT 24 |
5343999566 ps |
| T329 |
/workspace/coverage/cover_reg_top/59.xbar_access_same_device_slow_rsp.499397750 |
|
|
Mar 17 03:32:43 PM PDT 24 |
Mar 17 04:00:36 PM PDT 24 |
86339053519 ps |
| T520 |
/workspace/coverage/cover_reg_top/16.chip_tl_errors.1033154348 |
|
|
Mar 17 03:25:17 PM PDT 24 |
Mar 17 03:30:08 PM PDT 24 |
4143396760 ps |
| T78 |
/workspace/coverage/cover_reg_top/65.xbar_same_source.3780069689 |
|
|
Mar 17 03:33:32 PM PDT 24 |
Mar 17 03:34:19 PM PDT 24 |
1639489763 ps |
| T416 |
/workspace/coverage/cover_reg_top/33.xbar_error_and_unmapped_addr.603788836 |
|
|
Mar 17 03:28:30 PM PDT 24 |
Mar 17 03:28:35 PM PDT 24 |
23618112 ps |
| T463 |
/workspace/coverage/cover_reg_top/68.xbar_random_large_delays.1140509941 |
|
|
Mar 17 03:33:56 PM PDT 24 |
Mar 17 03:53:57 PM PDT 24 |
96356435940 ps |
| T701 |
/workspace/coverage/cover_reg_top/4.xbar_access_same_device.1865741858 |
|
|
Mar 17 03:22:50 PM PDT 24 |
Mar 17 03:23:44 PM PDT 24 |
767941821 ps |
| T523 |
/workspace/coverage/cover_reg_top/15.xbar_smoke_zero_delays.937639220 |
|
|
Mar 17 03:24:38 PM PDT 24 |
Mar 17 03:24:47 PM PDT 24 |
56891217 ps |
| T168 |
/workspace/coverage/cover_reg_top/1.chip_csr_rw.278810540 |
|
|
Mar 17 03:22:39 PM PDT 24 |
Mar 17 03:27:53 PM PDT 24 |
3640972880 ps |
| T417 |
/workspace/coverage/cover_reg_top/23.xbar_error_random.3748034431 |
|
|
Mar 17 03:26:47 PM PDT 24 |
Mar 17 03:27:33 PM PDT 24 |
1281054538 ps |
| T768 |
/workspace/coverage/cover_reg_top/71.xbar_random_large_delays.2917017906 |
|
|
Mar 17 03:34:27 PM PDT 24 |
Mar 17 03:35:19 PM PDT 24 |
5339310993 ps |
| T418 |
/workspace/coverage/cover_reg_top/16.xbar_error_and_unmapped_addr.2187410201 |
|
|
Mar 17 03:25:20 PM PDT 24 |
Mar 17 03:25:55 PM PDT 24 |
273354395 ps |
| T522 |
/workspace/coverage/cover_reg_top/51.xbar_access_same_device_slow_rsp.2581838503 |
|
|
Mar 17 03:31:37 PM PDT 24 |
Mar 17 03:57:52 PM PDT 24 |
87972105930 ps |
| T431 |
/workspace/coverage/cover_reg_top/19.xbar_smoke_slow_rsp.2121797476 |
|
|
Mar 17 03:25:39 PM PDT 24 |
Mar 17 03:26:39 PM PDT 24 |
3690611497 ps |
| T521 |
/workspace/coverage/cover_reg_top/58.xbar_stress_all_with_error.3319770569 |
|
|
Mar 17 03:32:43 PM PDT 24 |
Mar 17 03:39:41 PM PDT 24 |
10340731435 ps |
| T1318 |
/workspace/coverage/cover_reg_top/34.xbar_smoke.3341269700 |
|
|
Mar 17 03:28:36 PM PDT 24 |
Mar 17 03:28:42 PM PDT 24 |
36350742 ps |
| T541 |
/workspace/coverage/cover_reg_top/35.xbar_smoke_large_delays.775806894 |
|
|
Mar 17 03:28:41 PM PDT 24 |
Mar 17 03:29:59 PM PDT 24 |
7345911629 ps |
| T370 |
/workspace/coverage/cover_reg_top/70.xbar_same_source.1684620968 |
|
|
Mar 17 03:34:19 PM PDT 24 |
Mar 17 03:35:46 PM PDT 24 |
2596714082 ps |
| T1319 |
/workspace/coverage/cover_reg_top/22.xbar_smoke.845852562 |
|
|
Mar 17 03:26:21 PM PDT 24 |
Mar 17 03:26:30 PM PDT 24 |
214081330 ps |
| T423 |
/workspace/coverage/cover_reg_top/56.xbar_stress_all.4135146677 |
|
|
Mar 17 03:32:12 PM PDT 24 |
Mar 17 03:35:43 PM PDT 24 |
5646838810 ps |
| T829 |
/workspace/coverage/cover_reg_top/85.xbar_stress_all_with_rand_reset.421230864 |
|
|
Mar 17 03:36:32 PM PDT 24 |
Mar 17 03:36:54 PM PDT 24 |
24045080 ps |
| T514 |
/workspace/coverage/cover_reg_top/84.xbar_unmapped_addr.4143797390 |
|
|
Mar 17 03:36:26 PM PDT 24 |
Mar 17 03:36:36 PM PDT 24 |
70577000 ps |
| T393 |
/workspace/coverage/cover_reg_top/8.xbar_random_slow_rsp.1021750757 |
|
|
Mar 17 03:22:58 PM PDT 24 |
Mar 17 03:34:35 PM PDT 24 |
41322265686 ps |
| T1320 |
/workspace/coverage/cover_reg_top/18.xbar_error_and_unmapped_addr.4244566248 |
|
|
Mar 17 03:25:48 PM PDT 24 |
Mar 17 03:26:01 PM PDT 24 |
234810661 ps |
| T572 |
/workspace/coverage/cover_reg_top/56.xbar_random.3358959941 |
|
|
Mar 17 03:32:10 PM PDT 24 |
Mar 17 03:32:27 PM PDT 24 |
160988728 ps |
| T443 |
/workspace/coverage/cover_reg_top/95.xbar_stress_all_with_rand_reset.4133141595 |
|
|
Mar 17 03:37:49 PM PDT 24 |
Mar 17 03:47:06 PM PDT 24 |
10484007870 ps |
| T840 |
/workspace/coverage/cover_reg_top/44.xbar_access_same_device_slow_rsp.2212482774 |
|
|
Mar 17 03:30:22 PM PDT 24 |
Mar 17 03:42:17 PM PDT 24 |
38473690808 ps |
| T626 |
/workspace/coverage/cover_reg_top/68.xbar_smoke_zero_delays.989438482 |
|
|
Mar 17 03:33:58 PM PDT 24 |
Mar 17 03:34:04 PM PDT 24 |
44052084 ps |
| T664 |
/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_error.3874512950 |
|
|
Mar 17 03:33:10 PM PDT 24 |
Mar 17 03:39:11 PM PDT 24 |
9261263673 ps |
| T544 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_large_delays.3533898127 |
|
|
Mar 17 03:24:24 PM PDT 24 |
Mar 17 03:25:46 PM PDT 24 |
7092249809 ps |
| T516 |
/workspace/coverage/cover_reg_top/65.xbar_smoke_zero_delays.3817037162 |
|
|
Mar 17 03:33:26 PM PDT 24 |
Mar 17 03:33:33 PM PDT 24 |
53716342 ps |
| T515 |
/workspace/coverage/cover_reg_top/30.xbar_same_source.4191962703 |
|
|
Mar 17 03:27:53 PM PDT 24 |
Mar 17 03:28:35 PM PDT 24 |
1492816735 ps |
| T665 |
/workspace/coverage/cover_reg_top/14.xbar_error_random.354419601 |
|
|
Mar 17 03:24:34 PM PDT 24 |
Mar 17 03:25:04 PM PDT 24 |
365588419 ps |
| T1321 |
/workspace/coverage/cover_reg_top/22.xbar_random.2415368652 |
|
|
Mar 17 03:26:20 PM PDT 24 |
Mar 17 03:26:30 PM PDT 24 |
73747340 ps |
| T666 |
/workspace/coverage/cover_reg_top/89.xbar_error_random.2956573423 |
|
|
Mar 17 03:37:00 PM PDT 24 |
Mar 17 03:37:18 PM PDT 24 |
226578129 ps |
| T381 |
/workspace/coverage/cover_reg_top/22.xbar_same_source.722141339 |
|
|
Mar 17 03:26:26 PM PDT 24 |
Mar 17 03:26:52 PM PDT 24 |
360478466 ps |
| T562 |
/workspace/coverage/cover_reg_top/14.xbar_random_zero_delays.184240397 |
|
|
Mar 17 03:24:32 PM PDT 24 |
Mar 17 03:24:47 PM PDT 24 |
138159206 ps |
| T372 |
/workspace/coverage/cover_reg_top/74.xbar_stress_all.2802966475 |
|
|
Mar 17 03:34:54 PM PDT 24 |
Mar 17 03:38:46 PM PDT 24 |
6784122637 ps |
| T668 |
/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1396678297 |
|
|
Mar 17 03:26:41 PM PDT 24 |
Mar 17 03:28:21 PM PDT 24 |
546476919 ps |
| T587 |
/workspace/coverage/cover_reg_top/11.xbar_stress_all_with_reset_error.1616759913 |
|
|
Mar 17 03:24:08 PM PDT 24 |
Mar 17 03:30:36 PM PDT 24 |
7951016575 ps |
| T640 |
/workspace/coverage/cover_reg_top/49.xbar_stress_all_with_error.1881062187 |
|
|
Mar 17 03:31:14 PM PDT 24 |
Mar 17 03:35:15 PM PDT 24 |
2686245515 ps |
| T566 |
/workspace/coverage/cover_reg_top/97.xbar_stress_all_with_rand_reset.1434610025 |
|
|
Mar 17 03:38:07 PM PDT 24 |
Mar 17 03:40:11 PM PDT 24 |
428275583 ps |
| T530 |
/workspace/coverage/cover_reg_top/33.xbar_smoke_slow_rsp.119438642 |
|
|
Mar 17 03:28:28 PM PDT 24 |
Mar 17 03:30:15 PM PDT 24 |
6301165396 ps |
| T1322 |
/workspace/coverage/cover_reg_top/13.xbar_smoke_zero_delays.3897944900 |
|
|
Mar 17 03:24:20 PM PDT 24 |
Mar 17 03:24:26 PM PDT 24 |
35707037 ps |
| T536 |
/workspace/coverage/cover_reg_top/14.xbar_smoke.315538916 |
|
|
Mar 17 03:24:24 PM PDT 24 |
Mar 17 03:24:31 PM PDT 24 |
52243392 ps |
| T555 |
/workspace/coverage/cover_reg_top/40.xbar_random_large_delays.1141105092 |
|
|
Mar 17 03:29:38 PM PDT 24 |
Mar 17 03:43:42 PM PDT 24 |
73044626536 ps |
| T848 |
/workspace/coverage/cover_reg_top/29.xbar_access_same_device_slow_rsp.1867119093 |
|
|
Mar 17 03:27:46 PM PDT 24 |
Mar 17 03:44:40 PM PDT 24 |
57524751940 ps |
| T558 |
/workspace/coverage/cover_reg_top/40.xbar_random_zero_delays.2896174185 |
|
|
Mar 17 03:29:39 PM PDT 24 |
Mar 17 03:30:32 PM PDT 24 |
595983233 ps |
| T392 |
/workspace/coverage/cover_reg_top/89.xbar_access_same_device.503336130 |
|
|
Mar 17 03:37:02 PM PDT 24 |
Mar 17 03:38:33 PM PDT 24 |
1113198395 ps |
| T858 |
/workspace/coverage/cover_reg_top/95.xbar_random_slow_rsp.1977759200 |
|
|
Mar 17 03:37:45 PM PDT 24 |
Mar 17 03:38:43 PM PDT 24 |
3327495658 ps |
| T537 |
/workspace/coverage/cover_reg_top/50.xbar_stress_all.3594246273 |
|
|
Mar 17 03:31:18 PM PDT 24 |
Mar 17 03:32:22 PM PDT 24 |
813813399 ps |
| T446 |
/workspace/coverage/cover_reg_top/39.xbar_random.692652185 |
|
|
Mar 17 03:29:36 PM PDT 24 |
Mar 17 03:30:08 PM PDT 24 |
365730537 ps |
| T166 |
/workspace/coverage/cover_reg_top/15.chip_csr_rw.2791369383 |
|
|
Mar 17 03:25:15 PM PDT 24 |
Mar 17 03:33:14 PM PDT 24 |
5983334060 ps |
| T484 |
/workspace/coverage/cover_reg_top/5.xbar_random.1165966746 |
|
|
Mar 17 03:22:53 PM PDT 24 |
Mar 17 03:23:32 PM PDT 24 |
1217994306 ps |
| T551 |
/workspace/coverage/cover_reg_top/50.xbar_same_source.3008388532 |
|
|
Mar 17 03:31:23 PM PDT 24 |
Mar 17 03:31:46 PM PDT 24 |
730283198 ps |
| T1323 |
/workspace/coverage/cover_reg_top/2.chip_rv_dm_lc_disabled.2328220538 |
|
|
Mar 17 03:22:39 PM PDT 24 |
Mar 17 03:28:40 PM PDT 24 |
11011728953 ps |
| T432 |
/workspace/coverage/cover_reg_top/14.xbar_stress_all_with_rand_reset.1072607419 |
|
|
Mar 17 03:24:38 PM PDT 24 |
Mar 17 03:28:58 PM PDT 24 |
700420294 ps |
| T391 |
/workspace/coverage/cover_reg_top/86.xbar_stress_all_with_rand_reset.275917500 |
|
|
Mar 17 03:36:35 PM PDT 24 |
Mar 17 03:47:48 PM PDT 24 |
5091375294 ps |
| T604 |
/workspace/coverage/cover_reg_top/30.xbar_smoke_slow_rsp.889859652 |
|
|
Mar 17 03:27:49 PM PDT 24 |
Mar 17 03:29:37 PM PDT 24 |
6292006819 ps |
| T667 |
/workspace/coverage/cover_reg_top/4.xbar_stress_all_with_error.1919623866 |
|
|
Mar 17 03:22:48 PM PDT 24 |
Mar 17 03:27:25 PM PDT 24 |
3160104878 ps |
| T157 |
/workspace/coverage/cover_reg_top/0.chip_csr_hw_reset.1463604759 |
|
|
Mar 17 03:22:41 PM PDT 24 |
Mar 17 03:25:53 PM PDT 24 |
4621777726 ps |
| T548 |
/workspace/coverage/cover_reg_top/63.xbar_stress_all_with_rand_reset.4196017750 |
|
|
Mar 17 03:33:20 PM PDT 24 |
Mar 17 03:36:42 PM PDT 24 |
662673050 ps |
| T605 |
/workspace/coverage/cover_reg_top/10.xbar_random_slow_rsp.1497273851 |
|
|
Mar 17 03:23:47 PM PDT 24 |
Mar 17 03:28:37 PM PDT 24 |
16602921802 ps |
| T1324 |
/workspace/coverage/cover_reg_top/20.xbar_error_and_unmapped_addr.1924622617 |
|
|
Mar 17 03:26:03 PM PDT 24 |
Mar 17 03:26:31 PM PDT 24 |
745637791 ps |