| T320 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.1968728301 |
|
|
Mar 17 03:48:20 PM PDT 24 |
Mar 17 03:55:29 PM PDT 24 |
3479515894 ps |
| T289 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.1816085192 |
|
|
Mar 17 03:47:48 PM PDT 24 |
Mar 17 04:00:51 PM PDT 24 |
4462156994 ps |
| T1046 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.817934236 |
|
|
Mar 17 03:57:59 PM PDT 24 |
Mar 17 04:02:38 PM PDT 24 |
3016804765 ps |
| T1047 |
/workspace/coverage/default/1.chip_sw_gpio_smoketest.2460976892 |
|
|
Mar 17 04:00:14 PM PDT 24 |
Mar 17 04:04:34 PM PDT 24 |
2980392627 ps |
| T1048 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.3693888819 |
|
|
Mar 17 03:48:44 PM PDT 24 |
Mar 17 03:53:17 PM PDT 24 |
2455604126 ps |
| T215 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prod.1359972622 |
|
|
Mar 17 03:47:16 PM PDT 24 |
Mar 17 05:10:57 PM PDT 24 |
49959957576 ps |
| T1049 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.1867897970 |
|
|
Mar 17 04:08:59 PM PDT 24 |
Mar 17 04:13:25 PM PDT 24 |
2897622776 ps |
| T1050 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx.3471288473 |
|
|
Mar 17 04:01:55 PM PDT 24 |
Mar 17 04:17:14 PM PDT 24 |
5325702753 ps |
| T1051 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.515800495 |
|
|
Mar 17 04:17:59 PM PDT 24 |
Mar 17 04:28:00 PM PDT 24 |
6290031416 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1340560081 |
|
|
Mar 17 04:12:22 PM PDT 24 |
Mar 17 04:15:05 PM PDT 24 |
1952899816 ps |
| T1053 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.2099193130 |
|
|
Mar 17 04:10:27 PM PDT 24 |
Mar 17 04:19:15 PM PDT 24 |
5376340355 ps |
| T48 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.458274296 |
|
|
Mar 17 03:57:14 PM PDT 24 |
Mar 17 04:36:49 PM PDT 24 |
22022577904 ps |
| T1054 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.2620095121 |
|
|
Mar 17 03:56:07 PM PDT 24 |
Mar 17 04:04:26 PM PDT 24 |
5391810064 ps |
| T1055 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.370554300 |
|
|
Mar 17 03:50:39 PM PDT 24 |
Mar 17 04:02:21 PM PDT 24 |
5073362200 ps |
| T1056 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.390921225 |
|
|
Mar 17 03:50:09 PM PDT 24 |
Mar 17 04:01:30 PM PDT 24 |
5315898757 ps |
| T67 |
/workspace/coverage/default/0.chip_sw_usbdev_aon_pullup.1639052570 |
|
|
Mar 17 03:48:18 PM PDT 24 |
Mar 17 03:55:46 PM PDT 24 |
3216788568 ps |
| T115 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.2488299225 |
|
|
Mar 17 04:16:56 PM PDT 24 |
Mar 17 04:22:21 PM PDT 24 |
4023150748 ps |
| T330 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.183441631 |
|
|
Mar 17 03:55:07 PM PDT 24 |
Mar 17 04:03:58 PM PDT 24 |
2874274568 ps |
| T1057 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.1132900562 |
|
|
Mar 17 03:57:29 PM PDT 24 |
Mar 17 04:35:22 PM PDT 24 |
8612932984 ps |
| T260 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.2216402507 |
|
|
Mar 17 04:05:05 PM PDT 24 |
Mar 17 04:17:58 PM PDT 24 |
5126017280 ps |
| T87 |
/workspace/coverage/default/50.chip_sw_alert_handler_lpg_sleep_mode_alerts.1541784321 |
|
|
Mar 17 04:14:24 PM PDT 24 |
Mar 17 04:21:33 PM PDT 24 |
3782325628 ps |
| T23 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.1249112618 |
|
|
Mar 17 03:53:25 PM PDT 24 |
Mar 17 04:25:37 PM PDT 24 |
21345020732 ps |
| T1058 |
/workspace/coverage/default/1.rom_e2e_static_critical.4068331935 |
|
|
Mar 17 04:04:16 PM PDT 24 |
Mar 17 04:43:05 PM PDT 24 |
10259478972 ps |
| T1059 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3131154562 |
|
|
Mar 17 04:03:15 PM PDT 24 |
Mar 17 04:17:43 PM PDT 24 |
4836716504 ps |
| T1060 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.211031434 |
|
|
Mar 17 04:07:36 PM PDT 24 |
Mar 17 04:19:54 PM PDT 24 |
3818366658 ps |
| T1061 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.2539833587 |
|
|
Mar 17 03:47:00 PM PDT 24 |
Mar 17 03:49:56 PM PDT 24 |
2255771372 ps |
| T306 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.806868541 |
|
|
Mar 17 03:51:52 PM PDT 24 |
Mar 17 04:05:41 PM PDT 24 |
6162454779 ps |
| T1062 |
/workspace/coverage/default/0.chip_sw_coremark.3640099120 |
|
|
Mar 17 03:48:14 PM PDT 24 |
Mar 17 06:38:18 PM PDT 24 |
50732456936 ps |
| T307 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx2.1751881000 |
|
|
Mar 17 03:52:21 PM PDT 24 |
Mar 17 04:07:05 PM PDT 24 |
5753029393 ps |
| T337 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.1636824619 |
|
|
Mar 17 03:49:00 PM PDT 24 |
Mar 17 03:51:04 PM PDT 24 |
2147822242 ps |
| T1063 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.1597861994 |
|
|
Mar 17 03:51:57 PM PDT 24 |
Mar 17 03:56:29 PM PDT 24 |
2663439172 ps |
| T114 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3951374286 |
|
|
Mar 17 03:53:07 PM PDT 24 |
Mar 17 03:58:14 PM PDT 24 |
3003823391 ps |
| T1064 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.2485632939 |
|
|
Mar 17 04:04:23 PM PDT 24 |
Mar 17 04:17:42 PM PDT 24 |
5861581918 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_edn_kat.138929553 |
|
|
Mar 17 04:05:33 PM PDT 24 |
Mar 17 04:17:28 PM PDT 24 |
3731341800 ps |
| T1066 |
/workspace/coverage/default/6.chip_sw_lc_ctrl_transition.2671562712 |
|
|
Mar 17 04:12:35 PM PDT 24 |
Mar 17 04:28:25 PM PDT 24 |
11468830096 ps |
| T1067 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.2353840746 |
|
|
Mar 17 03:48:57 PM PDT 24 |
Mar 17 03:52:43 PM PDT 24 |
2816998740 ps |
| T1068 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.2486797883 |
|
|
Mar 17 04:02:49 PM PDT 24 |
Mar 17 04:19:08 PM PDT 24 |
4893440250 ps |
| T1069 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.4265863249 |
|
|
Mar 17 03:45:40 PM PDT 24 |
Mar 17 03:58:18 PM PDT 24 |
7431534744 ps |
| T1070 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.3888213456 |
|
|
Mar 17 04:04:19 PM PDT 24 |
Mar 17 04:53:47 PM PDT 24 |
26005943725 ps |
| T697 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.550621456 |
|
|
Mar 17 03:51:05 PM PDT 24 |
Mar 17 07:20:42 PM PDT 24 |
255540189752 ps |
| T1071 |
/workspace/coverage/default/8.chip_sw_lc_ctrl_transition.2199616590 |
|
|
Mar 17 04:11:47 PM PDT 24 |
Mar 17 04:18:51 PM PDT 24 |
6126393512 ps |
| T1072 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.1734810891 |
|
|
Mar 17 03:55:20 PM PDT 24 |
Mar 17 04:28:49 PM PDT 24 |
9017296220 ps |
| T1073 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2141658605 |
|
|
Mar 17 03:53:16 PM PDT 24 |
Mar 17 04:12:29 PM PDT 24 |
5254495569 ps |
| T1074 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.1674106648 |
|
|
Mar 17 04:08:23 PM PDT 24 |
Mar 17 04:13:42 PM PDT 24 |
2460756280 ps |
| T310 |
/workspace/coverage/default/1.chip_sw_i2c_device_tx_rx.3209141431 |
|
|
Mar 17 03:52:09 PM PDT 24 |
Mar 17 03:59:55 PM PDT 24 |
3697624410 ps |
| T669 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.914969325 |
|
|
Mar 17 03:50:05 PM PDT 24 |
Mar 17 04:56:21 PM PDT 24 |
24364482972 ps |
| T421 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.757647269 |
|
|
Mar 17 04:04:32 PM PDT 24 |
Mar 17 04:21:30 PM PDT 24 |
6238558268 ps |
| T1075 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.1392732689 |
|
|
Mar 17 04:07:53 PM PDT 24 |
Mar 17 04:18:38 PM PDT 24 |
3763396156 ps |
| T744 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.1716930625 |
|
|
Mar 17 04:17:04 PM PDT 24 |
Mar 17 04:22:40 PM PDT 24 |
4055647050 ps |
| T1076 |
/workspace/coverage/default/1.chip_sw_aes_entropy.2470544925 |
|
|
Mar 17 03:55:07 PM PDT 24 |
Mar 17 03:57:59 PM PDT 24 |
2915865460 ps |
| T1077 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2117537942 |
|
|
Mar 17 03:54:52 PM PDT 24 |
Mar 17 04:00:28 PM PDT 24 |
3359825202 ps |
| T1078 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_kmac.2246307080 |
|
|
Mar 17 03:49:03 PM PDT 24 |
Mar 17 03:58:53 PM PDT 24 |
5021851200 ps |
| T1079 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.546957720 |
|
|
Mar 17 03:53:14 PM PDT 24 |
Mar 17 04:27:18 PM PDT 24 |
8975232249 ps |
| T399 |
/workspace/coverage/default/1.chip_sw_rom_ctrl_integrity_check.961317204 |
|
|
Mar 17 03:55:16 PM PDT 24 |
Mar 17 04:03:48 PM PDT 24 |
9267709355 ps |
| T1080 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.11859576 |
|
|
Mar 17 03:47:57 PM PDT 24 |
Mar 17 04:07:42 PM PDT 24 |
7371393552 ps |
| T1081 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.782820948 |
|
|
Mar 17 04:19:51 PM PDT 24 |
Mar 17 04:31:08 PM PDT 24 |
4976232904 ps |
| T799 |
/workspace/coverage/default/81.chip_sw_alert_handler_lpg_sleep_mode_alerts.3699865635 |
|
|
Mar 17 04:19:06 PM PDT 24 |
Mar 17 04:25:06 PM PDT 24 |
3768605016 ps |
| T1082 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.2086123888 |
|
|
Mar 17 04:12:40 PM PDT 24 |
Mar 17 04:24:47 PM PDT 24 |
4084268572 ps |
| T362 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.332878375 |
|
|
Mar 17 03:48:57 PM PDT 24 |
Mar 17 04:15:05 PM PDT 24 |
21924663726 ps |
| T670 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.1420743392 |
|
|
Mar 17 03:57:20 PM PDT 24 |
Mar 17 04:53:22 PM PDT 24 |
24747835098 ps |
| T1083 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.1516246199 |
|
|
Mar 17 04:05:46 PM PDT 24 |
Mar 17 04:08:32 PM PDT 24 |
2139127384 ps |
| T298 |
/workspace/coverage/default/2.chip_sw_entropy_src_csrng.3783743072 |
|
|
Mar 17 04:05:56 PM PDT 24 |
Mar 17 04:29:50 PM PDT 24 |
7348080400 ps |
| T1084 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.2983720168 |
|
|
Mar 17 04:04:34 PM PDT 24 |
Mar 17 04:33:12 PM PDT 24 |
7371020684 ps |
| T1085 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.814589709 |
|
|
Mar 17 04:14:41 PM PDT 24 |
Mar 17 04:23:19 PM PDT 24 |
5282574412 ps |
| T120 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.320298344 |
|
|
Mar 17 03:48:16 PM PDT 24 |
Mar 17 04:10:34 PM PDT 24 |
8890978548 ps |
| T1086 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2830397079 |
|
|
Mar 17 04:11:18 PM PDT 24 |
Mar 17 04:42:13 PM PDT 24 |
8394254767 ps |
| T788 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.923818379 |
|
|
Mar 17 04:17:27 PM PDT 24 |
Mar 17 04:22:12 PM PDT 24 |
3878341230 ps |
| T1087 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.50726930 |
|
|
Mar 17 04:12:27 PM PDT 24 |
Mar 17 04:19:30 PM PDT 24 |
4079585196 ps |
| T228 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.3353478181 |
|
|
Mar 17 04:17:05 PM PDT 24 |
Mar 17 04:27:05 PM PDT 24 |
5219351436 ps |
| T227 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3398189757 |
|
|
Mar 17 04:18:30 PM PDT 24 |
Mar 17 04:26:58 PM PDT 24 |
5840820750 ps |
| T163 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.1987499783 |
|
|
Mar 17 03:49:32 PM PDT 24 |
Mar 17 03:53:23 PM PDT 24 |
2211061990 ps |
| T267 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.3288780805 |
|
|
Mar 17 03:47:15 PM PDT 24 |
Mar 17 03:56:41 PM PDT 24 |
18371758084 ps |
| T191 |
/workspace/coverage/default/1.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.752995661 |
|
|
Mar 17 03:57:39 PM PDT 24 |
Mar 17 04:06:31 PM PDT 24 |
3896699072 ps |
| T268 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.1331449474 |
|
|
Mar 17 03:47:11 PM PDT 24 |
Mar 17 04:17:14 PM PDT 24 |
32601623760 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.4085388448 |
|
|
Mar 17 04:01:27 PM PDT 24 |
Mar 17 04:07:02 PM PDT 24 |
3631386568 ps |
| T269 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.4153421343 |
|
|
Mar 17 04:20:03 PM PDT 24 |
Mar 17 04:25:45 PM PDT 24 |
3540986884 ps |
| T270 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.1755540587 |
|
|
Mar 17 04:14:40 PM PDT 24 |
Mar 17 04:22:51 PM PDT 24 |
4215632198 ps |
| T271 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.3611046636 |
|
|
Mar 17 04:12:58 PM PDT 24 |
Mar 17 04:24:57 PM PDT 24 |
5815409734 ps |
| T1088 |
/workspace/coverage/default/1.chip_sw_kmac_idle.415781040 |
|
|
Mar 17 03:56:01 PM PDT 24 |
Mar 17 04:00:23 PM PDT 24 |
2325218712 ps |
| T1089 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2667402725 |
|
|
Mar 17 03:55:13 PM PDT 24 |
Mar 17 04:04:37 PM PDT 24 |
4847528588 ps |
| T702 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1948859907 |
|
|
Mar 17 03:58:38 PM PDT 24 |
Mar 17 04:04:56 PM PDT 24 |
4486997320 ps |
| T811 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.2874661761 |
|
|
Mar 17 04:17:35 PM PDT 24 |
Mar 17 04:25:59 PM PDT 24 |
4369151720 ps |
| T1090 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.1994178262 |
|
|
Mar 17 04:01:11 PM PDT 24 |
Mar 17 04:06:00 PM PDT 24 |
2477479688 ps |
| T1091 |
/workspace/coverage/default/2.rom_e2e_static_critical.540382657 |
|
|
Mar 17 04:12:56 PM PDT 24 |
Mar 17 04:46:27 PM PDT 24 |
10140510048 ps |
| T1092 |
/workspace/coverage/default/2.chip_sw_power_sleep_load.3334935767 |
|
|
Mar 17 04:09:26 PM PDT 24 |
Mar 17 04:20:37 PM PDT 24 |
10645868392 ps |
| T287 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.2887725353 |
|
|
Mar 17 04:10:07 PM PDT 24 |
Mar 17 04:42:34 PM PDT 24 |
12567884387 ps |
| T1093 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1728634274 |
|
|
Mar 17 04:05:48 PM PDT 24 |
Mar 17 04:10:36 PM PDT 24 |
3209473114 ps |
| T734 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.3608111452 |
|
|
Mar 17 04:03:54 PM PDT 24 |
Mar 17 04:26:17 PM PDT 24 |
23745401512 ps |
| T1094 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.871717866 |
|
|
Mar 17 03:57:10 PM PDT 24 |
Mar 17 07:05:41 PM PDT 24 |
255452833280 ps |
| T802 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.1013965903 |
|
|
Mar 17 04:14:03 PM PDT 24 |
Mar 17 04:21:45 PM PDT 24 |
3795881276 ps |
| T703 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2133928440 |
|
|
Mar 17 03:52:06 PM PDT 24 |
Mar 17 03:58:32 PM PDT 24 |
4523230280 ps |
| T1095 |
/workspace/coverage/default/11.chip_sw_all_escalation_resets.968508883 |
|
|
Mar 17 04:11:17 PM PDT 24 |
Mar 17 04:21:22 PM PDT 24 |
5895858628 ps |
| T290 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.3069521663 |
|
|
Mar 17 03:49:10 PM PDT 24 |
Mar 17 04:01:46 PM PDT 24 |
4124445270 ps |
| T1096 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.377321252 |
|
|
Mar 17 04:12:34 PM PDT 24 |
Mar 17 04:19:39 PM PDT 24 |
2709668252 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.2130978838 |
|
|
Mar 17 03:54:00 PM PDT 24 |
Mar 17 04:08:09 PM PDT 24 |
4998697575 ps |
| T1098 |
/workspace/coverage/default/0.chip_sw_clkmgr_sleep_frequency.3953151442 |
|
|
Mar 17 03:48:22 PM PDT 24 |
Mar 17 03:59:11 PM PDT 24 |
4569820072 ps |
| T213 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.3698925891 |
|
|
Mar 17 04:03:30 PM PDT 24 |
Mar 17 05:28:39 PM PDT 24 |
49518031980 ps |
| T261 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.2354370534 |
|
|
Mar 17 04:05:48 PM PDT 24 |
Mar 17 04:16:43 PM PDT 24 |
5443825000 ps |
| T828 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1803386149 |
|
|
Mar 17 04:13:20 PM PDT 24 |
Mar 17 04:23:51 PM PDT 24 |
4708127048 ps |
| T1099 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1802106304 |
|
|
Mar 17 04:14:23 PM PDT 24 |
Mar 17 04:24:09 PM PDT 24 |
5784977400 ps |
| T138 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.2010398272 |
|
|
Mar 17 03:48:57 PM PDT 24 |
Mar 17 03:52:45 PM PDT 24 |
2626530608 ps |
| T780 |
/workspace/coverage/default/87.chip_sw_alert_handler_lpg_sleep_mode_alerts.561665697 |
|
|
Mar 17 04:18:34 PM PDT 24 |
Mar 17 04:24:33 PM PDT 24 |
3780451200 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.2040344815 |
|
|
Mar 17 03:59:57 PM PDT 24 |
Mar 17 04:03:50 PM PDT 24 |
2813379434 ps |
| T791 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.814825109 |
|
|
Mar 17 04:01:32 PM PDT 24 |
Mar 17 04:13:29 PM PDT 24 |
6078656362 ps |
| T1101 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1188545700 |
|
|
Mar 17 03:57:38 PM PDT 24 |
Mar 17 04:10:10 PM PDT 24 |
6502357950 ps |
| T1102 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.1102927783 |
|
|
Mar 17 03:55:13 PM PDT 24 |
Mar 17 03:59:15 PM PDT 24 |
3433933688 ps |
| T51 |
/workspace/coverage/default/0.chip_sw_alert_test.505130756 |
|
|
Mar 17 03:50:48 PM PDT 24 |
Mar 17 03:57:35 PM PDT 24 |
3069843090 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.2833325130 |
|
|
Mar 17 03:48:49 PM PDT 24 |
Mar 17 04:05:13 PM PDT 24 |
8623770120 ps |
| T1104 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.4103574822 |
|
|
Mar 17 04:12:08 PM PDT 24 |
Mar 17 04:21:36 PM PDT 24 |
4361045364 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3317356867 |
|
|
Mar 17 04:01:57 PM PDT 24 |
Mar 17 05:21:17 PM PDT 24 |
47204059895 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.2177915025 |
|
|
Mar 17 04:06:25 PM PDT 24 |
Mar 17 04:09:48 PM PDT 24 |
2259182409 ps |
| T1107 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.3998816961 |
|
|
Mar 17 04:18:13 PM PDT 24 |
Mar 17 04:27:07 PM PDT 24 |
5153981848 ps |
| T1108 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.3395652428 |
|
|
Mar 17 04:13:07 PM PDT 24 |
Mar 17 04:22:43 PM PDT 24 |
4319011664 ps |
| T795 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.111612987 |
|
|
Mar 17 04:18:57 PM PDT 24 |
Mar 17 04:26:26 PM PDT 24 |
5044279192 ps |
| T312 |
/workspace/coverage/default/0.chip_sival_flash_info_access.2247848658 |
|
|
Mar 17 03:47:36 PM PDT 24 |
Mar 17 03:51:57 PM PDT 24 |
3441769474 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.1015681333 |
|
|
Mar 17 04:07:30 PM PDT 24 |
Mar 17 04:16:18 PM PDT 24 |
7298041900 ps |
| T792 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3814642906 |
|
|
Mar 17 04:10:54 PM PDT 24 |
Mar 17 04:18:58 PM PDT 24 |
4354316200 ps |
| T1110 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.2211882634 |
|
|
Mar 17 04:13:24 PM PDT 24 |
Mar 17 04:34:29 PM PDT 24 |
7286778151 ps |
| T318 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.503923374 |
|
|
Mar 17 04:06:30 PM PDT 24 |
Mar 17 04:14:44 PM PDT 24 |
17645175624 ps |
| T1111 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency_reduced_freq.4213442434 |
|
|
Mar 17 03:50:03 PM PDT 24 |
Mar 17 04:28:13 PM PDT 24 |
12197182357 ps |
| T192 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.1584362804 |
|
|
Mar 17 04:07:49 PM PDT 24 |
Mar 17 04:16:43 PM PDT 24 |
4418764104 ps |
| T208 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_aes.2698165227 |
|
|
Mar 17 03:55:46 PM PDT 24 |
Mar 17 04:01:55 PM PDT 24 |
3362159104 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.3827322882 |
|
|
Mar 17 03:55:59 PM PDT 24 |
Mar 17 05:18:16 PM PDT 24 |
47429642868 ps |
| T403 |
/workspace/coverage/default/93.chip_sw_all_escalation_resets.3598824055 |
|
|
Mar 17 04:18:25 PM PDT 24 |
Mar 17 04:26:17 PM PDT 24 |
4265894584 ps |
| T52 |
/workspace/coverage/default/1.chip_sw_alert_test.4228285377 |
|
|
Mar 17 03:54:53 PM PDT 24 |
Mar 17 03:59:33 PM PDT 24 |
2872457518 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.482113026 |
|
|
Mar 17 04:03:51 PM PDT 24 |
Mar 17 04:12:43 PM PDT 24 |
7501621368 ps |
| T773 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2583668547 |
|
|
Mar 17 04:17:12 PM PDT 24 |
Mar 17 04:23:37 PM PDT 24 |
3768607720 ps |
| T1113 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1533439649 |
|
|
Mar 17 04:02:35 PM PDT 24 |
Mar 17 04:10:56 PM PDT 24 |
3490325028 ps |
| T1114 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.2966132048 |
|
|
Mar 17 04:02:01 PM PDT 24 |
Mar 17 04:15:48 PM PDT 24 |
5580512441 ps |
| T1115 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.3548772665 |
|
|
Mar 17 03:48:43 PM PDT 24 |
Mar 17 03:58:37 PM PDT 24 |
4567419038 ps |
| T1116 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.45693719 |
|
|
Mar 17 03:47:20 PM PDT 24 |
Mar 17 03:52:39 PM PDT 24 |
2986861168 ps |
| T736 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.1069159733 |
|
|
Mar 17 03:55:09 PM PDT 24 |
Mar 17 04:07:15 PM PDT 24 |
4566138440 ps |
| T1117 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.265313643 |
|
|
Mar 17 03:51:21 PM PDT 24 |
Mar 17 06:51:53 PM PDT 24 |
62646912935 ps |
| T1118 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.82942016 |
|
|
Mar 17 03:57:20 PM PDT 24 |
Mar 17 04:03:16 PM PDT 24 |
3552937848 ps |
| T797 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.1294284244 |
|
|
Mar 17 04:15:02 PM PDT 24 |
Mar 17 04:27:55 PM PDT 24 |
4486182370 ps |
| T1119 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.64948694 |
|
|
Mar 17 03:50:25 PM PDT 24 |
Mar 17 03:52:13 PM PDT 24 |
3043095217 ps |
| T774 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.3984601457 |
|
|
Mar 17 04:11:51 PM PDT 24 |
Mar 17 04:19:38 PM PDT 24 |
3253453878 ps |
| T1120 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.1870426139 |
|
|
Mar 17 04:07:01 PM PDT 24 |
Mar 17 04:16:02 PM PDT 24 |
4408017068 ps |
| T787 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.1925287038 |
|
|
Mar 17 04:15:53 PM PDT 24 |
Mar 17 04:27:01 PM PDT 24 |
5278181672 ps |
| T680 |
/workspace/coverage/default/3.chip_tap_straps_dev.2488237245 |
|
|
Mar 17 04:09:40 PM PDT 24 |
Mar 17 04:29:02 PM PDT 24 |
9832563378 ps |
| T229 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.26927339 |
|
|
Mar 17 04:14:58 PM PDT 24 |
Mar 17 04:21:41 PM PDT 24 |
4188429856 ps |
| T1121 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.3771334743 |
|
|
Mar 17 04:19:50 PM PDT 24 |
Mar 17 04:29:15 PM PDT 24 |
4952208520 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4160398307 |
|
|
Mar 17 04:04:55 PM PDT 24 |
Mar 17 04:13:48 PM PDT 24 |
3551709716 ps |
| T1123 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2283211253 |
|
|
Mar 17 03:50:00 PM PDT 24 |
Mar 17 04:23:36 PM PDT 24 |
9002895388 ps |
| T1124 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1691593883 |
|
|
Mar 17 04:18:03 PM PDT 24 |
Mar 17 04:24:04 PM PDT 24 |
3834733320 ps |
| T1125 |
/workspace/coverage/default/19.chip_sw_uart_rand_baudrate.854972584 |
|
|
Mar 17 04:14:44 PM PDT 24 |
Mar 17 04:27:47 PM PDT 24 |
4997703340 ps |
| T1126 |
/workspace/coverage/default/0.chip_sw_example_flash.2935776992 |
|
|
Mar 17 03:52:21 PM PDT 24 |
Mar 17 03:55:52 PM PDT 24 |
2623774040 ps |
| T1127 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.1495941765 |
|
|
Mar 17 03:59:05 PM PDT 24 |
Mar 17 04:03:07 PM PDT 24 |
3327933731 ps |
| T826 |
/workspace/coverage/default/13.chip_sw_alert_handler_lpg_sleep_mode_alerts.2649631864 |
|
|
Mar 17 04:12:40 PM PDT 24 |
Mar 17 04:18:58 PM PDT 24 |
3661363340 ps |
| T1128 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.3790111761 |
|
|
Mar 17 04:09:55 PM PDT 24 |
Mar 17 04:15:15 PM PDT 24 |
5755217824 ps |
| T728 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.1038396718 |
|
|
Mar 17 04:05:02 PM PDT 24 |
Mar 17 04:21:43 PM PDT 24 |
4846649956 ps |
| T1129 |
/workspace/coverage/default/1.chip_sw_flash_init.4026850583 |
|
|
Mar 17 03:58:11 PM PDT 24 |
Mar 17 04:29:01 PM PDT 24 |
23651974250 ps |
| T784 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.4058293024 |
|
|
Mar 17 04:16:12 PM PDT 24 |
Mar 17 04:24:17 PM PDT 24 |
4267169040 ps |
| T1130 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.961921970 |
|
|
Mar 17 03:47:44 PM PDT 24 |
Mar 17 03:56:56 PM PDT 24 |
6419487500 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_uart_smoketest_signed.2554980728 |
|
|
Mar 17 04:11:50 PM PDT 24 |
Mar 17 04:43:10 PM PDT 24 |
8766287000 ps |
| T1132 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.2416527166 |
|
|
Mar 17 04:01:42 PM PDT 24 |
Mar 17 04:05:48 PM PDT 24 |
2910129554 ps |
| T809 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.2534021368 |
|
|
Mar 17 04:20:48 PM PDT 24 |
Mar 17 04:26:36 PM PDT 24 |
3676331640 ps |
| T422 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.4121234638 |
|
|
Mar 17 04:03:31 PM PDT 24 |
Mar 17 04:14:06 PM PDT 24 |
3756382472 ps |
| T804 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.3645798741 |
|
|
Mar 17 04:15:39 PM PDT 24 |
Mar 17 04:26:41 PM PDT 24 |
5882462954 ps |
| T722 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.3431048529 |
|
|
Mar 17 03:54:57 PM PDT 24 |
Mar 17 04:11:35 PM PDT 24 |
5355002060 ps |
| T1133 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.1133337225 |
|
|
Mar 17 04:11:04 PM PDT 24 |
Mar 17 04:13:11 PM PDT 24 |
2231944800 ps |
| T1134 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.4073876361 |
|
|
Mar 17 04:01:16 PM PDT 24 |
Mar 17 04:05:18 PM PDT 24 |
3031918916 ps |
| T321 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.330084847 |
|
|
Mar 17 03:54:05 PM PDT 24 |
Mar 17 04:02:34 PM PDT 24 |
3645856794 ps |
| T1135 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.3285305580 |
|
|
Mar 17 04:10:50 PM PDT 24 |
Mar 17 04:18:18 PM PDT 24 |
6223450034 ps |
| T1136 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2866971736 |
|
|
Mar 17 04:03:54 PM PDT 24 |
Mar 17 04:13:22 PM PDT 24 |
6601589522 ps |
| T291 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2006868739 |
|
|
Mar 17 04:03:22 PM PDT 24 |
Mar 17 04:14:24 PM PDT 24 |
4601109338 ps |
| T1137 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.777227421 |
|
|
Mar 17 04:15:57 PM PDT 24 |
Mar 17 04:26:23 PM PDT 24 |
5486905870 ps |
| T1138 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.3917503370 |
|
|
Mar 17 04:01:10 PM PDT 24 |
Mar 17 04:06:21 PM PDT 24 |
3445062648 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.3320027073 |
|
|
Mar 17 04:06:10 PM PDT 24 |
Mar 17 04:13:42 PM PDT 24 |
3810571856 ps |
| T1140 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.3255130024 |
|
|
Mar 17 04:14:26 PM PDT 24 |
Mar 17 04:20:36 PM PDT 24 |
3728141072 ps |
| T1141 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_alt_clk_freq.26381716 |
|
|
Mar 17 03:51:35 PM PDT 24 |
Mar 17 04:03:25 PM PDT 24 |
4188595525 ps |
| T1142 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.1514097971 |
|
|
Mar 17 03:51:33 PM PDT 24 |
Mar 17 04:16:24 PM PDT 24 |
7482564528 ps |
| T1143 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.2528755501 |
|
|
Mar 17 03:56:24 PM PDT 24 |
Mar 17 04:31:59 PM PDT 24 |
8354311678 ps |
| T1144 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1997377013 |
|
|
Mar 17 04:12:37 PM PDT 24 |
Mar 17 04:29:10 PM PDT 24 |
11523038150 ps |
| T781 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.3763070529 |
|
|
Mar 17 04:13:33 PM PDT 24 |
Mar 17 04:21:57 PM PDT 24 |
5872802180 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.2228158083 |
|
|
Mar 17 03:52:21 PM PDT 24 |
Mar 17 03:58:39 PM PDT 24 |
3207870964 ps |
| T165 |
/workspace/coverage/default/0.chip_jtag_csr_rw.4172600105 |
|
|
Mar 17 03:40:31 PM PDT 24 |
Mar 17 04:00:59 PM PDT 24 |
11872035503 ps |
| T681 |
/workspace/coverage/default/4.chip_tap_straps_dev.1323624552 |
|
|
Mar 17 04:10:08 PM PDT 24 |
Mar 17 04:24:22 PM PDT 24 |
10535978216 ps |
| T1145 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3498170121 |
|
|
Mar 17 03:49:32 PM PDT 24 |
Mar 17 03:59:06 PM PDT 24 |
4759064104 ps |
| T1146 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.922797051 |
|
|
Mar 17 04:06:59 PM PDT 24 |
Mar 17 04:11:26 PM PDT 24 |
2769952741 ps |
| T1147 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.920992030 |
|
|
Mar 17 03:51:07 PM PDT 24 |
Mar 17 04:02:35 PM PDT 24 |
10512302835 ps |
| T737 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.1173028210 |
|
|
Mar 17 04:12:41 PM PDT 24 |
Mar 17 04:26:00 PM PDT 24 |
4989693200 ps |
| T1148 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_power_glitch_reset.2350105739 |
|
|
Mar 17 03:51:36 PM PDT 24 |
Mar 17 04:41:49 PM PDT 24 |
28726321958 ps |
| T771 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040597339 |
|
|
Mar 17 04:17:58 PM PDT 24 |
Mar 17 04:24:07 PM PDT 24 |
3114311016 ps |
| T1149 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.4078663722 |
|
|
Mar 17 04:05:30 PM PDT 24 |
Mar 17 04:15:44 PM PDT 24 |
4483035112 ps |
| T776 |
/workspace/coverage/default/55.chip_sw_alert_handler_lpg_sleep_mode_alerts.888012582 |
|
|
Mar 17 04:20:02 PM PDT 24 |
Mar 17 04:27:06 PM PDT 24 |
3276726268 ps |
| T1150 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.2841075042 |
|
|
Mar 17 04:10:53 PM PDT 24 |
Mar 17 04:41:07 PM PDT 24 |
13967723453 ps |
| T1151 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.3502567180 |
|
|
Mar 17 04:07:12 PM PDT 24 |
Mar 17 04:14:45 PM PDT 24 |
3446829000 ps |
| T209 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.1123424348 |
|
|
Mar 17 03:52:45 PM PDT 24 |
Mar 17 04:00:46 PM PDT 24 |
4352990712 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en.4247292791 |
|
|
Mar 17 03:48:34 PM PDT 24 |
Mar 17 03:54:28 PM PDT 24 |
2427890367 ps |
| T671 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2583905724 |
|
|
Mar 17 03:55:33 PM PDT 24 |
Mar 17 04:23:08 PM PDT 24 |
5780086204 ps |
| T1153 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.118489954 |
|
|
Mar 17 04:16:11 PM PDT 24 |
Mar 17 04:21:55 PM PDT 24 |
3029323160 ps |
| T1154 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.871883048 |
|
|
Mar 17 03:49:14 PM PDT 24 |
Mar 17 03:59:32 PM PDT 24 |
6134451808 ps |
| T296 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.177085999 |
|
|
Mar 17 03:49:07 PM PDT 24 |
Mar 17 04:03:41 PM PDT 24 |
4679671400 ps |
| T814 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.426102297 |
|
|
Mar 17 04:15:47 PM PDT 24 |
Mar 17 04:24:47 PM PDT 24 |
4969040856 ps |
| T1155 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.130373346 |
|
|
Mar 17 04:02:48 PM PDT 24 |
Mar 17 04:19:33 PM PDT 24 |
5460981726 ps |
| T1156 |
/workspace/coverage/default/0.chip_sw_aes_idle.2608651461 |
|
|
Mar 17 03:49:41 PM PDT 24 |
Mar 17 03:53:56 PM PDT 24 |
2707998328 ps |
| T1157 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.4008240148 |
|
|
Mar 17 03:52:48 PM PDT 24 |
Mar 17 04:36:06 PM PDT 24 |
24250895239 ps |
| T1158 |
/workspace/coverage/default/2.chip_sw_kmac_idle.543746445 |
|
|
Mar 17 04:11:17 PM PDT 24 |
Mar 17 04:15:17 PM PDT 24 |
3490769872 ps |
| T777 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.738431591 |
|
|
Mar 17 04:20:56 PM PDT 24 |
Mar 17 04:26:35 PM PDT 24 |
3023559240 ps |
| T1159 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.1390579247 |
|
|
Mar 17 03:53:35 PM PDT 24 |
Mar 17 03:59:35 PM PDT 24 |
4436755312 ps |
| T1160 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2376807013 |
|
|
Mar 17 03:47:13 PM PDT 24 |
Mar 17 04:17:54 PM PDT 24 |
17915530631 ps |
| T371 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1635944812 |
|
|
Mar 17 03:48:11 PM PDT 24 |
Mar 17 03:55:55 PM PDT 24 |
7228265710 ps |
| T46 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.990066944 |
|
|
Mar 17 03:46:54 PM PDT 24 |
Mar 17 03:54:34 PM PDT 24 |
4971857832 ps |
| T1161 |
/workspace/coverage/default/0.chip_sw_kmac_idle.2933928216 |
|
|
Mar 17 03:51:50 PM PDT 24 |
Mar 17 03:55:24 PM PDT 24 |
3273678896 ps |
| T729 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2044314369 |
|
|
Mar 17 03:46:40 PM PDT 24 |
Mar 17 04:01:59 PM PDT 24 |
4575995160 ps |
| T810 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.2420823746 |
|
|
Mar 17 04:21:08 PM PDT 24 |
Mar 17 04:27:00 PM PDT 24 |
3547916860 ps |
| T1162 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.913311441 |
|
|
Mar 17 04:05:54 PM PDT 24 |
Mar 17 04:19:55 PM PDT 24 |
7128638656 ps |
| T1163 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.1090084784 |
|
|
Mar 17 03:51:17 PM PDT 24 |
Mar 17 03:54:58 PM PDT 24 |
3049724017 ps |
| T1164 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.3167566095 |
|
|
Mar 17 04:07:27 PM PDT 24 |
Mar 17 04:46:59 PM PDT 24 |
12613794600 ps |
| T1165 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2549225379 |
|
|
Mar 17 03:47:18 PM PDT 24 |
Mar 17 03:57:26 PM PDT 24 |
4036594040 ps |
| T319 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1265441356 |
|
|
Mar 17 03:54:54 PM PDT 24 |
Mar 17 04:06:02 PM PDT 24 |
19631733400 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.1880286443 |
|
|
Mar 17 04:07:22 PM PDT 24 |
Mar 17 04:41:39 PM PDT 24 |
11264940004 ps |
| T1167 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3979730798 |
|
|
Mar 17 04:09:11 PM PDT 24 |
Mar 17 04:13:19 PM PDT 24 |
2675151070 ps |
| T288 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.2132723717 |
|
|
Mar 17 03:56:07 PM PDT 24 |
Mar 17 04:14:29 PM PDT 24 |
5825623396 ps |
| T1168 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.872359804 |
|
|
Mar 17 03:52:16 PM PDT 24 |
Mar 17 04:03:00 PM PDT 24 |
4869131404 ps |
| T1169 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.4270653798 |
|
|
Mar 17 03:57:55 PM PDT 24 |
Mar 17 04:06:48 PM PDT 24 |
3588353000 ps |
| T1170 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.1511902684 |
|
|
Mar 17 03:52:46 PM PDT 24 |
Mar 17 04:11:20 PM PDT 24 |
5656163748 ps |
| T124 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.206450566 |
|
|
Mar 17 04:02:36 PM PDT 24 |
Mar 17 04:04:12 PM PDT 24 |
2031713516 ps |
| T1171 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.822974867 |
|
|
Mar 17 04:12:14 PM PDT 24 |
Mar 17 05:05:10 PM PDT 24 |
22716625013 ps |
| T1172 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.810530186 |
|
|
Mar 17 04:06:57 PM PDT 24 |
Mar 17 04:18:14 PM PDT 24 |
4449355180 ps |
| T1173 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2278264905 |
|
|
Mar 17 03:45:38 PM PDT 24 |
Mar 17 04:17:37 PM PDT 24 |
14574123626 ps |
| T1174 |
/workspace/coverage/default/0.chip_sw_rv_timer_smoketest.1998956874 |
|
|
Mar 17 03:54:46 PM PDT 24 |
Mar 17 03:59:47 PM PDT 24 |
2838169208 ps |
| T139 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.1388754412 |
|
|
Mar 17 04:08:33 PM PDT 24 |
Mar 17 04:12:24 PM PDT 24 |
3175608702 ps |
| T1175 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.2085141982 |
|
|
Mar 17 03:54:04 PM PDT 24 |
Mar 17 03:59:37 PM PDT 24 |
3471345470 ps |
| T1176 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.3536463725 |
|
|
Mar 17 04:10:55 PM PDT 24 |
Mar 17 04:17:12 PM PDT 24 |
3635624224 ps |
| T769 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.3201370191 |
|
|
Mar 17 04:14:02 PM PDT 24 |
Mar 17 04:20:02 PM PDT 24 |
3700784484 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.81485363 |
|
|
Mar 17 04:07:25 PM PDT 24 |
Mar 17 04:17:48 PM PDT 24 |
5096236882 ps |
| T821 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.1665240132 |
|
|
Mar 17 04:19:26 PM PDT 24 |
Mar 17 04:30:17 PM PDT 24 |
6064793786 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_aes_entropy.814072452 |
|
|
Mar 17 04:06:17 PM PDT 24 |
Mar 17 04:10:09 PM PDT 24 |
2236285368 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2749299342 |
|
|
Mar 17 03:48:08 PM PDT 24 |
Mar 17 03:56:33 PM PDT 24 |
5244180120 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_example_concurrency.2966727422 |
|
|
Mar 17 03:52:41 PM PDT 24 |
Mar 17 03:57:09 PM PDT 24 |
3092768496 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2615186113 |
|
|
Mar 17 03:50:45 PM PDT 24 |
Mar 17 03:53:26 PM PDT 24 |
1951490646 ps |
| T699 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.948399053 |
|
|
Mar 17 04:17:07 PM PDT 24 |
Mar 17 04:25:06 PM PDT 24 |
4137327624 ps |
| T1181 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.4116452011 |
|
|
Mar 17 03:54:17 PM PDT 24 |
Mar 17 04:01:33 PM PDT 24 |
3843712189 ps |
| T1182 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.924733701 |
|
|
Mar 17 04:09:09 PM PDT 24 |
Mar 17 04:15:56 PM PDT 24 |
3043780728 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.2525881871 |
|
|
Mar 17 04:12:21 PM PDT 24 |
Mar 17 04:20:44 PM PDT 24 |
5314486104 ps |
| T410 |
/workspace/coverage/default/0.chip_jtag_mem_access.1008005793 |
|
|
Mar 17 03:40:39 PM PDT 24 |
Mar 17 04:04:32 PM PDT 24 |
13609304168 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2276957537 |
|
|
Mar 17 04:07:43 PM PDT 24 |
Mar 17 04:17:21 PM PDT 24 |
4620666810 ps |
| T193 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2907554465 |
|
|
Mar 17 03:48:30 PM PDT 24 |
Mar 17 03:56:12 PM PDT 24 |
4346012632 ps |
| T1185 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.1720771734 |
|
|
Mar 17 04:17:34 PM PDT 24 |
Mar 17 04:24:09 PM PDT 24 |
3814154530 ps |
| T1186 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.2941545982 |
|
|
Mar 17 04:04:36 PM PDT 24 |
Mar 17 04:22:07 PM PDT 24 |
7473561792 ps |
| T1187 |
/workspace/coverage/default/1.chip_sw_power_idle_load.3807643929 |
|
|
Mar 17 03:59:26 PM PDT 24 |
Mar 17 04:09:53 PM PDT 24 |
4144219244 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.1052017296 |
|
|
Mar 17 04:08:59 PM PDT 24 |
Mar 17 04:16:00 PM PDT 24 |
2842955550 ps |
| T1189 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.1791570238 |
|
|
Mar 17 04:12:20 PM PDT 24 |
Mar 17 05:05:10 PM PDT 24 |
23301986104 ps |
| T1190 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2881425111 |
|
|
Mar 17 03:46:02 PM PDT 24 |
Mar 17 04:04:16 PM PDT 24 |
5813432535 ps |
| T785 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2484556887 |
|
|
Mar 17 04:17:28 PM PDT 24 |
Mar 17 04:23:24 PM PDT 24 |
4400027400 ps |
| T36 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.625558860 |
|
|
Mar 17 03:54:14 PM PDT 24 |
Mar 17 04:01:14 PM PDT 24 |
3122024306 ps |
| T519 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2214594782 |
|
|
Mar 17 04:00:05 PM PDT 24 |
Mar 17 04:10:06 PM PDT 24 |
3902357813 ps |
| T1191 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.2700398393 |
|
|
Mar 17 03:48:48 PM PDT 24 |
Mar 17 03:52:44 PM PDT 24 |
2810157492 ps |