| T96 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2797761748 |
|
|
Mar 19 03:52:51 PM PDT 24 |
Mar 19 04:01:56 PM PDT 24 |
5983461860 ps |
| T97 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.3059061785 |
|
|
Mar 19 04:00:15 PM PDT 24 |
Mar 19 04:10:50 PM PDT 24 |
4168060144 ps |
| T98 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.2333373520 |
|
|
Mar 19 04:11:04 PM PDT 24 |
Mar 19 04:18:21 PM PDT 24 |
3393041140 ps |
| T99 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.2270733101 |
|
|
Mar 19 03:58:42 PM PDT 24 |
Mar 19 04:07:58 PM PDT 24 |
4337969784 ps |
| T100 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.2599268826 |
|
|
Mar 19 04:05:47 PM PDT 24 |
Mar 19 04:18:54 PM PDT 24 |
4866545336 ps |
| T101 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.1558715216 |
|
|
Mar 19 03:50:08 PM PDT 24 |
Mar 19 04:02:33 PM PDT 24 |
5170580704 ps |
| T70 |
/workspace/coverage/default/0.chip_jtag_mem_access.71266440 |
|
|
Mar 19 03:36:34 PM PDT 24 |
Mar 19 04:02:11 PM PDT 24 |
13079357699 ps |
| T102 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1714637224 |
|
|
Mar 19 04:02:51 PM PDT 24 |
Mar 19 04:16:07 PM PDT 24 |
5062662568 ps |
| T41 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.201294607 |
|
|
Mar 19 04:03:02 PM PDT 24 |
Mar 19 04:10:32 PM PDT 24 |
3843172328 ps |
| T5 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.3514554115 |
|
|
Mar 19 03:49:56 PM PDT 24 |
Mar 19 03:54:09 PM PDT 24 |
2703438860 ps |
| T390 |
/workspace/coverage/default/72.chip_sw_all_escalation_resets.1210800889 |
|
|
Mar 19 04:14:01 PM PDT 24 |
Mar 19 04:26:54 PM PDT 24 |
5441078980 ps |
| T171 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.554511007 |
|
|
Mar 19 03:55:00 PM PDT 24 |
Mar 19 04:06:28 PM PDT 24 |
6106377870 ps |
| T204 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.1258551928 |
|
|
Mar 19 04:05:11 PM PDT 24 |
Mar 19 04:12:00 PM PDT 24 |
4827862702 ps |
| T391 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.2668976852 |
|
|
Mar 19 04:08:53 PM PDT 24 |
Mar 19 04:46:51 PM PDT 24 |
8971729630 ps |
| T54 |
/workspace/coverage/default/0.chip_sw_alert_test.1017854350 |
|
|
Mar 19 03:46:18 PM PDT 24 |
Mar 19 03:51:32 PM PDT 24 |
3053037856 ps |
| T392 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.4177974025 |
|
|
Mar 19 03:47:29 PM PDT 24 |
Mar 19 04:05:49 PM PDT 24 |
5024905078 ps |
| T285 |
/workspace/coverage/default/0.chip_plic_all_irqs_0.108057580 |
|
|
Mar 19 03:48:03 PM PDT 24 |
Mar 19 04:09:17 PM PDT 24 |
6652264220 ps |
| T319 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.1940001340 |
|
|
Mar 19 03:47:03 PM PDT 24 |
Mar 19 03:57:54 PM PDT 24 |
4265293957 ps |
| T789 |
/workspace/coverage/default/47.chip_sw_all_escalation_resets.4028627294 |
|
|
Mar 19 04:10:49 PM PDT 24 |
Mar 19 04:21:31 PM PDT 24 |
5850886356 ps |
| T493 |
/workspace/coverage/default/0.chip_sw_pwrmgr_all_reset_reqs.2513686031 |
|
|
Mar 19 03:47:16 PM PDT 24 |
Mar 19 04:15:51 PM PDT 24 |
11412305956 ps |
| T745 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.1697535120 |
|
|
Mar 19 04:08:46 PM PDT 24 |
Mar 19 04:16:43 PM PDT 24 |
4165227252 ps |
| T685 |
/workspace/coverage/default/24.chip_sw_alert_handler_lpg_sleep_mode_alerts.3216991745 |
|
|
Mar 19 04:10:18 PM PDT 24 |
Mar 19 04:18:44 PM PDT 24 |
3484819372 ps |
| T931 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4206475251 |
|
|
Mar 19 03:57:54 PM PDT 24 |
Mar 19 04:07:59 PM PDT 24 |
5024465278 ps |
| T932 |
/workspace/coverage/default/0.chip_sw_aes_idle.4085645625 |
|
|
Mar 19 03:46:59 PM PDT 24 |
Mar 19 03:51:02 PM PDT 24 |
2452114300 ps |
| T933 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.2760080312 |
|
|
Mar 19 04:02:56 PM PDT 24 |
Mar 19 04:14:22 PM PDT 24 |
4851543070 ps |
| T781 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.3244704476 |
|
|
Mar 19 04:14:23 PM PDT 24 |
Mar 19 04:19:55 PM PDT 24 |
3589334460 ps |
| T266 |
/workspace/coverage/default/2.chip_sw_flash_init.3617040024 |
|
|
Mar 19 03:55:35 PM PDT 24 |
Mar 19 04:32:17 PM PDT 24 |
22058130864 ps |
| T934 |
/workspace/coverage/default/2.chip_sw_edn_kat.2565831647 |
|
|
Mar 19 04:00:41 PM PDT 24 |
Mar 19 04:12:29 PM PDT 24 |
3709914004 ps |
| T311 |
/workspace/coverage/default/0.chip_sw_i2c_device_tx_rx.3449136048 |
|
|
Mar 19 03:47:12 PM PDT 24 |
Mar 19 03:56:19 PM PDT 24 |
3950795308 ps |
| T190 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx1.2118664784 |
|
|
Mar 19 04:07:05 PM PDT 24 |
Mar 19 04:22:30 PM PDT 24 |
5899723243 ps |
| T395 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.3535179884 |
|
|
Mar 19 03:52:28 PM PDT 24 |
Mar 19 03:57:12 PM PDT 24 |
2624479656 ps |
| T137 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.287892585 |
|
|
Mar 19 03:46:28 PM PDT 24 |
Mar 19 03:50:04 PM PDT 24 |
2902600458 ps |
| T935 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.1989432858 |
|
|
Mar 19 03:46:45 PM PDT 24 |
Mar 19 03:49:51 PM PDT 24 |
1980201524 ps |
| T936 |
/workspace/coverage/default/0.chip_sw_hmac_smoketest.1196412732 |
|
|
Mar 19 03:46:02 PM PDT 24 |
Mar 19 03:51:29 PM PDT 24 |
3213860308 ps |
| T662 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.3259999072 |
|
|
Mar 19 03:51:20 PM PDT 24 |
Mar 19 03:53:09 PM PDT 24 |
2108639920 ps |
| T791 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2464026101 |
|
|
Mar 19 04:10:27 PM PDT 24 |
Mar 19 04:25:04 PM PDT 24 |
5903613964 ps |
| T937 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.50748127 |
|
|
Mar 19 03:48:43 PM PDT 24 |
Mar 19 04:06:00 PM PDT 24 |
5509247874 ps |
| T938 |
/workspace/coverage/default/2.chip_sw_rv_timer_smoketest.1940521869 |
|
|
Mar 19 04:07:13 PM PDT 24 |
Mar 19 04:10:56 PM PDT 24 |
2769073300 ps |
| T939 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.3110598972 |
|
|
Mar 19 03:57:55 PM PDT 24 |
Mar 19 04:06:15 PM PDT 24 |
5386093092 ps |
| T741 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.2549499983 |
|
|
Mar 19 04:10:31 PM PDT 24 |
Mar 19 04:15:41 PM PDT 24 |
3056953996 ps |
| T940 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.1160525325 |
|
|
Mar 19 03:46:24 PM PDT 24 |
Mar 19 04:05:09 PM PDT 24 |
5545944007 ps |
| T301 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx2.2701320103 |
|
|
Mar 19 03:46:26 PM PDT 24 |
Mar 19 04:06:45 PM PDT 24 |
5731117120 ps |
| T941 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.54254599 |
|
|
Mar 19 03:47:46 PM PDT 24 |
Mar 19 03:52:11 PM PDT 24 |
3445520634 ps |
| T147 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1897296533 |
|
|
Mar 19 03:47:57 PM PDT 24 |
Mar 19 03:56:15 PM PDT 24 |
4800701226 ps |
| T942 |
/workspace/coverage/default/2.chip_sw_otbn_smoketest.389080874 |
|
|
Mar 19 04:06:21 PM PDT 24 |
Mar 19 04:28:34 PM PDT 24 |
6269094072 ps |
| T943 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.2792181741 |
|
|
Mar 19 03:53:35 PM PDT 24 |
Mar 19 04:13:43 PM PDT 24 |
8256491150 ps |
| T944 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.1984036989 |
|
|
Mar 19 03:58:57 PM PDT 24 |
Mar 19 04:06:26 PM PDT 24 |
3528066940 ps |
| T719 |
/workspace/coverage/default/71.chip_sw_alert_handler_lpg_sleep_mode_alerts.3949557948 |
|
|
Mar 19 04:12:15 PM PDT 24 |
Mar 19 04:22:21 PM PDT 24 |
3984363908 ps |
| T945 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.1392418951 |
|
|
Mar 19 04:07:10 PM PDT 24 |
Mar 19 04:22:33 PM PDT 24 |
7053141788 ps |
| T323 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx1.3425108452 |
|
|
Mar 19 03:54:48 PM PDT 24 |
Mar 19 04:12:19 PM PDT 24 |
5152181398 ps |
| T946 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1385076313 |
|
|
Mar 19 04:07:12 PM PDT 24 |
Mar 19 04:17:58 PM PDT 24 |
8052986296 ps |
| T761 |
/workspace/coverage/default/16.chip_sw_alert_handler_lpg_sleep_mode_alerts.3560813012 |
|
|
Mar 19 04:07:32 PM PDT 24 |
Mar 19 04:13:55 PM PDT 24 |
3843061368 ps |
| T786 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.1245021063 |
|
|
Mar 19 04:10:49 PM PDT 24 |
Mar 19 04:21:49 PM PDT 24 |
4582179756 ps |
| T663 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2401592867 |
|
|
Mar 19 03:56:30 PM PDT 24 |
Mar 19 03:58:04 PM PDT 24 |
1984776288 ps |
| T148 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1310201275 |
|
|
Mar 19 03:50:22 PM PDT 24 |
Mar 19 04:00:51 PM PDT 24 |
5623496685 ps |
| T715 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.350363068 |
|
|
Mar 19 04:13:44 PM PDT 24 |
Mar 19 04:19:28 PM PDT 24 |
3839524322 ps |
| T947 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod_end.2928687207 |
|
|
Mar 19 03:50:51 PM PDT 24 |
Mar 19 04:27:25 PM PDT 24 |
8235223374 ps |
| T948 |
/workspace/coverage/default/3.chip_tap_straps_rma.2294476229 |
|
|
Mar 19 04:05:31 PM PDT 24 |
Mar 19 04:12:09 PM PDT 24 |
5400754796 ps |
| T949 |
/workspace/coverage/default/1.chip_tap_straps_prod.381726737 |
|
|
Mar 19 03:51:14 PM PDT 24 |
Mar 19 03:53:32 PM PDT 24 |
2877766780 ps |
| T950 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_mem_protection.3387306839 |
|
|
Mar 19 03:48:42 PM PDT 24 |
Mar 19 04:08:13 PM PDT 24 |
5778870720 ps |
| T669 |
/workspace/coverage/default/66.chip_sw_all_escalation_resets.1042046554 |
|
|
Mar 19 04:11:04 PM PDT 24 |
Mar 19 04:21:16 PM PDT 24 |
4977614392 ps |
| T288 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx3.4276372646 |
|
|
Mar 19 03:46:42 PM PDT 24 |
Mar 19 04:00:30 PM PDT 24 |
5321640830 ps |
| T40 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_wake_ups.1465451491 |
|
|
Mar 19 04:07:15 PM PDT 24 |
Mar 19 04:15:45 PM PDT 24 |
6854193444 ps |
| T17 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2466605879 |
|
|
Mar 19 04:03:43 PM PDT 24 |
Mar 19 04:26:39 PM PDT 24 |
19791843514 ps |
| T951 |
/workspace/coverage/default/1.rom_e2e_asm_init_rma.2733108178 |
|
|
Mar 19 03:54:59 PM PDT 24 |
Mar 19 04:30:16 PM PDT 24 |
9185723429 ps |
| T952 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.1371284036 |
|
|
Mar 19 04:01:45 PM PDT 24 |
Mar 19 04:13:13 PM PDT 24 |
4262449320 ps |
| T953 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_lc_escalate.1915089951 |
|
|
Mar 19 03:46:58 PM PDT 24 |
Mar 19 03:58:04 PM PDT 24 |
4804457618 ps |
| T304 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2466193932 |
|
|
Mar 19 03:52:35 PM PDT 24 |
Mar 19 03:58:16 PM PDT 24 |
2622969504 ps |
| T738 |
/workspace/coverage/default/83.chip_sw_alert_handler_lpg_sleep_mode_alerts.2781829361 |
|
|
Mar 19 04:14:32 PM PDT 24 |
Mar 19 04:22:16 PM PDT 24 |
3561407720 ps |
| T954 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.144449140 |
|
|
Mar 19 03:54:03 PM PDT 24 |
Mar 19 04:01:03 PM PDT 24 |
3139843560 ps |
| T955 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4236693644 |
|
|
Mar 19 03:56:33 PM PDT 24 |
Mar 19 04:46:43 PM PDT 24 |
12569334606 ps |
| T956 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.497223705 |
|
|
Mar 19 03:52:54 PM PDT 24 |
Mar 19 04:26:17 PM PDT 24 |
8151269578 ps |
| T957 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.1747884321 |
|
|
Mar 19 03:47:06 PM PDT 24 |
Mar 19 04:06:24 PM PDT 24 |
8701992956 ps |
| T157 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.887209372 |
|
|
Mar 19 04:07:49 PM PDT 24 |
Mar 19 04:17:31 PM PDT 24 |
5827820384 ps |
| T94 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_wake_ups.460476988 |
|
|
Mar 19 03:48:28 PM PDT 24 |
Mar 19 04:13:44 PM PDT 24 |
19241692600 ps |
| T185 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_reset_toggle.2075460627 |
|
|
Mar 19 03:49:35 PM PDT 24 |
Mar 19 04:16:59 PM PDT 24 |
7656621538 ps |
| T958 |
/workspace/coverage/default/0.rom_e2e_asm_init_dev.3823291551 |
|
|
Mar 19 03:58:23 PM PDT 24 |
Mar 19 04:34:27 PM PDT 24 |
8965513351 ps |
| T396 |
/workspace/coverage/default/2.chip_sw_rom_ctrl_integrity_check.1035911467 |
|
|
Mar 19 04:02:05 PM PDT 24 |
Mar 19 04:09:47 PM PDT 24 |
8470997233 ps |
| T360 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.1169134892 |
|
|
Mar 19 03:47:25 PM PDT 24 |
Mar 19 03:51:10 PM PDT 24 |
2606499466 ps |
| T766 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.936284290 |
|
|
Mar 19 04:10:50 PM PDT 24 |
Mar 19 04:18:57 PM PDT 24 |
4532628864 ps |
| T117 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_vendor_test_csr_access.2487243370 |
|
|
Mar 19 03:46:24 PM PDT 24 |
Mar 19 03:48:10 PM PDT 24 |
1917066684 ps |
| T959 |
/workspace/coverage/default/15.chip_sw_uart_rand_baudrate.725503136 |
|
|
Mar 19 04:08:39 PM PDT 24 |
Mar 19 04:21:47 PM PDT 24 |
5188966245 ps |
| T325 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.2980553553 |
|
|
Mar 19 04:12:10 PM PDT 24 |
Mar 19 04:22:16 PM PDT 24 |
4455061060 ps |
| T960 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.1013788543 |
|
|
Mar 19 03:47:26 PM PDT 24 |
Mar 19 03:50:14 PM PDT 24 |
1943858303 ps |
| T265 |
/workspace/coverage/default/1.chip_sw_flash_init_reduced_freq.3924651328 |
|
|
Mar 19 03:51:53 PM PDT 24 |
Mar 19 04:26:03 PM PDT 24 |
18942475337 ps |
| T245 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.2988615610 |
|
|
Mar 19 04:02:59 PM PDT 24 |
Mar 19 04:08:06 PM PDT 24 |
2624377172 ps |
| T961 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod.1034315170 |
|
|
Mar 19 03:52:57 PM PDT 24 |
Mar 19 04:46:04 PM PDT 24 |
11925045880 ps |
| T962 |
/workspace/coverage/default/18.chip_sw_uart_rand_baudrate.2602172569 |
|
|
Mar 19 04:07:42 PM PDT 24 |
Mar 19 04:20:57 PM PDT 24 |
5334756500 ps |
| T283 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.542019190 |
|
|
Mar 19 03:48:51 PM PDT 24 |
Mar 19 04:16:48 PM PDT 24 |
11753588008 ps |
| T208 |
/workspace/coverage/default/42.chip_sw_alert_handler_lpg_sleep_mode_alerts.4264824440 |
|
|
Mar 19 04:12:40 PM PDT 24 |
Mar 19 04:19:11 PM PDT 24 |
3627128000 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_usbdev_stream.2898456508 |
|
|
Mar 19 03:50:42 PM PDT 24 |
Mar 19 05:04:06 PM PDT 24 |
18453028200 ps |
| T792 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.1690201623 |
|
|
Mar 19 04:08:00 PM PDT 24 |
Mar 19 04:18:03 PM PDT 24 |
4829794224 ps |
| T963 |
/workspace/coverage/default/0.chip_sw_kmac_entropy.1558444316 |
|
|
Mar 19 03:45:35 PM PDT 24 |
Mar 19 03:51:40 PM PDT 24 |
3115496640 ps |
| T964 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en_reduced_freq.117667554 |
|
|
Mar 19 04:04:55 PM PDT 24 |
Mar 19 04:08:21 PM PDT 24 |
3102128489 ps |
| T965 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.2109224502 |
|
|
Mar 19 04:02:09 PM PDT 24 |
Mar 19 04:09:59 PM PDT 24 |
3387363784 ps |
| T43 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_wake_ups.3715670 |
|
|
Mar 19 04:03:44 PM PDT 24 |
Mar 19 04:29:32 PM PDT 24 |
19064248012 ps |
| T273 |
/workspace/coverage/default/35.chip_sw_all_escalation_resets.82703398 |
|
|
Mar 19 04:10:27 PM PDT 24 |
Mar 19 04:21:59 PM PDT 24 |
5038384040 ps |
| T726 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.583265909 |
|
|
Mar 19 04:10:43 PM PDT 24 |
Mar 19 04:18:50 PM PDT 24 |
4129394650 ps |
| T233 |
/workspace/coverage/default/2.chip_sw_otbn_mem_scramble.4166566592 |
|
|
Mar 19 04:00:06 PM PDT 24 |
Mar 19 04:08:10 PM PDT 24 |
3224593322 ps |
| T274 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.3808137245 |
|
|
Mar 19 04:16:23 PM PDT 24 |
Mar 19 04:26:52 PM PDT 24 |
4787581710 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.2198049073 |
|
|
Mar 19 03:50:31 PM PDT 24 |
Mar 19 04:41:23 PM PDT 24 |
11774787768 ps |
| T966 |
/workspace/coverage/default/0.chip_sw_example_concurrency.3478698782 |
|
|
Mar 19 03:49:35 PM PDT 24 |
Mar 19 03:52:31 PM PDT 24 |
2995387696 ps |
| T967 |
/workspace/coverage/default/1.rom_keymgr_functest.2542623106 |
|
|
Mar 19 03:53:10 PM PDT 24 |
Mar 19 04:01:09 PM PDT 24 |
4774135856 ps |
| T968 |
/workspace/coverage/default/0.chip_tap_straps_prod.1032997691 |
|
|
Mar 19 03:48:32 PM PDT 24 |
Mar 19 03:50:53 PM PDT 24 |
2454934000 ps |
| T326 |
/workspace/coverage/default/0.chip_sw_rstmgr_rst_cnsty_escalation.253803348 |
|
|
Mar 19 03:49:53 PM PDT 24 |
Mar 19 03:58:56 PM PDT 24 |
5613814146 ps |
| T81 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.913643606 |
|
|
Mar 19 04:08:33 PM PDT 24 |
Mar 19 04:18:08 PM PDT 24 |
5872831392 ps |
| T85 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod.753366318 |
|
|
Mar 19 03:51:23 PM PDT 24 |
Mar 19 04:31:14 PM PDT 24 |
8804469134 ps |
| T86 |
/workspace/coverage/default/2.rom_e2e_smoke.3597609781 |
|
|
Mar 19 04:05:21 PM PDT 24 |
Mar 19 04:42:09 PM PDT 24 |
8654806222 ps |
| T87 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.4032062503 |
|
|
Mar 19 04:02:47 PM PDT 24 |
Mar 19 04:16:59 PM PDT 24 |
4871291552 ps |
| T88 |
/workspace/coverage/default/57.chip_sw_alert_handler_lpg_sleep_mode_alerts.1422757389 |
|
|
Mar 19 04:10:11 PM PDT 24 |
Mar 19 04:18:55 PM PDT 24 |
3950625640 ps |
| T89 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac.685164369 |
|
|
Mar 19 03:50:45 PM PDT 24 |
Mar 19 03:55:22 PM PDT 24 |
2780005128 ps |
| T90 |
/workspace/coverage/default/77.chip_sw_alert_handler_lpg_sleep_mode_alerts.592623691 |
|
|
Mar 19 04:15:48 PM PDT 24 |
Mar 19 04:21:02 PM PDT 24 |
3377387132 ps |
| T91 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771485533 |
|
|
Mar 19 04:09:42 PM PDT 24 |
Mar 19 04:16:13 PM PDT 24 |
3750647792 ps |
| T92 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.1539677729 |
|
|
Mar 19 04:07:44 PM PDT 24 |
Mar 19 04:13:56 PM PDT 24 |
3898016692 ps |
| T93 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_disabled.2264965293 |
|
|
Mar 19 03:47:14 PM PDT 24 |
Mar 19 03:51:16 PM PDT 24 |
2872078914 ps |
| T969 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.3016274518 |
|
|
Mar 19 03:56:12 PM PDT 24 |
Mar 19 04:33:57 PM PDT 24 |
8845251438 ps |
| T970 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.644394745 |
|
|
Mar 19 03:57:54 PM PDT 24 |
Mar 19 04:13:58 PM PDT 24 |
6194685766 ps |
| T971 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.1329662321 |
|
|
Mar 19 03:53:07 PM PDT 24 |
Mar 19 04:25:17 PM PDT 24 |
7698766455 ps |
| T972 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.2227115229 |
|
|
Mar 19 03:46:56 PM PDT 24 |
Mar 19 03:53:06 PM PDT 24 |
4274639168 ps |
| T168 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_status.3494936230 |
|
|
Mar 19 03:47:03 PM PDT 24 |
Mar 19 03:50:16 PM PDT 24 |
2563968406 ps |
| T973 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3522163334 |
|
|
Mar 19 03:48:48 PM PDT 24 |
Mar 19 04:15:31 PM PDT 24 |
8629685044 ps |
| T672 |
/workspace/coverage/default/0.chip_sw_power_idle_load.852802918 |
|
|
Mar 19 03:48:24 PM PDT 24 |
Mar 19 04:00:52 PM PDT 24 |
4314070286 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.1406520720 |
|
|
Mar 19 04:02:38 PM PDT 24 |
Mar 19 04:34:51 PM PDT 24 |
19319392873 ps |
| T764 |
/workspace/coverage/default/42.chip_sw_all_escalation_resets.1167844079 |
|
|
Mar 19 04:13:09 PM PDT 24 |
Mar 19 04:22:57 PM PDT 24 |
4694026172 ps |
| T974 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usb_clk_disabled_when_active.180645831 |
|
|
Mar 19 03:50:55 PM PDT 24 |
Mar 19 03:58:11 PM PDT 24 |
4420735360 ps |
| T975 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.2877536500 |
|
|
Mar 19 03:50:34 PM PDT 24 |
Mar 19 03:55:14 PM PDT 24 |
2301268470 ps |
| T976 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_hmac_trans.462653862 |
|
|
Mar 19 04:01:49 PM PDT 24 |
Mar 19 04:09:33 PM PDT 24 |
4945603920 ps |
| T287 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.1464609574 |
|
|
Mar 19 03:54:08 PM PDT 24 |
Mar 19 04:09:41 PM PDT 24 |
4749503820 ps |
| T717 |
/workspace/coverage/default/85.chip_sw_alert_handler_lpg_sleep_mode_alerts.2600528516 |
|
|
Mar 19 04:12:44 PM PDT 24 |
Mar 19 04:19:27 PM PDT 24 |
4328151112 ps |
| T977 |
/workspace/coverage/default/0.chip_sw_clkmgr_smoketest.3428672985 |
|
|
Mar 19 03:47:38 PM PDT 24 |
Mar 19 03:51:23 PM PDT 24 |
2911036792 ps |
| T978 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2992367611 |
|
|
Mar 19 04:03:25 PM PDT 24 |
Mar 19 04:11:23 PM PDT 24 |
5397006038 ps |
| T979 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_scramble.959029351 |
|
|
Mar 19 04:04:04 PM PDT 24 |
Mar 19 04:17:06 PM PDT 24 |
7402959008 ps |
| T980 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_rnd.2904826595 |
|
|
Mar 19 03:46:53 PM PDT 24 |
Mar 19 04:05:25 PM PDT 24 |
4890354400 ps |
| T981 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.3782021475 |
|
|
Mar 19 03:47:34 PM PDT 24 |
Mar 19 04:06:52 PM PDT 24 |
8255368088 ps |
| T402 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_clkoff.3802192127 |
|
|
Mar 19 03:59:51 PM PDT 24 |
Mar 19 04:25:12 PM PDT 24 |
7429223912 ps |
| T24 |
/workspace/coverage/default/1.chip_sw_gpio.3278991810 |
|
|
Mar 19 03:46:29 PM PDT 24 |
Mar 19 03:53:05 PM PDT 24 |
3652797296 ps |
| T982 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.3517711836 |
|
|
Mar 19 03:49:32 PM PDT 24 |
Mar 19 04:05:53 PM PDT 24 |
5320496872 ps |
| T55 |
/workspace/coverage/default/2.chip_sw_alert_test.1008769832 |
|
|
Mar 19 04:01:33 PM PDT 24 |
Mar 19 04:07:51 PM PDT 24 |
3202753800 ps |
| T186 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1600210868 |
|
|
Mar 19 03:50:25 PM PDT 24 |
Mar 19 04:02:00 PM PDT 24 |
4339186293 ps |
| T754 |
/workspace/coverage/default/64.chip_sw_alert_handler_lpg_sleep_mode_alerts.3771798799 |
|
|
Mar 19 04:11:39 PM PDT 24 |
Mar 19 04:18:19 PM PDT 24 |
3763487480 ps |
| T983 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.1315829828 |
|
|
Mar 19 04:06:20 PM PDT 24 |
Mar 19 04:25:42 PM PDT 24 |
7262950326 ps |
| T984 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_reset_reqs.1085803972 |
|
|
Mar 19 03:46:41 PM PDT 24 |
Mar 19 04:34:27 PM PDT 24 |
25972711298 ps |
| T985 |
/workspace/coverage/default/1.chip_sw_flash_crash_alert.61733132 |
|
|
Mar 19 03:49:12 PM PDT 24 |
Mar 19 03:58:46 PM PDT 24 |
5547106512 ps |
| T986 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.3938199687 |
|
|
Mar 19 03:50:52 PM PDT 24 |
Mar 19 04:01:39 PM PDT 24 |
4668352968 ps |
| T298 |
/workspace/coverage/default/0.chip_sw_entropy_src_csrng.1628312345 |
|
|
Mar 19 03:47:32 PM PDT 24 |
Mar 19 04:12:46 PM PDT 24 |
6643354650 ps |
| T987 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3573161792 |
|
|
Mar 19 03:51:20 PM PDT 24 |
Mar 19 04:23:38 PM PDT 24 |
9335202599 ps |
| T664 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3011606797 |
|
|
Mar 19 03:53:06 PM PDT 24 |
Mar 19 03:55:00 PM PDT 24 |
2242923704 ps |
| T654 |
/workspace/coverage/default/1.chip_sw_edn_auto_mode.2059779464 |
|
|
Mar 19 03:53:48 PM PDT 24 |
Mar 19 04:20:31 PM PDT 24 |
7033624136 ps |
| T988 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2061629481 |
|
|
Mar 19 04:02:53 PM PDT 24 |
Mar 19 04:13:27 PM PDT 24 |
4005104156 ps |
| T312 |
/workspace/coverage/default/2.chip_sw_i2c_device_tx_rx.899081417 |
|
|
Mar 19 03:55:33 PM PDT 24 |
Mar 19 04:04:57 PM PDT 24 |
4804442064 ps |
| T790 |
/workspace/coverage/default/34.chip_sw_alert_handler_lpg_sleep_mode_alerts.267344629 |
|
|
Mar 19 04:11:48 PM PDT 24 |
Mar 19 04:18:46 PM PDT 24 |
3439061536 ps |
| T725 |
/workspace/coverage/default/36.chip_sw_all_escalation_resets.2668818396 |
|
|
Mar 19 04:11:42 PM PDT 24 |
Mar 19 04:23:10 PM PDT 24 |
4699621576 ps |
| T82 |
/workspace/coverage/default/49.chip_sw_alert_handler_lpg_sleep_mode_alerts.2145025277 |
|
|
Mar 19 04:09:44 PM PDT 24 |
Mar 19 04:18:02 PM PDT 24 |
3448305432 ps |
| T989 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.2221992230 |
|
|
Mar 19 04:00:15 PM PDT 24 |
Mar 19 04:04:26 PM PDT 24 |
2858333992 ps |
| T729 |
/workspace/coverage/default/27.chip_sw_alert_handler_lpg_sleep_mode_alerts.2112778920 |
|
|
Mar 19 04:08:57 PM PDT 24 |
Mar 19 04:16:12 PM PDT 24 |
3340948038 ps |
| T234 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en.1370244998 |
|
|
Mar 19 04:04:21 PM PDT 24 |
Mar 19 04:15:04 PM PDT 24 |
4798253593 ps |
| T990 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.355712537 |
|
|
Mar 19 03:50:50 PM PDT 24 |
Mar 19 03:55:40 PM PDT 24 |
3303482614 ps |
| T314 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.3081148195 |
|
|
Mar 19 03:53:36 PM PDT 24 |
Mar 19 03:57:32 PM PDT 24 |
2624763566 ps |
| T300 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx.2364791070 |
|
|
Mar 19 03:54:49 PM PDT 24 |
Mar 19 04:07:35 PM PDT 24 |
4480101760 ps |
| T205 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.104410122 |
|
|
Mar 19 04:08:18 PM PDT 24 |
Mar 19 04:19:50 PM PDT 24 |
6167039610 ps |
| T991 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.1339046692 |
|
|
Mar 19 03:53:26 PM PDT 24 |
Mar 19 04:39:49 PM PDT 24 |
11824383476 ps |
| T744 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.3552948524 |
|
|
Mar 19 04:10:13 PM PDT 24 |
Mar 19 04:16:42 PM PDT 24 |
4062396560 ps |
| T71 |
/workspace/coverage/default/1.chip_jtag_mem_access.2422728953 |
|
|
Mar 19 03:38:58 PM PDT 24 |
Mar 19 04:06:06 PM PDT 24 |
13959994816 ps |
| T992 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.2068088148 |
|
|
Mar 19 03:46:58 PM PDT 24 |
Mar 19 04:00:17 PM PDT 24 |
7038268106 ps |
| T83 |
/workspace/coverage/default/3.chip_sw_alert_handler_lpg_sleep_mode_alerts.2070764975 |
|
|
Mar 19 04:05:51 PM PDT 24 |
Mar 19 04:12:42 PM PDT 24 |
3378933216 ps |
| T993 |
/workspace/coverage/default/2.rom_e2e_static_critical.520167052 |
|
|
Mar 19 04:08:32 PM PDT 24 |
Mar 19 04:53:30 PM PDT 24 |
10946759426 ps |
| T994 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_lc.2386784323 |
|
|
Mar 19 03:46:04 PM PDT 24 |
Mar 19 03:55:10 PM PDT 24 |
5550741452 ps |
| T113 |
/workspace/coverage/default/0.chip_sw_alert_handler_reverse_ping_in_deep_sleep.1165305471 |
|
|
Mar 19 03:49:24 PM PDT 24 |
Mar 19 07:30:50 PM PDT 24 |
255796186270 ps |
| T801 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.2803071214 |
|
|
Mar 19 04:13:49 PM PDT 24 |
Mar 19 04:23:00 PM PDT 24 |
3591171420 ps |
| T995 |
/workspace/coverage/default/76.chip_sw_alert_handler_lpg_sleep_mode_alerts.3131093546 |
|
|
Mar 19 04:12:54 PM PDT 24 |
Mar 19 04:19:24 PM PDT 24 |
3842886648 ps |
| T750 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.3517732435 |
|
|
Mar 19 04:10:14 PM PDT 24 |
Mar 19 04:22:28 PM PDT 24 |
5330308402 ps |
| T996 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.4178889691 |
|
|
Mar 19 03:50:59 PM PDT 24 |
Mar 19 04:39:24 PM PDT 24 |
26076382833 ps |
| T665 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.3971673086 |
|
|
Mar 19 03:48:33 PM PDT 24 |
Mar 19 03:50:56 PM PDT 24 |
3954147935 ps |
| T997 |
/workspace/coverage/default/1.chip_sw_kmac_mode_cshake.3964429554 |
|
|
Mar 19 03:50:00 PM PDT 24 |
Mar 19 03:53:49 PM PDT 24 |
3166974426 ps |
| T289 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4022949562 |
|
|
Mar 19 03:48:15 PM PDT 24 |
Mar 19 03:58:28 PM PDT 24 |
4942367072 ps |
| T798 |
/workspace/coverage/default/37.chip_sw_alert_handler_lpg_sleep_mode_alerts.1852272797 |
|
|
Mar 19 04:08:29 PM PDT 24 |
Mar 19 04:15:26 PM PDT 24 |
3660043582 ps |
| T998 |
/workspace/coverage/default/9.chip_sw_lc_ctrl_transition.1084809439 |
|
|
Mar 19 04:08:59 PM PDT 24 |
Mar 19 04:21:37 PM PDT 24 |
5264452874 ps |
| T77 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.1737337835 |
|
|
Mar 19 03:48:25 PM PDT 24 |
Mar 19 03:52:16 PM PDT 24 |
2979301303 ps |
| T32 |
/workspace/coverage/default/2.chip_sw_spi_device_tpm.4240069339 |
|
|
Mar 19 03:56:13 PM PDT 24 |
Mar 19 04:01:05 PM PDT 24 |
3286633947 ps |
| T999 |
/workspace/coverage/default/2.chip_sw_aon_timer_smoketest.158154652 |
|
|
Mar 19 04:05:13 PM PDT 24 |
Mar 19 04:11:02 PM PDT 24 |
3552660700 ps |
| T653 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.216081864 |
|
|
Mar 19 03:48:03 PM PDT 24 |
Mar 19 04:53:20 PM PDT 24 |
24882187351 ps |
| T119 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.3825642384 |
|
|
Mar 19 04:08:21 PM PDT 24 |
Mar 19 04:20:45 PM PDT 24 |
5438106200 ps |
| T1000 |
/workspace/coverage/default/1.chip_sw_clkmgr_smoketest.3146586701 |
|
|
Mar 19 03:50:40 PM PDT 24 |
Mar 19 03:54:01 PM PDT 24 |
3338096888 ps |
| T731 |
/workspace/coverage/default/51.chip_sw_all_escalation_resets.1341131632 |
|
|
Mar 19 04:11:55 PM PDT 24 |
Mar 19 04:22:48 PM PDT 24 |
5153565776 ps |
| T1001 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prod.4181479081 |
|
|
Mar 19 03:48:14 PM PDT 24 |
Mar 19 05:14:14 PM PDT 24 |
46167951048 ps |
| T1002 |
/workspace/coverage/default/1.chip_sw_rstmgr_rst_cnsty_escalation.1731299031 |
|
|
Mar 19 03:50:26 PM PDT 24 |
Mar 19 04:01:52 PM PDT 24 |
4338888080 ps |
| T771 |
/workspace/coverage/default/8.chip_sw_all_escalation_resets.2423053108 |
|
|
Mar 19 04:06:42 PM PDT 24 |
Mar 19 04:15:35 PM PDT 24 |
5441674912 ps |
| T6 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.865789981 |
|
|
Mar 19 03:50:19 PM PDT 24 |
Mar 19 03:54:33 PM PDT 24 |
2702694150 ps |
| T1003 |
/workspace/coverage/default/0.chip_sw_kmac_idle.3472600444 |
|
|
Mar 19 03:49:40 PM PDT 24 |
Mar 19 03:54:18 PM PDT 24 |
2410898764 ps |
| T1004 |
/workspace/coverage/default/1.chip_sw_aes_masking_off.2250619028 |
|
|
Mar 19 03:53:25 PM PDT 24 |
Mar 19 03:57:45 PM PDT 24 |
2714080613 ps |
| T1005 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.847061917 |
|
|
Mar 19 03:48:30 PM PDT 24 |
Mar 19 04:01:28 PM PDT 24 |
4436683340 ps |
| T1006 |
/workspace/coverage/default/2.chip_sw_example_flash.2529332892 |
|
|
Mar 19 03:52:43 PM PDT 24 |
Mar 19 03:57:00 PM PDT 24 |
3020110868 ps |
| T302 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.627311478 |
|
|
Mar 19 03:48:48 PM PDT 24 |
Mar 19 04:04:16 PM PDT 24 |
5212026950 ps |
| T219 |
/workspace/coverage/default/32.chip_sw_all_escalation_resets.2551048381 |
|
|
Mar 19 04:09:54 PM PDT 24 |
Mar 19 04:18:33 PM PDT 24 |
3999646744 ps |
| T1007 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.3203768743 |
|
|
Mar 19 03:45:12 PM PDT 24 |
Mar 19 03:49:58 PM PDT 24 |
2449601345 ps |
| T1008 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_wake_5_bug.3377235286 |
|
|
Mar 19 04:02:27 PM PDT 24 |
Mar 19 04:10:54 PM PDT 24 |
5582385622 ps |
| T191 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.1870419648 |
|
|
Mar 19 04:07:33 PM PDT 24 |
Mar 19 04:18:32 PM PDT 24 |
4620822063 ps |
| T1009 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.1458568743 |
|
|
Mar 19 03:52:25 PM PDT 24 |
Mar 19 04:30:14 PM PDT 24 |
23475221995 ps |
| T1010 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.4166851243 |
|
|
Mar 19 03:46:04 PM PDT 24 |
Mar 19 04:07:38 PM PDT 24 |
6287334936 ps |
| T1011 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.1695523244 |
|
|
Mar 19 03:46:34 PM PDT 24 |
Mar 19 04:01:38 PM PDT 24 |
4971691810 ps |
| T1012 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2484636858 |
|
|
Mar 19 03:57:45 PM PDT 24 |
Mar 19 04:19:45 PM PDT 24 |
11429833125 ps |
| T799 |
/workspace/coverage/default/71.chip_sw_all_escalation_resets.3775529541 |
|
|
Mar 19 04:12:00 PM PDT 24 |
Mar 19 04:24:09 PM PDT 24 |
6000384566 ps |
| T1013 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.2477266138 |
|
|
Mar 19 03:52:22 PM PDT 24 |
Mar 19 03:57:59 PM PDT 24 |
3839617070 ps |
| T1014 |
/workspace/coverage/default/0.chip_sw_clkmgr_reset_frequency.721738382 |
|
|
Mar 19 03:49:53 PM PDT 24 |
Mar 19 03:57:17 PM PDT 24 |
3508314416 ps |
| T112 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_pings.953517208 |
|
|
Mar 19 03:46:00 PM PDT 24 |
Mar 19 04:09:17 PM PDT 24 |
12033447022 ps |
| T1015 |
/workspace/coverage/default/0.rom_e2e_smoke.3224817734 |
|
|
Mar 19 03:46:52 PM PDT 24 |
Mar 19 04:20:58 PM PDT 24 |
8636076184 ps |
| T1016 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.3684579140 |
|
|
Mar 19 04:06:33 PM PDT 24 |
Mar 19 04:10:37 PM PDT 24 |
3099013750 ps |
| T33 |
/workspace/coverage/default/1.chip_sw_spi_device_tpm.34489730 |
|
|
Mar 19 03:50:30 PM PDT 24 |
Mar 19 03:59:32 PM PDT 24 |
3693571263 ps |
| T716 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1261728553 |
|
|
Mar 19 04:13:07 PM PDT 24 |
Mar 19 04:20:51 PM PDT 24 |
3751846670 ps |
| T397 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.2983256357 |
|
|
Mar 19 03:46:41 PM PDT 24 |
Mar 19 03:56:30 PM PDT 24 |
8387315726 ps |
| T180 |
/workspace/coverage/default/0.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.2007453921 |
|
|
Mar 19 03:48:14 PM PDT 24 |
Mar 19 03:59:45 PM PDT 24 |
5043307688 ps |
| T1017 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.2746161791 |
|
|
Mar 19 03:51:26 PM PDT 24 |
Mar 19 03:59:19 PM PDT 24 |
3928976216 ps |
| T1018 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_prod.1202731240 |
|
|
Mar 19 03:51:09 PM PDT 24 |
Mar 19 04:01:15 PM PDT 24 |
4484432772 ps |
| T324 |
/workspace/coverage/default/0.chip_sw_pattgen_ios.3858035036 |
|
|
Mar 19 03:46:21 PM PDT 24 |
Mar 19 03:49:54 PM PDT 24 |
2544237250 ps |
| T1019 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.346438531 |
|
|
Mar 19 04:07:26 PM PDT 24 |
Mar 19 04:28:04 PM PDT 24 |
10658746857 ps |
| T194 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2653081952 |
|
|
Mar 19 03:48:59 PM PDT 24 |
Mar 19 07:06:08 PM PDT 24 |
65060603032 ps |
| T1020 |
/workspace/coverage/default/1.chip_sw_example_flash.447987434 |
|
|
Mar 19 03:49:18 PM PDT 24 |
Mar 19 03:53:21 PM PDT 24 |
2883931792 ps |
| T253 |
/workspace/coverage/default/1.chip_jtag_csr_rw.2069215599 |
|
|
Mar 19 03:38:41 PM PDT 24 |
Mar 19 04:18:15 PM PDT 24 |
18758977512 ps |
| T782 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.1782100083 |
|
|
Mar 19 04:09:10 PM PDT 24 |
Mar 19 04:21:15 PM PDT 24 |
4508125552 ps |
| T45 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3121811039 |
|
|
Mar 19 03:57:59 PM PDT 24 |
Mar 19 04:03:48 PM PDT 24 |
3768366408 ps |
| T213 |
/workspace/coverage/default/1.chip_sw_plic_sw_irq.1268696538 |
|
|
Mar 19 03:51:04 PM PDT 24 |
Mar 19 03:54:18 PM PDT 24 |
2765326530 ps |
| T307 |
/workspace/coverage/default/13.chip_sw_uart_rand_baudrate.1858894822 |
|
|
Mar 19 04:06:51 PM PDT 24 |
Mar 19 04:46:40 PM PDT 24 |
13429147507 ps |
| T371 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.3663131238 |
|
|
Mar 19 04:10:41 PM PDT 24 |
Mar 19 04:17:33 PM PDT 24 |
4168126152 ps |
| T120 |
/workspace/coverage/default/20.chip_sw_all_escalation_resets.1530116961 |
|
|
Mar 19 04:09:13 PM PDT 24 |
Mar 19 04:22:55 PM PDT 24 |
6219839608 ps |
| T235 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.1216756306 |
|
|
Mar 19 04:05:54 PM PDT 24 |
Mar 19 04:17:39 PM PDT 24 |
5522441815 ps |
| T372 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.3338447689 |
|
|
Mar 19 04:09:13 PM PDT 24 |
Mar 19 04:21:18 PM PDT 24 |
4930897188 ps |
| T373 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3505660871 |
|
|
Mar 19 03:50:12 PM PDT 24 |
Mar 19 04:04:32 PM PDT 24 |
4202024450 ps |
| T220 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.356116476 |
|
|
Mar 19 04:07:12 PM PDT 24 |
Mar 19 04:15:54 PM PDT 24 |
4795451138 ps |
| T30 |
/workspace/coverage/default/1.chip_sw_spi_host_tx_rx.563229035 |
|
|
Mar 19 03:50:32 PM PDT 24 |
Mar 19 03:54:45 PM PDT 24 |
2959793968 ps |
| T1021 |
/workspace/coverage/default/2.chip_sw_flash_scrambling_smoketest.1557772540 |
|
|
Mar 19 04:07:24 PM PDT 24 |
Mar 19 04:11:49 PM PDT 24 |
2652624704 ps |
| T175 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.4113563444 |
|
|
Mar 19 03:51:10 PM PDT 24 |
Mar 19 04:02:42 PM PDT 24 |
3912148000 ps |
| T1022 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod.2864356054 |
|
|
Mar 19 03:56:44 PM PDT 24 |
Mar 19 04:33:20 PM PDT 24 |
8805027546 ps |
| T1023 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.124876556 |
|
|
Mar 19 03:46:40 PM PDT 24 |
Mar 19 03:51:00 PM PDT 24 |
2705676080 ps |
| T64 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.2689194898 |
|
|
Mar 19 03:45:49 PM PDT 24 |
Mar 19 03:51:36 PM PDT 24 |
2518489770 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2672918001 |
|
|
Mar 19 03:47:45 PM PDT 24 |
Mar 19 05:26:57 PM PDT 24 |
48031051121 ps |
| T1024 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.76115525 |
|
|
Mar 19 03:49:16 PM PDT 24 |
Mar 19 04:04:12 PM PDT 24 |
5618220912 ps |
| T709 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.3803083113 |
|
|
Mar 19 04:12:19 PM PDT 24 |
Mar 19 04:21:35 PM PDT 24 |
4387042712 ps |
| T365 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usbdev_smoketest.805735094 |
|
|
Mar 19 03:53:18 PM PDT 24 |
Mar 19 04:00:59 PM PDT 24 |
5335515184 ps |
| T1025 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.2307775827 |
|
|
Mar 19 04:04:27 PM PDT 24 |
Mar 19 04:08:48 PM PDT 24 |
2410765318 ps |
| T1026 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.3421484849 |
|
|
Mar 19 04:02:23 PM PDT 24 |
Mar 19 04:09:13 PM PDT 24 |
3447345872 ps |
| T1027 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.824330920 |
|
|
Mar 19 03:46:26 PM PDT 24 |
Mar 19 04:22:40 PM PDT 24 |
8393164330 ps |
| T1028 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.4076708168 |
|
|
Mar 19 03:58:05 PM PDT 24 |
Mar 19 04:21:54 PM PDT 24 |
11324328504 ps |
| T710 |
/workspace/coverage/default/44.chip_sw_alert_handler_lpg_sleep_mode_alerts.1564393702 |
|
|
Mar 19 04:09:24 PM PDT 24 |
Mar 19 04:15:40 PM PDT 24 |
3788656268 ps |
| T1029 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1046318859 |
|
|
Mar 19 03:49:37 PM PDT 24 |
Mar 19 04:02:58 PM PDT 24 |
6066918129 ps |
| T110 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.1799009271 |
|
|
Mar 19 04:03:57 PM PDT 24 |
Mar 19 04:14:19 PM PDT 24 |
3949867904 ps |
| T353 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.3599348552 |
|
|
Mar 19 03:51:22 PM PDT 24 |
Mar 19 03:54:36 PM PDT 24 |
2879451266 ps |
| T34 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.223495870 |
|
|
Mar 19 03:53:24 PM PDT 24 |
Mar 19 03:59:39 PM PDT 24 |
3233686620 ps |
| T1030 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter.4125371335 |
|
|
Mar 19 03:51:11 PM PDT 24 |
Mar 19 03:55:54 PM PDT 24 |
2565616846 ps |
| T1031 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.1737208407 |
|
|
Mar 19 03:47:49 PM PDT 24 |
Mar 19 03:50:31 PM PDT 24 |
2957068484 ps |
| T1032 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_lc_rw_en.3872062371 |
|
|
Mar 19 03:48:42 PM PDT 24 |
Mar 19 03:55:41 PM PDT 24 |
3854807480 ps |