| T1176 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.2462557752 |
|
|
Mar 19 03:49:35 PM PDT 24 |
Mar 19 04:23:58 PM PDT 24 |
8854761762 ps |
| T1177 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.22015432 |
|
|
Mar 19 04:04:56 PM PDT 24 |
Mar 19 04:16:25 PM PDT 24 |
4025137682 ps |
| T42 |
/workspace/coverage/default/0.chip_rv_dm_ndm_reset_req.364990613 |
|
|
Mar 19 03:51:35 PM PDT 24 |
Mar 19 03:58:17 PM PDT 24 |
2996701768 ps |
| T1178 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3752018687 |
|
|
Mar 19 03:59:22 PM PDT 24 |
Mar 19 04:14:44 PM PDT 24 |
4968578306 ps |
| T1179 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.463308534 |
|
|
Mar 19 03:50:40 PM PDT 24 |
Mar 19 03:55:28 PM PDT 24 |
2964824100 ps |
| T713 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082387984 |
|
|
Mar 19 03:50:07 PM PDT 24 |
Mar 19 03:58:54 PM PDT 24 |
4329654048 ps |
| T1180 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.2016465686 |
|
|
Mar 19 03:51:09 PM PDT 24 |
Mar 19 04:16:50 PM PDT 24 |
5701632860 ps |
| T1181 |
/workspace/coverage/default/2.chip_tap_straps_dev.3833831101 |
|
|
Mar 19 04:05:11 PM PDT 24 |
Mar 19 04:10:05 PM PDT 24 |
3250720082 ps |
| T1182 |
/workspace/coverage/default/2.rom_raw_unlock.2028995843 |
|
|
Mar 19 04:06:00 PM PDT 24 |
Mar 19 04:36:24 PM PDT 24 |
13669600950 ps |
| T1183 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.3495476943 |
|
|
Mar 19 03:57:29 PM PDT 24 |
Mar 19 04:07:33 PM PDT 24 |
9028908342 ps |
| T1184 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.3139201095 |
|
|
Mar 19 04:02:17 PM PDT 24 |
Mar 19 04:13:53 PM PDT 24 |
7525427912 ps |
| T735 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.2879945845 |
|
|
Mar 19 04:11:52 PM PDT 24 |
Mar 19 04:19:02 PM PDT 24 |
3702404832 ps |
| T759 |
/workspace/coverage/default/8.chip_sw_alert_handler_lpg_sleep_mode_alerts.3327249655 |
|
|
Mar 19 04:09:11 PM PDT 24 |
Mar 19 04:15:54 PM PDT 24 |
4121953200 ps |
| T1185 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2080268067 |
|
|
Mar 19 03:53:36 PM PDT 24 |
Mar 19 04:02:52 PM PDT 24 |
4733702184 ps |
| T1186 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_test_unlocked0.2146863352 |
|
|
Mar 19 03:52:43 PM PDT 24 |
Mar 19 04:21:11 PM PDT 24 |
6894062135 ps |
| T224 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1606603789 |
|
|
Mar 19 03:47:39 PM PDT 24 |
Mar 19 03:57:00 PM PDT 24 |
4644970048 ps |
| T1187 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2381045180 |
|
|
Mar 19 03:50:47 PM PDT 24 |
Mar 19 04:00:43 PM PDT 24 |
3608878086 ps |
| T286 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.2596889372 |
|
|
Mar 19 04:02:26 PM PDT 24 |
Mar 19 04:17:33 PM PDT 24 |
4554456200 ps |
| T806 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.1403075004 |
|
|
Mar 19 04:13:06 PM PDT 24 |
Mar 19 04:25:16 PM PDT 24 |
5647820320 ps |
| T1188 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en.1534010241 |
|
|
Mar 19 03:59:06 PM PDT 24 |
Mar 19 04:58:06 PM PDT 24 |
18732273334 ps |
| T1189 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.3482800160 |
|
|
Mar 19 03:47:19 PM PDT 24 |
Mar 19 03:49:30 PM PDT 24 |
2075367715 ps |
| T736 |
/workspace/coverage/default/84.chip_sw_all_escalation_resets.674490856 |
|
|
Mar 19 04:13:18 PM PDT 24 |
Mar 19 04:21:13 PM PDT 24 |
4691885968 ps |
| T732 |
/workspace/coverage/default/62.chip_sw_all_escalation_resets.2998694882 |
|
|
Mar 19 04:13:41 PM PDT 24 |
Mar 19 04:23:03 PM PDT 24 |
4126100632 ps |
| T1190 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx1.3380516259 |
|
|
Mar 19 03:51:15 PM PDT 24 |
Mar 19 04:04:21 PM PDT 24 |
5146512434 ps |
| T1191 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.1254154303 |
|
|
Mar 19 03:55:14 PM PDT 24 |
Mar 19 04:34:24 PM PDT 24 |
7828322420 ps |
| T1192 |
/workspace/coverage/default/1.chip_sw_rstmgr_smoketest.176389753 |
|
|
Mar 19 03:53:06 PM PDT 24 |
Mar 19 03:56:46 PM PDT 24 |
2353553152 ps |
| T661 |
/workspace/coverage/default/0.chip_tap_straps_dev.1236122440 |
|
|
Mar 19 03:46:48 PM PDT 24 |
Mar 19 04:19:07 PM PDT 24 |
15494155495 ps |
| T1193 |
/workspace/coverage/default/1.chip_sw_uart_smoketest.1441030892 |
|
|
Mar 19 03:51:38 PM PDT 24 |
Mar 19 03:55:03 PM PDT 24 |
2400271576 ps |
| T1194 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.1528524157 |
|
|
Mar 19 03:55:10 PM PDT 24 |
Mar 19 04:30:45 PM PDT 24 |
9363171213 ps |
| T804 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.1529625097 |
|
|
Mar 19 04:08:57 PM PDT 24 |
Mar 19 04:16:13 PM PDT 24 |
3478665180 ps |
| T293 |
/workspace/coverage/default/1.chip_plic_all_irqs_0.1066214356 |
|
|
Mar 19 03:50:05 PM PDT 24 |
Mar 19 04:08:12 PM PDT 24 |
6397451128 ps |
| T780 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2553890902 |
|
|
Mar 19 04:10:22 PM PDT 24 |
Mar 19 04:17:06 PM PDT 24 |
3491987628 ps |
| T722 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.615307062 |
|
|
Mar 19 04:12:12 PM PDT 24 |
Mar 19 04:27:04 PM PDT 24 |
6043305394 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1318273843 |
|
|
Mar 19 03:57:50 PM PDT 24 |
Mar 19 04:04:31 PM PDT 24 |
5211112900 ps |
| T1195 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.3780146273 |
|
|
Mar 19 04:00:49 PM PDT 24 |
Mar 19 04:04:43 PM PDT 24 |
3172485156 ps |
| T1196 |
/workspace/coverage/default/0.chip_sw_pwrmgr_wdog_reset.1273553192 |
|
|
Mar 19 03:47:25 PM PDT 24 |
Mar 19 03:53:56 PM PDT 24 |
4358979568 ps |
| T1197 |
/workspace/coverage/default/2.chip_sw_hmac_enc.1260875005 |
|
|
Mar 19 04:00:43 PM PDT 24 |
Mar 19 04:04:37 PM PDT 24 |
3122848100 ps |
| T1198 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3207831484 |
|
|
Mar 19 04:04:19 PM PDT 24 |
Mar 19 04:13:36 PM PDT 24 |
5691188248 ps |
| T164 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.1323150576 |
|
|
Mar 19 03:51:32 PM PDT 24 |
Mar 19 03:59:48 PM PDT 24 |
5844606000 ps |
| T1199 |
/workspace/coverage/default/3.chip_sw_lc_ctrl_transition.2368276437 |
|
|
Mar 19 04:08:16 PM PDT 24 |
Mar 19 04:18:40 PM PDT 24 |
7253358789 ps |
| T1200 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.236729585 |
|
|
Mar 19 04:05:04 PM PDT 24 |
Mar 19 04:14:12 PM PDT 24 |
5756052576 ps |
| T1201 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_kmac.1205523401 |
|
|
Mar 19 04:00:07 PM PDT 24 |
Mar 19 04:07:30 PM PDT 24 |
5324422234 ps |
| T1202 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_frequency.3796317608 |
|
|
Mar 19 03:57:27 PM PDT 24 |
Mar 19 04:03:55 PM PDT 24 |
3019627878 ps |
| T1203 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access.1660234068 |
|
|
Mar 19 03:55:30 PM PDT 24 |
Mar 19 04:13:01 PM PDT 24 |
5791008280 ps |
| T1204 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_rma.355382528 |
|
|
Mar 19 03:51:10 PM PDT 24 |
Mar 19 04:29:52 PM PDT 24 |
8607063324 ps |
| T1205 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.3097856501 |
|
|
Mar 19 04:13:36 PM PDT 24 |
Mar 19 04:41:00 PM PDT 24 |
9056507939 ps |
| T1206 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.2383585846 |
|
|
Mar 19 04:08:11 PM PDT 24 |
Mar 19 04:44:44 PM PDT 24 |
8637977278 ps |
| T1207 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.1893001070 |
|
|
Mar 19 03:48:57 PM PDT 24 |
Mar 19 04:07:28 PM PDT 24 |
5638192908 ps |
| T1208 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.653910404 |
|
|
Mar 19 04:03:57 PM PDT 24 |
Mar 19 04:11:03 PM PDT 24 |
3462298669 ps |
| T1209 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1418486554 |
|
|
Mar 19 03:56:10 PM PDT 24 |
Mar 19 04:02:08 PM PDT 24 |
3517911750 ps |
| T1210 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_prodend.2575764135 |
|
|
Mar 19 03:48:45 PM PDT 24 |
Mar 19 04:06:13 PM PDT 24 |
9916332362 ps |
| T1211 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.2419976949 |
|
|
Mar 19 03:47:23 PM PDT 24 |
Mar 19 04:45:29 PM PDT 24 |
17144138664 ps |
| T1212 |
/workspace/coverage/default/0.rom_e2e_shutdown_exception_c.2616192516 |
|
|
Mar 19 03:51:16 PM PDT 24 |
Mar 19 04:26:25 PM PDT 24 |
8281695368 ps |
| T1213 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_power_glitch_reset.3915571283 |
|
|
Mar 19 03:51:21 PM PDT 24 |
Mar 19 04:43:15 PM PDT 24 |
34932722256 ps |
| T1214 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.3391404896 |
|
|
Mar 19 03:46:50 PM PDT 24 |
Mar 19 04:29:07 PM PDT 24 |
20726922658 ps |
| T1215 |
/workspace/coverage/default/2.chip_sw_pwrmgr_main_power_glitch_reset.637583766 |
|
|
Mar 19 03:58:04 PM PDT 24 |
Mar 19 04:06:13 PM PDT 24 |
5441624914 ps |
| T1216 |
/workspace/coverage/default/1.rom_e2e_smoke.650022013 |
|
|
Mar 19 03:51:39 PM PDT 24 |
Mar 19 04:29:42 PM PDT 24 |
8952409652 ps |
| T1217 |
/workspace/coverage/default/0.rom_e2e_static_critical.1860834117 |
|
|
Mar 19 03:52:50 PM PDT 24 |
Mar 19 04:35:50 PM PDT 24 |
11078373712 ps |
| T1218 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.784394989 |
|
|
Mar 19 03:51:21 PM PDT 24 |
Mar 19 07:08:27 PM PDT 24 |
64079627340 ps |
| T1219 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3256601930 |
|
|
Mar 19 03:49:53 PM PDT 24 |
Mar 19 03:57:42 PM PDT 24 |
4144230734 ps |
| T31 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.392350099 |
|
|
Mar 19 03:56:36 PM PDT 24 |
Mar 19 04:02:24 PM PDT 24 |
2881252230 ps |
| T1220 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.1120175635 |
|
|
Mar 19 03:48:58 PM PDT 24 |
Mar 19 03:57:48 PM PDT 24 |
4021685143 ps |
| T1221 |
/workspace/coverage/default/2.chip_sw_csrng_smoketest.2746759328 |
|
|
Mar 19 04:05:42 PM PDT 24 |
Mar 19 04:08:51 PM PDT 24 |
2450330160 ps |
| T797 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.1089186480 |
|
|
Mar 19 04:09:24 PM PDT 24 |
Mar 19 04:17:19 PM PDT 24 |
4239049884 ps |
| T1222 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.942835100 |
|
|
Mar 19 03:51:19 PM PDT 24 |
Mar 19 04:33:16 PM PDT 24 |
10317833086 ps |
| T1223 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_mem_protection.965185708 |
|
|
Mar 19 04:03:42 PM PDT 24 |
Mar 19 04:24:19 PM PDT 24 |
5892258302 ps |
| T1224 |
/workspace/coverage/default/2.chip_sw_exit_test_unlocked_bootstrap.2559645080 |
|
|
Mar 19 03:53:45 PM PDT 24 |
Mar 19 06:40:52 PM PDT 24 |
58994463875 ps |
| T1225 |
/workspace/coverage/default/1.rom_e2e_shutdown_output.2240206638 |
|
|
Mar 19 03:58:26 PM PDT 24 |
Mar 19 04:50:43 PM PDT 24 |
26172980186 ps |
| T1226 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_alt_clk_freq.4182761336 |
|
|
Mar 19 03:48:31 PM PDT 24 |
Mar 19 04:20:16 PM PDT 24 |
12548909223 ps |
| T1227 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.3920904675 |
|
|
Mar 19 04:00:32 PM PDT 24 |
Mar 19 07:12:09 PM PDT 24 |
254762160960 ps |
| T1228 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.3946516037 |
|
|
Mar 19 03:59:33 PM PDT 24 |
Mar 19 04:03:22 PM PDT 24 |
2705275001 ps |
| T1229 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.681620072 |
|
|
Mar 19 03:53:32 PM PDT 24 |
Mar 19 03:57:50 PM PDT 24 |
2011558821 ps |
| T1230 |
/workspace/coverage/default/0.chip_sw_aes_enc_jitter_en_reduced_freq.50370749 |
|
|
Mar 19 03:50:42 PM PDT 24 |
Mar 19 03:55:33 PM PDT 24 |
3503401576 ps |
| T728 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.4056904255 |
|
|
Mar 19 04:13:29 PM PDT 24 |
Mar 19 04:24:49 PM PDT 24 |
5740804120 ps |
| T141 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.1700500277 |
|
|
Mar 19 03:54:42 PM PDT 24 |
Mar 19 04:32:09 PM PDT 24 |
12903317274 ps |
| T1231 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.3944768208 |
|
|
Mar 19 03:48:33 PM PDT 24 |
Mar 19 03:53:29 PM PDT 24 |
3105592698 ps |
| T748 |
/workspace/coverage/default/73.chip_sw_all_escalation_resets.2047601253 |
|
|
Mar 19 04:12:27 PM PDT 24 |
Mar 19 04:26:47 PM PDT 24 |
5757486312 ps |
| T1232 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.1122876600 |
|
|
Mar 19 03:59:48 PM PDT 24 |
Mar 19 04:06:09 PM PDT 24 |
3338066479 ps |
| T1233 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.59201598 |
|
|
Mar 19 03:44:39 PM PDT 24 |
Mar 19 03:49:11 PM PDT 24 |
3144883960 ps |
| T367 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_wake_ups.2999348113 |
|
|
Mar 19 03:47:27 PM PDT 24 |
Mar 19 04:04:27 PM PDT 24 |
21269932008 ps |
| T1234 |
/workspace/coverage/default/0.chip_sw_uart_tx_rx_idx1.2719497421 |
|
|
Mar 19 03:49:52 PM PDT 24 |
Mar 19 04:07:00 PM PDT 24 |
5565762218 ps |
| T1235 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_peri.329272094 |
|
|
Mar 19 03:48:21 PM PDT 24 |
Mar 19 04:13:16 PM PDT 24 |
11746617986 ps |
| T769 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.437990879 |
|
|
Mar 19 04:11:10 PM PDT 24 |
Mar 19 04:21:11 PM PDT 24 |
4573808656 ps |
| T1236 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.2080227891 |
|
|
Mar 19 03:59:31 PM PDT 24 |
Mar 19 04:08:56 PM PDT 24 |
5091953010 ps |
| T698 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.3536986171 |
|
|
Mar 19 03:46:07 PM PDT 24 |
Mar 19 04:01:51 PM PDT 24 |
4940061848 ps |
| T1237 |
/workspace/coverage/default/1.chip_sw_alert_handler_escalation.272369905 |
|
|
Mar 19 03:48:22 PM PDT 24 |
Mar 19 03:56:29 PM PDT 24 |
4500763580 ps |
| T1238 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.1472930707 |
|
|
Mar 19 03:46:48 PM PDT 24 |
Mar 19 03:58:15 PM PDT 24 |
4526604854 ps |
| T1239 |
/workspace/coverage/default/2.chip_sw_rstmgr_sw_rst.2228966108 |
|
|
Mar 19 03:57:01 PM PDT 24 |
Mar 19 04:02:09 PM PDT 24 |
2400651856 ps |
| T1240 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx2.2373549595 |
|
|
Mar 19 03:51:20 PM PDT 24 |
Mar 19 04:07:47 PM PDT 24 |
5668498292 ps |
| T1241 |
/workspace/coverage/default/2.chip_sw_uart_rand_baudrate.704089727 |
|
|
Mar 19 03:54:36 PM PDT 24 |
Mar 19 04:39:28 PM PDT 24 |
14266786201 ps |
| T1242 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.2406551784 |
|
|
Mar 19 03:54:52 PM PDT 24 |
Mar 19 03:59:17 PM PDT 24 |
3135259952 ps |
| T1243 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2429031465 |
|
|
Mar 19 03:49:19 PM PDT 24 |
Mar 19 04:29:16 PM PDT 24 |
9321914584 ps |
| T254 |
/workspace/coverage/default/0.chip_jtag_csr_rw.2988515219 |
|
|
Mar 19 03:36:34 PM PDT 24 |
Mar 19 03:57:39 PM PDT 24 |
10698666451 ps |
| T494 |
/workspace/coverage/default/2.chip_jtag_csr_rw.2054469877 |
|
|
Mar 19 03:55:12 PM PDT 24 |
Mar 19 04:13:24 PM PDT 24 |
10604756356 ps |
| T627 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.3726156120 |
|
|
Mar 19 03:52:55 PM PDT 24 |
Mar 19 04:02:41 PM PDT 24 |
5139720276 ps |
| T1244 |
/workspace/coverage/default/1.chip_tap_straps_dev.1603480229 |
|
|
Mar 19 03:48:48 PM PDT 24 |
Mar 19 04:03:16 PM PDT 24 |
8976540504 ps |
| T1245 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_dev.686580086 |
|
|
Mar 19 03:47:51 PM PDT 24 |
Mar 19 04:09:23 PM PDT 24 |
9214517500 ps |
| T1246 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en.3496769150 |
|
|
Mar 19 03:53:17 PM PDT 24 |
Mar 19 04:02:13 PM PDT 24 |
4274669416 ps |
| T1247 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.3638023479 |
|
|
Mar 19 04:07:06 PM PDT 24 |
Mar 19 04:13:27 PM PDT 24 |
3570768192 ps |
| T1248 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.2271782896 |
|
|
Mar 19 03:48:26 PM PDT 24 |
Mar 19 03:53:04 PM PDT 24 |
2244197886 ps |
| T1249 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.3963882823 |
|
|
Mar 19 03:46:40 PM PDT 24 |
Mar 19 03:50:21 PM PDT 24 |
2594313518 ps |
| T1250 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ulp_z3_wakeup.1331997217 |
|
|
Mar 19 03:50:46 PM PDT 24 |
Mar 19 03:58:05 PM PDT 24 |
5604373000 ps |
| T1251 |
/workspace/coverage/default/0.chip_sw_kmac_app_rom.2360959944 |
|
|
Mar 19 03:51:47 PM PDT 24 |
Mar 19 03:56:06 PM PDT 24 |
2760703834 ps |
| T702 |
/workspace/coverage/default/0.chip_sw_data_integrity_escalation.2959345998 |
|
|
Mar 19 03:50:01 PM PDT 24 |
Mar 19 04:03:05 PM PDT 24 |
5727009260 ps |
| T1252 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.461266122 |
|
|
Mar 19 03:45:00 PM PDT 24 |
Mar 19 04:06:17 PM PDT 24 |
9205832873 ps |
| T655 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1848902467 |
|
|
Mar 19 03:59:14 PM PDT 24 |
Mar 19 04:14:37 PM PDT 24 |
4078903574 ps |
| T714 |
/workspace/coverage/default/56.chip_sw_alert_handler_lpg_sleep_mode_alerts.827285122 |
|
|
Mar 19 04:10:22 PM PDT 24 |
Mar 19 04:18:34 PM PDT 24 |
3708203384 ps |
| T660 |
/workspace/coverage/default/1.chip_sw_rv_dm_access_after_escalation_reset.147665069 |
|
|
Mar 19 03:47:36 PM PDT 24 |
Mar 19 03:54:12 PM PDT 24 |
5354569353 ps |
| T753 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.15291180 |
|
|
Mar 19 04:11:21 PM PDT 24 |
Mar 19 04:17:52 PM PDT 24 |
3535748196 ps |
| T1253 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1828861989 |
|
|
Mar 19 03:48:22 PM PDT 24 |
Mar 19 04:02:46 PM PDT 24 |
6564711358 ps |
| T768 |
/workspace/coverage/default/40.chip_sw_alert_handler_lpg_sleep_mode_alerts.3608320751 |
|
|
Mar 19 04:13:18 PM PDT 24 |
Mar 19 04:21:39 PM PDT 24 |
3681896748 ps |
| T1254 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.2466637086 |
|
|
Mar 19 03:49:48 PM PDT 24 |
Mar 19 04:05:14 PM PDT 24 |
7997760210 ps |
| T1255 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.3042606332 |
|
|
Mar 19 03:47:36 PM PDT 24 |
Mar 19 03:55:40 PM PDT 24 |
3215880540 ps |
| T295 |
/workspace/coverage/default/2.chip_plic_all_irqs_0.3035011866 |
|
|
Mar 19 04:03:51 PM PDT 24 |
Mar 19 04:21:55 PM PDT 24 |
5594877456 ps |
| T802 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.237328907 |
|
|
Mar 19 04:11:52 PM PDT 24 |
Mar 19 04:18:24 PM PDT 24 |
3758715812 ps |
| T1256 |
/workspace/coverage/default/0.chip_sw_flash_init.3577972992 |
|
|
Mar 19 03:45:22 PM PDT 24 |
Mar 19 04:20:16 PM PDT 24 |
25299092480 ps |
| T263 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.1959563094 |
|
|
Mar 19 04:01:39 PM PDT 24 |
Mar 19 04:57:49 PM PDT 24 |
12629525704 ps |
| T1257 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access.3788360397 |
|
|
Mar 19 03:48:06 PM PDT 24 |
Mar 19 04:04:51 PM PDT 24 |
6064289640 ps |
| T1258 |
/workspace/coverage/default/1.chip_sw_pwrmgr_full_aon_reset.4284413137 |
|
|
Mar 19 03:50:24 PM PDT 24 |
Mar 19 03:57:31 PM PDT 24 |
7233017100 ps |
| T1259 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3301812342 |
|
|
Mar 19 03:55:10 PM PDT 24 |
Mar 19 04:31:28 PM PDT 24 |
8212784858 ps |
| T1260 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_rma.1332154175 |
|
|
Mar 19 03:56:00 PM PDT 24 |
Mar 19 04:19:43 PM PDT 24 |
7898033612 ps |
| T1261 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_otbn_trans.4080328501 |
|
|
Mar 19 03:46:26 PM PDT 24 |
Mar 19 03:54:28 PM PDT 24 |
4904302752 ps |
| T742 |
/workspace/coverage/default/14.chip_sw_all_escalation_resets.527612793 |
|
|
Mar 19 04:07:13 PM PDT 24 |
Mar 19 04:17:21 PM PDT 24 |
5739917602 ps |
| T1262 |
/workspace/coverage/default/0.rom_volatile_raw_unlock.1938696850 |
|
|
Mar 19 03:47:15 PM PDT 24 |
Mar 19 03:49:01 PM PDT 24 |
1982739620 ps |
| T1263 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.922845942 |
|
|
Mar 19 04:14:18 PM PDT 24 |
Mar 19 04:24:51 PM PDT 24 |
5429106514 ps |
| T1264 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.2527146343 |
|
|
Mar 19 03:48:16 PM PDT 24 |
Mar 19 03:52:46 PM PDT 24 |
3008160000 ps |
| T1265 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.3583733047 |
|
|
Mar 19 03:50:32 PM PDT 24 |
Mar 19 03:59:37 PM PDT 24 |
5810893582 ps |
| T746 |
/workspace/coverage/default/89.chip_sw_all_escalation_resets.917639487 |
|
|
Mar 19 04:14:11 PM PDT 24 |
Mar 19 04:23:45 PM PDT 24 |
5731428704 ps |
| T1266 |
/workspace/coverage/default/0.chip_sw_uart_smoketest.2933587907 |
|
|
Mar 19 03:53:17 PM PDT 24 |
Mar 19 03:57:49 PM PDT 24 |
2920764062 ps |
| T776 |
/workspace/coverage/default/28.chip_sw_alert_handler_lpg_sleep_mode_alerts.2796517860 |
|
|
Mar 19 04:10:23 PM PDT 24 |
Mar 19 04:16:17 PM PDT 24 |
3563974368 ps |
| T1267 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.2542693012 |
|
|
Mar 19 03:59:18 PM PDT 24 |
Mar 19 04:10:16 PM PDT 24 |
4668480065 ps |
| T1268 |
/workspace/coverage/default/1.chip_sw_aes_entropy.1251548214 |
|
|
Mar 19 03:48:51 PM PDT 24 |
Mar 19 03:53:20 PM PDT 24 |
2540096920 ps |
| T1269 |
/workspace/coverage/default/1.chip_sw_clkmgr_jitter_reduced_freq.3710905646 |
|
|
Mar 19 03:50:47 PM PDT 24 |
Mar 19 03:53:25 PM PDT 24 |
3038812311 ps |
| T1270 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_smoketest.2429485650 |
|
|
Mar 19 03:53:55 PM PDT 24 |
Mar 19 03:58:25 PM PDT 24 |
3430888218 ps |
| T1271 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.1377620424 |
|
|
Mar 19 03:53:17 PM PDT 24 |
Mar 19 03:56:40 PM PDT 24 |
2631819880 ps |
| T1272 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_otbn_trans.614669428 |
|
|
Mar 19 04:02:43 PM PDT 24 |
Mar 19 04:09:40 PM PDT 24 |
4450070680 ps |
| T47 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.1098819231 |
|
|
Mar 19 03:46:48 PM PDT 24 |
Mar 19 03:51:58 PM PDT 24 |
3224990232 ps |
| T787 |
/workspace/coverage/default/1.chip_sw_all_escalation_resets.2832368285 |
|
|
Mar 19 03:49:03 PM PDT 24 |
Mar 19 04:01:35 PM PDT 24 |
6259847586 ps |
| T1273 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.2909857338 |
|
|
Mar 19 03:47:29 PM PDT 24 |
Mar 19 03:52:11 PM PDT 24 |
4755561808 ps |
| T1274 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.1692647767 |
|
|
Mar 19 03:54:25 PM PDT 24 |
Mar 19 03:58:59 PM PDT 24 |
2633117728 ps |
| T1275 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.1803633032 |
|
|
Mar 19 04:03:04 PM PDT 24 |
Mar 19 04:16:21 PM PDT 24 |
5614965928 ps |
| T328 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2892224654 |
|
|
Mar 19 04:00:02 PM PDT 24 |
Mar 19 04:10:48 PM PDT 24 |
19098494560 ps |
| T1276 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.133836834 |
|
|
Mar 19 03:47:09 PM PDT 24 |
Mar 19 03:51:03 PM PDT 24 |
3035968130 ps |
| T1277 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.95924783 |
|
|
Mar 19 04:11:43 PM PDT 24 |
Mar 19 04:24:24 PM PDT 24 |
4860221016 ps |
| T1278 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod.2454488538 |
|
|
Mar 19 03:57:36 PM PDT 24 |
Mar 19 04:35:51 PM PDT 24 |
8070249088 ps |
| T1279 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.2221346101 |
|
|
Mar 19 03:50:45 PM PDT 24 |
Mar 19 03:54:23 PM PDT 24 |
2762618658 ps |
| T1280 |
/workspace/coverage/default/4.chip_tap_straps_dev.617843223 |
|
|
Mar 19 04:05:17 PM PDT 24 |
Mar 19 04:11:28 PM PDT 24 |
4043605956 ps |
| T1281 |
/workspace/coverage/default/0.rom_e2e_asm_init_prod.3078586830 |
|
|
Mar 19 03:53:07 PM PDT 24 |
Mar 19 04:33:16 PM PDT 24 |
9271848729 ps |
| T778 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1497042027 |
|
|
Mar 19 04:11:57 PM PDT 24 |
Mar 19 04:24:26 PM PDT 24 |
5114876064 ps |
| T1282 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.1555706551 |
|
|
Mar 19 03:58:38 PM PDT 24 |
Mar 19 04:14:10 PM PDT 24 |
7502406650 ps |
| T387 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.3484812484 |
|
|
Mar 19 03:49:53 PM PDT 24 |
Mar 19 03:58:17 PM PDT 24 |
7137630128 ps |
| T246 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_address_translation.4237697206 |
|
|
Mar 19 03:47:36 PM PDT 24 |
Mar 19 03:50:20 PM PDT 24 |
2318941200 ps |
| T1283 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_clock_freqs.2241702992 |
|
|
Mar 19 03:47:51 PM PDT 24 |
Mar 19 04:05:09 PM PDT 24 |
5575230602 ps |
| T1284 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_dev.2092181096 |
|
|
Mar 19 03:47:35 PM PDT 24 |
Mar 19 04:13:13 PM PDT 24 |
7655816120 ps |
| T1285 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2191125998 |
|
|
Mar 19 03:47:27 PM PDT 24 |
Mar 19 03:56:39 PM PDT 24 |
3646189928 ps |
| T1286 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.1646238277 |
|
|
Mar 19 03:56:24 PM PDT 24 |
Mar 19 04:16:58 PM PDT 24 |
6219787792 ps |
| T1287 |
/workspace/coverage/default/2.rom_e2e_asm_init_dev.3005718050 |
|
|
Mar 19 04:08:38 PM PDT 24 |
Mar 19 04:42:05 PM PDT 24 |
8358503484 ps |
| T329 |
/workspace/coverage/default/1.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2538312760 |
|
|
Mar 19 03:48:05 PM PDT 24 |
Mar 19 03:54:26 PM PDT 24 |
18686768944 ps |
| T334 |
/workspace/coverage/default/0.chip_sw_hmac_enc_jitter_en.3411829261 |
|
|
Mar 19 03:45:49 PM PDT 24 |
Mar 19 03:50:11 PM PDT 24 |
3132764904 ps |
| T1288 |
/workspace/coverage/default/1.chip_sw_aes_enc.1320969271 |
|
|
Mar 19 03:47:11 PM PDT 24 |
Mar 19 03:52:56 PM PDT 24 |
3024666664 ps |
| T696 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.2366627710 |
|
|
Mar 19 03:46:56 PM PDT 24 |
Mar 19 03:52:30 PM PDT 24 |
4403247140 ps |
| T733 |
/workspace/coverage/default/75.chip_sw_alert_handler_lpg_sleep_mode_alerts.1605963551 |
|
|
Mar 19 04:12:51 PM PDT 24 |
Mar 19 04:18:57 PM PDT 24 |
4209235412 ps |
| T247 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_icache_invalidate.779045216 |
|
|
Mar 19 04:03:40 PM PDT 24 |
Mar 19 04:08:02 PM PDT 24 |
2988871196 ps |
| T1289 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.4160120519 |
|
|
Mar 19 04:10:00 PM PDT 24 |
Mar 19 04:17:25 PM PDT 24 |
3712561560 ps |
| T201 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.1309126842 |
|
|
Mar 19 03:47:24 PM PDT 24 |
Mar 19 03:56:25 PM PDT 24 |
3937612784 ps |
| T1290 |
/workspace/coverage/default/10.chip_sw_lc_ctrl_transition.3500418255 |
|
|
Mar 19 04:08:56 PM PDT 24 |
Mar 19 04:23:40 PM PDT 24 |
8982709096 ps |
| T237 |
/workspace/coverage/default/20.chip_sw_alert_handler_lpg_sleep_mode_alerts.3480284832 |
|
|
Mar 19 04:10:40 PM PDT 24 |
Mar 19 04:17:25 PM PDT 24 |
4085419544 ps |
| T1291 |
/workspace/coverage/default/12.chip_sw_uart_rand_baudrate.3583696761 |
|
|
Mar 19 04:07:26 PM PDT 24 |
Mar 19 05:09:22 PM PDT 24 |
22697266229 ps |
| T1292 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1801144948 |
|
|
Mar 19 03:54:53 PM PDT 24 |
Mar 19 04:21:41 PM PDT 24 |
7414206630 ps |
| T1293 |
/workspace/coverage/default/92.chip_sw_all_escalation_resets.1558964621 |
|
|
Mar 19 04:13:37 PM PDT 24 |
Mar 19 04:23:04 PM PDT 24 |
4706530672 ps |
| T760 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2471300602 |
|
|
Mar 19 04:11:29 PM PDT 24 |
Mar 19 04:22:33 PM PDT 24 |
5626889330 ps |
| T785 |
/workspace/coverage/default/51.chip_sw_alert_handler_lpg_sleep_mode_alerts.1797321413 |
|
|
Mar 19 04:13:24 PM PDT 24 |
Mar 19 04:20:11 PM PDT 24 |
4065049100 ps |
| T1294 |
/workspace/coverage/default/2.chip_sw_aes_entropy.598753320 |
|
|
Mar 19 04:03:23 PM PDT 24 |
Mar 19 04:07:47 PM PDT 24 |
2953966724 ps |
| T66 |
/workspace/coverage/cover_reg_top/99.xbar_access_same_device.1179386930 |
|
|
Mar 19 04:30:50 PM PDT 24 |
Mar 19 04:31:40 PM PDT 24 |
1057390827 ps |
| T67 |
/workspace/coverage/cover_reg_top/69.xbar_stress_all_with_rand_reset.1842877450 |
|
|
Mar 19 04:26:23 PM PDT 24 |
Mar 19 04:28:04 PM PDT 24 |
234487376 ps |
| T68 |
/workspace/coverage/cover_reg_top/4.chip_csr_rw.2814482812 |
|
|
Mar 19 04:10:48 PM PDT 24 |
Mar 19 04:22:31 PM PDT 24 |
5916957920 ps |
| T72 |
/workspace/coverage/cover_reg_top/22.xbar_random_zero_delays.2880076569 |
|
|
Mar 19 04:18:18 PM PDT 24 |
Mar 19 04:18:48 PM PDT 24 |
250298515 ps |
| T73 |
/workspace/coverage/cover_reg_top/39.xbar_error_random.3634913068 |
|
|
Mar 19 04:21:55 PM PDT 24 |
Mar 19 04:22:49 PM PDT 24 |
596909108 ps |
| T74 |
/workspace/coverage/cover_reg_top/81.xbar_smoke.867131838 |
|
|
Mar 19 04:27:54 PM PDT 24 |
Mar 19 04:28:04 PM PDT 24 |
148559233 ps |
| T210 |
/workspace/coverage/cover_reg_top/24.xbar_error_and_unmapped_addr.4264811714 |
|
|
Mar 19 04:19:01 PM PDT 24 |
Mar 19 04:19:31 PM PDT 24 |
606586494 ps |
| T405 |
/workspace/coverage/cover_reg_top/39.xbar_same_source.4203910922 |
|
|
Mar 19 04:21:49 PM PDT 24 |
Mar 19 04:22:13 PM PDT 24 |
717645832 ps |
| T406 |
/workspace/coverage/cover_reg_top/73.xbar_stress_all.499380686 |
|
|
Mar 19 04:26:46 PM PDT 24 |
Mar 19 04:30:19 PM PDT 24 |
1913385171 ps |
| T388 |
/workspace/coverage/cover_reg_top/30.xbar_access_same_device_slow_rsp.900667463 |
|
|
Mar 19 04:20:11 PM PDT 24 |
Mar 19 04:39:40 PM PDT 24 |
64781078597 ps |
| T502 |
/workspace/coverage/cover_reg_top/87.xbar_smoke_large_delays.1360873746 |
|
|
Mar 19 04:29:01 PM PDT 24 |
Mar 19 04:30:23 PM PDT 24 |
6997630567 ps |
| T496 |
/workspace/coverage/cover_reg_top/28.xbar_unmapped_addr.1408575618 |
|
|
Mar 19 04:19:54 PM PDT 24 |
Mar 19 04:20:35 PM PDT 24 |
880073594 ps |
| T404 |
/workspace/coverage/cover_reg_top/26.xbar_stress_all_with_reset_error.2160172095 |
|
|
Mar 19 04:19:35 PM PDT 24 |
Mar 19 04:22:57 PM PDT 24 |
672731104 ps |
| T720 |
/workspace/coverage/cover_reg_top/6.xbar_stress_all_with_reset_error.2372561893 |
|
|
Mar 19 04:11:52 PM PDT 24 |
Mar 19 04:12:16 PM PDT 24 |
51016785 ps |
| T498 |
/workspace/coverage/cover_reg_top/52.xbar_stress_all_with_reset_error.314459320 |
|
|
Mar 19 04:23:44 PM PDT 24 |
Mar 19 04:28:11 PM PDT 24 |
4173452442 ps |
| T505 |
/workspace/coverage/cover_reg_top/88.xbar_unmapped_addr.731358526 |
|
|
Mar 19 04:29:12 PM PDT 24 |
Mar 19 04:29:23 PM PDT 24 |
70174222 ps |
| T501 |
/workspace/coverage/cover_reg_top/82.xbar_smoke_large_delays.3915653928 |
|
|
Mar 19 04:28:01 PM PDT 24 |
Mar 19 04:29:29 PM PDT 24 |
8227575762 ps |
| T459 |
/workspace/coverage/cover_reg_top/66.xbar_unmapped_addr.3559311702 |
|
|
Mar 19 04:25:40 PM PDT 24 |
Mar 19 04:26:23 PM PDT 24 |
964971263 ps |
| T470 |
/workspace/coverage/cover_reg_top/94.xbar_smoke_slow_rsp.420704105 |
|
|
Mar 19 04:30:07 PM PDT 24 |
Mar 19 04:31:33 PM PDT 24 |
4537494459 ps |
| T507 |
/workspace/coverage/cover_reg_top/65.xbar_smoke_slow_rsp.1896449971 |
|
|
Mar 19 04:25:35 PM PDT 24 |
Mar 19 04:27:15 PM PDT 24 |
5447181907 ps |
| T495 |
/workspace/coverage/cover_reg_top/62.xbar_stress_all_with_reset_error.2408498351 |
|
|
Mar 19 04:25:17 PM PDT 24 |
Mar 19 04:34:23 PM PDT 24 |
9698386954 ps |
| T408 |
/workspace/coverage/cover_reg_top/77.xbar_random_large_delays.3624055177 |
|
|
Mar 19 04:27:30 PM PDT 24 |
Mar 19 04:49:27 PM PDT 24 |
118152623362 ps |
| T336 |
/workspace/coverage/cover_reg_top/3.chip_csr_rw.3273007121 |
|
|
Mar 19 04:10:09 PM PDT 24 |
Mar 19 04:20:15 PM PDT 24 |
5255637520 ps |
| T500 |
/workspace/coverage/cover_reg_top/43.xbar_stress_all.3023287343 |
|
|
Mar 19 04:22:21 PM PDT 24 |
Mar 19 04:23:07 PM PDT 24 |
920802173 ps |
| T394 |
/workspace/coverage/cover_reg_top/12.xbar_random_zero_delays.2711560663 |
|
|
Mar 19 04:14:31 PM PDT 24 |
Mar 19 04:15:22 PM PDT 24 |
525649082 ps |
| T506 |
/workspace/coverage/cover_reg_top/86.xbar_error_and_unmapped_addr.3994247607 |
|
|
Mar 19 04:28:52 PM PDT 24 |
Mar 19 04:29:09 PM PDT 24 |
132796745 ps |
| T434 |
/workspace/coverage/cover_reg_top/80.xbar_smoke_slow_rsp.3754081312 |
|
|
Mar 19 04:27:47 PM PDT 24 |
Mar 19 04:29:35 PM PDT 24 |
6087149887 ps |
| T504 |
/workspace/coverage/cover_reg_top/31.xbar_smoke.714996185 |
|
|
Mar 19 04:20:10 PM PDT 24 |
Mar 19 04:20:16 PM PDT 24 |
37018171 ps |
| T389 |
/workspace/coverage/cover_reg_top/23.xbar_random_slow_rsp.3503840747 |
|
|
Mar 19 04:18:41 PM PDT 24 |
Mar 19 04:38:52 PM PDT 24 |
63642184273 ps |
| T599 |
/workspace/coverage/cover_reg_top/83.xbar_same_source.2212469756 |
|
|
Mar 19 04:28:21 PM PDT 24 |
Mar 19 04:28:36 PM PDT 24 |
401786355 ps |
| T880 |
/workspace/coverage/cover_reg_top/2.chip_prim_tl_access.1916461747 |
|
|
Mar 19 04:08:58 PM PDT 24 |
Mar 19 04:13:58 PM PDT 24 |
6227737326 ps |
| T831 |
/workspace/coverage/cover_reg_top/8.xbar_access_same_device_slow_rsp.4136417602 |
|
|
Mar 19 04:12:37 PM PDT 24 |
Mar 19 04:16:16 PM PDT 24 |
11940252339 ps |
| T497 |
/workspace/coverage/cover_reg_top/55.xbar_random.3569568060 |
|
|
Mar 19 04:24:01 PM PDT 24 |
Mar 19 04:25:47 PM PDT 24 |
2402143138 ps |
| T499 |
/workspace/coverage/cover_reg_top/25.chip_tl_errors.3200244158 |
|
|
Mar 19 04:18:59 PM PDT 24 |
Mar 19 04:23:55 PM PDT 24 |
3473967930 ps |
| T825 |
/workspace/coverage/cover_reg_top/14.xbar_access_same_device.3295301490 |
|
|
Mar 19 04:15:04 PM PDT 24 |
Mar 19 04:15:38 PM PDT 24 |
369140890 ps |
| T630 |
/workspace/coverage/cover_reg_top/87.xbar_same_source.71027175 |
|
|
Mar 19 04:29:04 PM PDT 24 |
Mar 19 04:29:19 PM PDT 24 |
379530470 ps |
| T858 |
/workspace/coverage/cover_reg_top/31.xbar_stress_all_with_reset_error.1712970617 |
|
|
Mar 19 04:20:23 PM PDT 24 |
Mar 19 04:20:48 PM PDT 24 |
10042520 ps |
| T568 |
/workspace/coverage/cover_reg_top/34.xbar_stress_all_with_rand_reset.3042721323 |
|
|
Mar 19 04:20:54 PM PDT 24 |
Mar 19 04:21:24 PM PDT 24 |
40052883 ps |
| T1295 |
/workspace/coverage/cover_reg_top/29.xbar_smoke_large_delays.1913142329 |
|
|
Mar 19 04:19:50 PM PDT 24 |
Mar 19 04:21:01 PM PDT 24 |
6411009627 ps |
| T604 |
/workspace/coverage/cover_reg_top/15.xbar_unmapped_addr.2596215022 |
|
|
Mar 19 04:15:56 PM PDT 24 |
Mar 19 04:16:36 PM PDT 24 |
750655977 ps |
| T647 |
/workspace/coverage/cover_reg_top/23.xbar_stress_all_with_reset_error.1845701663 |
|
|
Mar 19 04:18:41 PM PDT 24 |
Mar 19 04:22:06 PM PDT 24 |
528030299 ps |
| T810 |
/workspace/coverage/cover_reg_top/6.xbar_access_same_device.3619008657 |
|
|
Mar 19 04:11:18 PM PDT 24 |
Mar 19 04:12:13 PM PDT 24 |
615180448 ps |
| T605 |
/workspace/coverage/cover_reg_top/4.xbar_same_source.339584349 |
|
|
Mar 19 04:10:22 PM PDT 24 |
Mar 19 04:10:46 PM PDT 24 |
268554300 ps |
| T607 |
/workspace/coverage/cover_reg_top/80.xbar_stress_all_with_rand_reset.3737701501 |
|
|
Mar 19 04:27:55 PM PDT 24 |
Mar 19 04:31:21 PM PDT 24 |
649143845 ps |
| T503 |
/workspace/coverage/cover_reg_top/13.xbar_stress_all_with_reset_error.1578408792 |
|
|
Mar 19 04:14:51 PM PDT 24 |
Mar 19 04:19:33 PM PDT 24 |
1550804222 ps |
| T477 |
/workspace/coverage/cover_reg_top/44.xbar_smoke_slow_rsp.1973934424 |
|
|
Mar 19 04:22:36 PM PDT 24 |
Mar 19 04:23:59 PM PDT 24 |
4617089878 ps |
| T374 |
/workspace/coverage/cover_reg_top/35.xbar_stress_all_with_rand_reset.2899375794 |
|
|
Mar 19 04:21:14 PM PDT 24 |
Mar 19 04:26:13 PM PDT 24 |
1824780809 ps |
| T393 |
/workspace/coverage/cover_reg_top/19.xbar_same_source.2797533237 |
|
|
Mar 19 04:17:12 PM PDT 24 |
Mar 19 04:17:45 PM PDT 24 |
376599374 ps |
| T841 |
/workspace/coverage/cover_reg_top/80.xbar_access_same_device.2813226911 |
|
|
Mar 19 04:27:48 PM PDT 24 |
Mar 19 04:28:31 PM PDT 24 |
508692539 ps |
| T1296 |
/workspace/coverage/cover_reg_top/50.xbar_error_and_unmapped_addr.3065295992 |
|
|
Mar 19 04:23:37 PM PDT 24 |
Mar 19 04:23:59 PM PDT 24 |
480680069 ps |
| T560 |
/workspace/coverage/cover_reg_top/79.xbar_same_source.3404772923 |
|
|
Mar 19 04:27:44 PM PDT 24 |
Mar 19 04:27:53 PM PDT 24 |
91772694 ps |
| T488 |
/workspace/coverage/cover_reg_top/98.xbar_random_large_delays.2341455648 |
|
|
Mar 19 04:30:58 PM PDT 24 |
Mar 19 04:47:57 PM PDT 24 |
101054504195 ps |
| T508 |
/workspace/coverage/cover_reg_top/11.xbar_random_large_delays.863849202 |
|
|
Mar 19 04:13:58 PM PDT 24 |
Mar 19 04:17:05 PM PDT 24 |
15859972531 ps |
| T610 |
/workspace/coverage/cover_reg_top/14.xbar_smoke_zero_delays.1729920873 |
|
|
Mar 19 04:15:04 PM PDT 24 |
Mar 19 04:15:12 PM PDT 24 |
51373130 ps |
| T525 |
/workspace/coverage/cover_reg_top/77.xbar_stress_all_with_rand_reset.2210316261 |
|
|
Mar 19 04:27:24 PM PDT 24 |
Mar 19 04:29:19 PM PDT 24 |
182098878 ps |
| T172 |
/workspace/coverage/cover_reg_top/18.chip_same_csr_outstanding.1401916975 |
|
|
Mar 19 04:16:59 PM PDT 24 |
Mar 19 05:15:47 PM PDT 24 |
29626775086 ps |
| T449 |
/workspace/coverage/cover_reg_top/54.xbar_stress_all.1573779908 |
|
|
Mar 19 04:23:52 PM PDT 24 |
Mar 19 04:35:21 PM PDT 24 |
16656793353 ps |
| T569 |
/workspace/coverage/cover_reg_top/23.xbar_unmapped_addr.1622931139 |
|
|
Mar 19 04:18:39 PM PDT 24 |
Mar 19 04:19:21 PM PDT 24 |
286087150 ps |
| T173 |
/workspace/coverage/cover_reg_top/0.chip_csr_aliasing.2729724591 |
|
|
Mar 19 04:06:49 PM PDT 24 |
Mar 19 06:51:53 PM PDT 24 |
55494001405 ps |
| T1297 |
/workspace/coverage/cover_reg_top/25.xbar_error_random.1544357819 |
|
|
Mar 19 04:19:06 PM PDT 24 |
Mar 19 04:19:15 PM PDT 24 |
69061141 ps |
| T517 |
/workspace/coverage/cover_reg_top/13.xbar_random_zero_delays.1332298251 |
|
|
Mar 19 04:14:39 PM PDT 24 |
Mar 19 04:15:36 PM PDT 24 |
502602924 ps |
| T635 |
/workspace/coverage/cover_reg_top/54.xbar_unmapped_addr.1283018221 |
|
|
Mar 19 04:24:00 PM PDT 24 |
Mar 19 04:24:39 PM PDT 24 |
896422881 ps |
| T447 |
/workspace/coverage/cover_reg_top/9.xbar_unmapped_addr.4065040522 |
|
|
Mar 19 04:13:08 PM PDT 24 |
Mar 19 04:13:22 PM PDT 24 |
215745542 ps |
| T561 |
/workspace/coverage/cover_reg_top/24.xbar_smoke_large_delays.654367767 |
|
|
Mar 19 04:19:02 PM PDT 24 |
Mar 19 04:20:23 PM PDT 24 |
7366146707 ps |
| T671 |
/workspace/coverage/cover_reg_top/25.xbar_access_same_device.289145480 |
|
|
Mar 19 04:19:02 PM PDT 24 |
Mar 19 04:20:32 PM PDT 24 |
1883431197 ps |
| T438 |
/workspace/coverage/cover_reg_top/0.xbar_random.4044189592 |
|
|
Mar 19 04:07:02 PM PDT 24 |
Mar 19 04:08:22 PM PDT 24 |
2011672242 ps |
| T1298 |
/workspace/coverage/cover_reg_top/74.xbar_smoke.2633615492 |
|
|
Mar 19 04:26:47 PM PDT 24 |
Mar 19 04:26:57 PM PDT 24 |
147417578 ps |
| T623 |
/workspace/coverage/cover_reg_top/0.xbar_smoke_zero_delays.2413807671 |
|
|
Mar 19 04:07:05 PM PDT 24 |
Mar 19 04:07:11 PM PDT 24 |
41035252 ps |
| T414 |
/workspace/coverage/cover_reg_top/88.xbar_random_slow_rsp.977671590 |
|
|
Mar 19 04:29:11 PM PDT 24 |
Mar 19 04:43:34 PM PDT 24 |
49103743587 ps |
| T644 |
/workspace/coverage/cover_reg_top/92.xbar_smoke.2645023282 |
|
|
Mar 19 04:29:53 PM PDT 24 |
Mar 19 04:30:00 PM PDT 24 |
44356857 ps |
| T1299 |
/workspace/coverage/cover_reg_top/29.xbar_smoke_zero_delays.2142485610 |
|
|
Mar 19 04:19:51 PM PDT 24 |
Mar 19 04:19:58 PM PDT 24 |
55368411 ps |
| T509 |
/workspace/coverage/cover_reg_top/14.chip_tl_errors.174570249 |
|
|
Mar 19 04:14:51 PM PDT 24 |
Mar 19 04:19:49 PM PDT 24 |
4139393417 ps |
| T1300 |
/workspace/coverage/cover_reg_top/70.xbar_error_and_unmapped_addr.569119616 |
|
|
Mar 19 04:26:28 PM PDT 24 |
Mar 19 04:26:40 PM PDT 24 |
246341022 ps |
| T409 |
/workspace/coverage/cover_reg_top/15.xbar_stress_all_with_rand_reset.1979099866 |
|
|
Mar 19 04:15:58 PM PDT 24 |
Mar 19 04:22:40 PM PDT 24 |
2290947595 ps |
| T835 |
/workspace/coverage/cover_reg_top/36.xbar_access_same_device.3313146552 |
|
|
Mar 19 04:21:19 PM PDT 24 |
Mar 19 04:22:47 PM PDT 24 |
2014472452 ps |
| T1301 |
/workspace/coverage/cover_reg_top/21.xbar_smoke_zero_delays.778511350 |
|
|
Mar 19 04:18:05 PM PDT 24 |
Mar 19 04:18:12 PM PDT 24 |
46389437 ps |
| T601 |
/workspace/coverage/cover_reg_top/55.xbar_random_zero_delays.1939306766 |
|
|
Mar 19 04:24:00 PM PDT 24 |
Mar 19 04:24:06 PM PDT 24 |
40427886 ps |