| T20 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_reset.2499226183 |
|
|
Mar 19 03:50:43 PM PDT 24 |
Mar 19 04:16:20 PM PDT 24 |
23141712112 ps |
| T1033 |
/workspace/coverage/default/0.chip_sw_alert_handler_ping_timeout.2994448337 |
|
|
Mar 19 03:49:43 PM PDT 24 |
Mar 19 03:55:24 PM PDT 24 |
3298852512 ps |
| T1034 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.2994423702 |
|
|
Mar 19 04:07:24 PM PDT 24 |
Mar 19 04:20:14 PM PDT 24 |
5614601862 ps |
| T1035 |
/workspace/coverage/default/1.rom_e2e_static_critical.2003353853 |
|
|
Mar 19 03:53:51 PM PDT 24 |
Mar 19 04:34:02 PM PDT 24 |
10705340962 ps |
| T774 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.3123022830 |
|
|
Mar 19 04:12:59 PM PDT 24 |
Mar 19 04:18:54 PM PDT 24 |
3272194938 ps |
| T1036 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_inputs.1238309246 |
|
|
Mar 19 03:45:36 PM PDT 24 |
Mar 19 03:51:44 PM PDT 24 |
3587748717 ps |
| T7 |
/workspace/coverage/default/2.chip_sw_sleep_pin_mio_dio_val.2373240031 |
|
|
Mar 19 03:54:26 PM PDT 24 |
Mar 19 03:59:30 PM PDT 24 |
3488763451 ps |
| T779 |
/workspace/coverage/default/74.chip_sw_alert_handler_lpg_sleep_mode_alerts.2266962468 |
|
|
Mar 19 04:11:52 PM PDT 24 |
Mar 19 04:16:19 PM PDT 24 |
3258782600 ps |
| T1037 |
/workspace/coverage/default/0.chip_sw_aon_timer_sleep_wdog_sleep_pause.3054651096 |
|
|
Mar 19 03:46:37 PM PDT 24 |
Mar 19 03:55:26 PM PDT 24 |
7141349190 ps |
| T1038 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2311781866 |
|
|
Mar 19 03:57:34 PM PDT 24 |
Mar 19 04:33:23 PM PDT 24 |
8908918964 ps |
| T1039 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.3106078677 |
|
|
Mar 19 03:45:17 PM PDT 24 |
Mar 19 03:48:25 PM PDT 24 |
2513159096 ps |
| T1040 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.2969179227 |
|
|
Mar 19 03:44:23 PM PDT 24 |
Mar 19 04:09:40 PM PDT 24 |
12129809235 ps |
| T772 |
/workspace/coverage/default/83.chip_sw_all_escalation_resets.3010485207 |
|
|
Mar 19 04:13:04 PM PDT 24 |
Mar 19 04:21:12 PM PDT 24 |
5548192482 ps |
| T1041 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.1821878047 |
|
|
Mar 19 03:50:18 PM PDT 24 |
Mar 19 04:49:54 PM PDT 24 |
18360458482 ps |
| T1042 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.1316259424 |
|
|
Mar 19 03:55:39 PM PDT 24 |
Mar 19 04:29:26 PM PDT 24 |
8565072116 ps |
| T1043 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3039644158 |
|
|
Mar 19 03:59:50 PM PDT 24 |
Mar 19 04:05:40 PM PDT 24 |
2594156138 ps |
| T1044 |
/workspace/coverage/default/1.chip_sw_hmac_enc_idle.3776328001 |
|
|
Mar 19 03:49:53 PM PDT 24 |
Mar 19 03:55:03 PM PDT 24 |
3206359696 ps |
| T1045 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.325029152 |
|
|
Mar 19 03:49:31 PM PDT 24 |
Mar 19 03:58:00 PM PDT 24 |
3845688228 ps |
| T1046 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod_end.1587516969 |
|
|
Mar 19 03:52:45 PM PDT 24 |
Mar 19 04:28:07 PM PDT 24 |
8517484500 ps |
| T1047 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.1812850454 |
|
|
Mar 19 04:03:13 PM PDT 24 |
Mar 19 04:13:58 PM PDT 24 |
4433440420 ps |
| T1048 |
/workspace/coverage/default/1.chip_sw_aon_timer_irq.54551256 |
|
|
Mar 19 03:50:57 PM PDT 24 |
Mar 19 03:57:16 PM PDT 24 |
4363223508 ps |
| T292 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3155314289 |
|
|
Mar 19 03:46:45 PM PDT 24 |
Mar 19 03:56:29 PM PDT 24 |
3562147605 ps |
| T1049 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.2574776871 |
|
|
Mar 19 03:59:03 PM PDT 24 |
Mar 19 04:09:42 PM PDT 24 |
5774810760 ps |
| T1050 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_power_glitch_reset.2309055833 |
|
|
Mar 19 03:47:12 PM PDT 24 |
Mar 19 03:52:59 PM PDT 24 |
6224185376 ps |
| T261 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_otbn.3987203591 |
|
|
Mar 19 03:45:37 PM PDT 24 |
Mar 19 05:12:01 PM PDT 24 |
19251401520 ps |
| T1051 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.1340237934 |
|
|
Mar 19 03:48:18 PM PDT 24 |
Mar 19 03:53:53 PM PDT 24 |
2891446186 ps |
| T121 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3890466691 |
|
|
Mar 19 03:48:32 PM PDT 24 |
Mar 19 03:59:31 PM PDT 24 |
5738015136 ps |
| T1052 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.1778899407 |
|
|
Mar 19 04:03:49 PM PDT 24 |
Mar 19 04:10:40 PM PDT 24 |
3839630472 ps |
| T1053 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2568257105 |
|
|
Mar 19 03:56:28 PM PDT 24 |
Mar 19 05:24:10 PM PDT 24 |
50128479062 ps |
| T25 |
/workspace/coverage/default/2.chip_sw_gpio.810171948 |
|
|
Mar 19 03:53:13 PM PDT 24 |
Mar 19 04:01:09 PM PDT 24 |
4156653636 ps |
| T59 |
/workspace/coverage/default/1.chip_tap_straps_rma.3776967990 |
|
|
Mar 19 03:49:08 PM PDT 24 |
Mar 19 04:07:53 PM PDT 24 |
10279914507 ps |
| T221 |
/workspace/coverage/default/2.chip_sw_rstmgr_cpu_info.2337205211 |
|
|
Mar 19 03:57:50 PM PDT 24 |
Mar 19 04:06:48 PM PDT 24 |
5371620332 ps |
| T1054 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_testunlocks.3558726622 |
|
|
Mar 19 03:56:33 PM PDT 24 |
Mar 19 04:29:31 PM PDT 24 |
22619925288 ps |
| T749 |
/workspace/coverage/default/58.chip_sw_all_escalation_resets.2919442048 |
|
|
Mar 19 04:13:13 PM PDT 24 |
Mar 19 04:21:52 PM PDT 24 |
4043808384 ps |
| T1055 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.1464949371 |
|
|
Mar 19 03:50:28 PM PDT 24 |
Mar 19 03:57:42 PM PDT 24 |
4465226316 ps |
| T1056 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_inputs.1486741468 |
|
|
Mar 19 03:58:19 PM PDT 24 |
Mar 19 04:04:20 PM PDT 24 |
2779737332 ps |
| T106 |
/workspace/coverage/default/0.rom_raw_unlock.187214651 |
|
|
Mar 19 03:51:27 PM PDT 24 |
Mar 19 04:27:52 PM PDT 24 |
16792672067 ps |
| T491 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.371201391 |
|
|
Mar 19 03:59:17 PM PDT 24 |
Mar 19 04:13:36 PM PDT 24 |
5044904146 ps |
| T44 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3957442944 |
|
|
Mar 19 03:48:22 PM PDT 24 |
Mar 19 04:18:18 PM PDT 24 |
19895693252 ps |
| T313 |
/workspace/coverage/default/2.chip_sw_i2c_host_tx_rx_idx2.2830699394 |
|
|
Mar 19 03:56:46 PM PDT 24 |
Mar 19 04:12:23 PM PDT 24 |
5338132844 ps |
| T1057 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.4020133657 |
|
|
Mar 19 04:03:28 PM PDT 24 |
Mar 19 04:12:52 PM PDT 24 |
5648310147 ps |
| T1058 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3312539260 |
|
|
Mar 19 03:56:09 PM PDT 24 |
Mar 19 04:04:48 PM PDT 24 |
3828842744 ps |
| T1059 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2357457256 |
|
|
Mar 19 03:47:25 PM PDT 24 |
Mar 19 03:58:43 PM PDT 24 |
4467989184 ps |
| T46 |
/workspace/coverage/default/0.chip_sw_sleep_pin_retention.100686193 |
|
|
Mar 19 03:49:12 PM PDT 24 |
Mar 19 03:54:20 PM PDT 24 |
3843753440 ps |
| T1060 |
/workspace/coverage/default/12.chip_sw_lc_ctrl_transition.3796954517 |
|
|
Mar 19 04:06:39 PM PDT 24 |
Mar 19 04:26:04 PM PDT 24 |
12962175919 ps |
| T1061 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.79432804 |
|
|
Mar 19 03:46:29 PM PDT 24 |
Mar 19 03:49:16 PM PDT 24 |
2400648468 ps |
| T807 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.1556342879 |
|
|
Mar 19 04:11:09 PM PDT 24 |
Mar 19 04:18:04 PM PDT 24 |
4229138104 ps |
| T1062 |
/workspace/coverage/default/1.chip_sw_entropy_src_smoketest.3436275905 |
|
|
Mar 19 03:54:12 PM PDT 24 |
Mar 19 04:02:36 PM PDT 24 |
3674531826 ps |
| T49 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.3329488564 |
|
|
Mar 19 03:58:06 PM PDT 24 |
Mar 19 04:01:50 PM PDT 24 |
3071639100 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.1325274231 |
|
|
Mar 19 04:04:10 PM PDT 24 |
Mar 19 04:28:00 PM PDT 24 |
9553439852 ps |
| T383 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1196846966 |
|
|
Mar 19 04:09:22 PM PDT 24 |
Mar 19 04:20:40 PM PDT 24 |
5290818154 ps |
| T384 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.2995192497 |
|
|
Mar 19 03:59:24 PM PDT 24 |
Mar 19 04:06:26 PM PDT 24 |
3702807180 ps |
| T332 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops.2630358178 |
|
|
Mar 19 03:54:39 PM PDT 24 |
Mar 19 04:07:34 PM PDT 24 |
3629574980 ps |
| T344 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.2374821313 |
|
|
Mar 19 04:00:32 PM PDT 24 |
Mar 19 04:09:27 PM PDT 24 |
2707706400 ps |
| T385 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.1479055908 |
|
|
Mar 19 04:05:12 PM PDT 24 |
Mar 19 04:07:02 PM PDT 24 |
2205961802 ps |
| T386 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_rma.4070651733 |
|
|
Mar 19 03:53:11 PM PDT 24 |
Mar 19 04:28:09 PM PDT 24 |
8411640080 ps |
| T62 |
/workspace/coverage/default/0.chip_tap_straps_testunlock0.2600852366 |
|
|
Mar 19 03:48:01 PM PDT 24 |
Mar 19 03:52:07 PM PDT 24 |
3423488879 ps |
| T195 |
/workspace/coverage/default/2.chip_sw_inject_scramble_seed.1994892280 |
|
|
Mar 19 03:52:51 PM PDT 24 |
Mar 19 06:49:30 PM PDT 24 |
63461582304 ps |
| T209 |
/workspace/coverage/default/49.chip_sw_all_escalation_resets.1887847400 |
|
|
Mar 19 04:12:42 PM PDT 24 |
Mar 19 04:21:05 PM PDT 24 |
5284030840 ps |
| T800 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.2576119121 |
|
|
Mar 19 04:13:08 PM PDT 24 |
Mar 19 04:22:43 PM PDT 24 |
5490510230 ps |
| T1063 |
/workspace/coverage/default/0.chip_sw_example_rom.3497285708 |
|
|
Mar 19 03:48:41 PM PDT 24 |
Mar 19 03:51:03 PM PDT 24 |
2088299640 ps |
| T1064 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_aes_trans.3646067108 |
|
|
Mar 19 03:47:01 PM PDT 24 |
Mar 19 03:52:46 PM PDT 24 |
4528131210 ps |
| T1065 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation_jitter_en.2420584165 |
|
|
Mar 19 04:02:39 PM PDT 24 |
Mar 19 04:12:31 PM PDT 24 |
5355896770 ps |
| T1066 |
/workspace/coverage/default/2.chip_sw_power_idle_load.2040449181 |
|
|
Mar 19 04:06:46 PM PDT 24 |
Mar 19 04:16:32 PM PDT 24 |
3750283730 ps |
| T727 |
/workspace/coverage/default/64.chip_sw_all_escalation_resets.3677758501 |
|
|
Mar 19 04:14:45 PM PDT 24 |
Mar 19 04:25:14 PM PDT 24 |
4200415212 ps |
| T775 |
/workspace/coverage/default/97.chip_sw_all_escalation_resets.3074792007 |
|
|
Mar 19 04:13:20 PM PDT 24 |
Mar 19 04:25:10 PM PDT 24 |
6157227176 ps |
| T666 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.71354471 |
|
|
Mar 19 03:43:47 PM PDT 24 |
Mar 19 03:45:35 PM PDT 24 |
2061263805 ps |
| T1067 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_peri.3289852931 |
|
|
Mar 19 03:47:36 PM PDT 24 |
Mar 19 04:04:43 PM PDT 24 |
8731624840 ps |
| T1068 |
/workspace/coverage/default/0.chip_sw_otbn_smoketest.2797042477 |
|
|
Mar 19 03:48:51 PM PDT 24 |
Mar 19 04:18:22 PM PDT 24 |
7494200500 ps |
| T1069 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en.2054134177 |
|
|
Mar 19 03:48:01 PM PDT 24 |
Mar 19 03:51:52 PM PDT 24 |
2032108729 ps |
| T262 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2214134034 |
|
|
Mar 19 03:56:25 PM PDT 24 |
Mar 19 05:17:25 PM PDT 24 |
18086993744 ps |
| T1070 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.770012278 |
|
|
Mar 19 03:50:27 PM PDT 24 |
Mar 19 04:00:57 PM PDT 24 |
5385707758 ps |
| T1071 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.674919306 |
|
|
Mar 19 03:55:56 PM PDT 24 |
Mar 19 04:15:47 PM PDT 24 |
5733443476 ps |
| T808 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.4218020459 |
|
|
Mar 19 04:07:09 PM PDT 24 |
Mar 19 04:13:43 PM PDT 24 |
3443664052 ps |
| T755 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.275135830 |
|
|
Mar 19 04:15:47 PM PDT 24 |
Mar 19 04:22:01 PM PDT 24 |
3349118144 ps |
| T1072 |
/workspace/coverage/default/1.chip_sw_kmac_smoketest.80585701 |
|
|
Mar 19 03:54:46 PM PDT 24 |
Mar 19 03:58:58 PM PDT 24 |
2840918898 ps |
| T1073 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.2102515655 |
|
|
Mar 19 04:06:04 PM PDT 24 |
Mar 19 04:11:37 PM PDT 24 |
3619592060 ps |
| T333 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en.1843321568 |
|
|
Mar 19 04:01:20 PM PDT 24 |
Mar 19 04:06:16 PM PDT 24 |
3564258170 ps |
| T169 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3381238878 |
|
|
Mar 19 03:46:43 PM PDT 24 |
Mar 19 03:56:02 PM PDT 24 |
6922043360 ps |
| T752 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.2616498719 |
|
|
Mar 19 04:12:01 PM PDT 24 |
Mar 19 04:18:41 PM PDT 24 |
4051302880 ps |
| T1074 |
/workspace/coverage/default/2.chip_sw_aes_enc.1074463859 |
|
|
Mar 19 03:59:42 PM PDT 24 |
Mar 19 04:05:18 PM PDT 24 |
2987063682 ps |
| T739 |
/workspace/coverage/default/91.chip_sw_all_escalation_resets.1778743123 |
|
|
Mar 19 04:13:15 PM PDT 24 |
Mar 19 04:23:52 PM PDT 24 |
5161754200 ps |
| T1075 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_rma.517645739 |
|
|
Mar 19 03:49:47 PM PDT 24 |
Mar 19 04:45:33 PM PDT 24 |
12869679544 ps |
| T659 |
/workspace/coverage/default/2.chip_sw_rv_dm_access_after_escalation_reset.4169112583 |
|
|
Mar 19 04:02:31 PM PDT 24 |
Mar 19 04:09:50 PM PDT 24 |
4392470834 ps |
| T1076 |
/workspace/coverage/default/1.chip_sival_flash_info_access.584829282 |
|
|
Mar 19 03:53:11 PM PDT 24 |
Mar 19 03:58:21 PM PDT 24 |
3259230390 ps |
| T1077 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.1330010695 |
|
|
Mar 19 03:54:08 PM PDT 24 |
Mar 19 04:03:19 PM PDT 24 |
5028835960 ps |
| T1078 |
/workspace/coverage/default/2.chip_sw_keymgr_key_derivation.2174029304 |
|
|
Mar 19 04:00:56 PM PDT 24 |
Mar 19 04:09:06 PM PDT 24 |
3744602734 ps |
| T1079 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2940597763 |
|
|
Mar 19 03:48:43 PM PDT 24 |
Mar 19 04:08:22 PM PDT 24 |
5242294103 ps |
| T1080 |
/workspace/coverage/default/1.chip_sw_alert_handler_ping_timeout.2656281739 |
|
|
Mar 19 03:46:46 PM PDT 24 |
Mar 19 03:56:23 PM PDT 24 |
5816516376 ps |
| T777 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.136218284 |
|
|
Mar 19 04:14:18 PM PDT 24 |
Mar 19 04:23:46 PM PDT 24 |
4545889332 ps |
| T757 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227081772 |
|
|
Mar 19 04:13:15 PM PDT 24 |
Mar 19 04:19:51 PM PDT 24 |
3540717510 ps |
| T1081 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.2676390425 |
|
|
Mar 19 04:06:18 PM PDT 24 |
Mar 19 04:16:58 PM PDT 24 |
7350913889 ps |
| T803 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_alerts.1323804988 |
|
|
Mar 19 03:46:55 PM PDT 24 |
Mar 19 03:54:53 PM PDT 24 |
3539042392 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.1447792999 |
|
|
Mar 19 04:04:31 PM PDT 24 |
Mar 19 05:23:20 PM PDT 24 |
29265581518 ps |
| T721 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.861887390 |
|
|
Mar 19 04:14:03 PM PDT 24 |
Mar 19 04:27:33 PM PDT 24 |
6080418336 ps |
| T1082 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation.877664983 |
|
|
Mar 19 03:47:48 PM PDT 24 |
Mar 19 03:55:54 PM PDT 24 |
3372328406 ps |
| T1083 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.640478759 |
|
|
Mar 19 03:46:22 PM PDT 24 |
Mar 19 04:23:59 PM PDT 24 |
21680770505 ps |
| T1084 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.329531529 |
|
|
Mar 19 03:48:27 PM PDT 24 |
Mar 19 04:37:19 PM PDT 24 |
11914330770 ps |
| T321 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.2953475130 |
|
|
Mar 19 03:49:43 PM PDT 24 |
Mar 19 04:03:09 PM PDT 24 |
3942675800 ps |
| T296 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2135953342 |
|
|
Mar 19 03:50:04 PM PDT 24 |
Mar 19 04:01:54 PM PDT 24 |
3786879984 ps |
| T1085 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.3211027086 |
|
|
Mar 19 03:49:36 PM PDT 24 |
Mar 19 04:20:25 PM PDT 24 |
7061893658 ps |
| T1086 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.4084316362 |
|
|
Mar 19 03:52:53 PM PDT 24 |
Mar 19 04:25:56 PM PDT 24 |
8073226576 ps |
| T1087 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1509365785 |
|
|
Mar 19 03:59:03 PM PDT 24 |
Mar 19 04:15:18 PM PDT 24 |
5752718102 ps |
| T222 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.2708881030 |
|
|
Mar 19 04:14:53 PM PDT 24 |
Mar 19 04:24:42 PM PDT 24 |
5800150808 ps |
| T1088 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_rma.270311305 |
|
|
Mar 19 03:53:57 PM PDT 24 |
Mar 19 04:26:19 PM PDT 24 |
8988855235 ps |
| T1089 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.664348197 |
|
|
Mar 19 03:53:08 PM PDT 24 |
Mar 19 03:57:39 PM PDT 24 |
2876748124 ps |
| T1090 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.2827119486 |
|
|
Mar 19 03:48:44 PM PDT 24 |
Mar 19 03:58:02 PM PDT 24 |
3706432680 ps |
| T107 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2891696937 |
|
|
Mar 19 03:45:45 PM PDT 24 |
Mar 19 06:49:24 PM PDT 24 |
57981690812 ps |
| T695 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1481870655 |
|
|
Mar 19 03:51:09 PM PDT 24 |
Mar 19 03:56:52 PM PDT 24 |
4008816952 ps |
| T1091 |
/workspace/coverage/default/1.rom_volatile_raw_unlock.2163624943 |
|
|
Mar 19 03:51:31 PM PDT 24 |
Mar 19 03:53:41 PM PDT 24 |
2685422850 ps |
| T492 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.1458636274 |
|
|
Mar 19 03:47:28 PM PDT 24 |
Mar 19 03:59:16 PM PDT 24 |
4669153876 ps |
| T1092 |
/workspace/coverage/default/2.chip_sw_example_manufacturer.220033290 |
|
|
Mar 19 03:53:57 PM PDT 24 |
Mar 19 03:58:05 PM PDT 24 |
2501322400 ps |
| T1093 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rand_to_scrap.706077121 |
|
|
Mar 19 03:46:13 PM PDT 24 |
Mar 19 03:49:02 PM PDT 24 |
2937717302 ps |
| T95 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_all_wake_ups.2995666654 |
|
|
Mar 19 03:51:46 PM PDT 24 |
Mar 19 04:24:23 PM PDT 24 |
22611176580 ps |
| T763 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.1948314056 |
|
|
Mar 19 04:13:23 PM PDT 24 |
Mar 19 04:18:51 PM PDT 24 |
3576305564 ps |
| T1094 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.731439379 |
|
|
Mar 19 04:05:07 PM PDT 24 |
Mar 19 04:09:47 PM PDT 24 |
2863404090 ps |
| T352 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2406803075 |
|
|
Mar 19 04:02:57 PM PDT 24 |
Mar 19 04:06:31 PM PDT 24 |
2565819808 ps |
| T770 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.1460255257 |
|
|
Mar 19 04:07:24 PM PDT 24 |
Mar 19 04:20:28 PM PDT 24 |
6176949164 ps |
| T1095 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.1908825113 |
|
|
Mar 19 04:09:10 PM PDT 24 |
Mar 19 04:45:28 PM PDT 24 |
13189864458 ps |
| T1096 |
/workspace/coverage/default/0.chip_sw_usb_ast_clk_calib.1197530301 |
|
|
Mar 19 03:46:55 PM PDT 24 |
Mar 19 03:51:51 PM PDT 24 |
2788380573 ps |
| T751 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.1450024980 |
|
|
Mar 19 04:12:43 PM PDT 24 |
Mar 19 04:21:50 PM PDT 24 |
4576822360 ps |
| T1097 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation.347052509 |
|
|
Mar 19 03:52:18 PM PDT 24 |
Mar 19 04:00:09 PM PDT 24 |
3591485264 ps |
| T1098 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.1991069666 |
|
|
Mar 19 04:10:02 PM PDT 24 |
Mar 19 04:38:08 PM PDT 24 |
6357325160 ps |
| T1099 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_rand_to_scrap.3541527810 |
|
|
Mar 19 03:56:04 PM PDT 24 |
Mar 19 04:00:10 PM PDT 24 |
3414289278 ps |
| T1100 |
/workspace/coverage/default/1.chip_sw_csrng_kat_test.3311864651 |
|
|
Mar 19 03:51:38 PM PDT 24 |
Mar 19 03:56:12 PM PDT 24 |
2802594272 ps |
| T1101 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.689356998 |
|
|
Mar 19 04:07:21 PM PDT 24 |
Mar 19 04:12:46 PM PDT 24 |
3607775780 ps |
| T48 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.504972757 |
|
|
Mar 19 03:51:36 PM PDT 24 |
Mar 19 03:56:00 PM PDT 24 |
4435718648 ps |
| T375 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_scramble.3542397505 |
|
|
Mar 19 03:46:59 PM PDT 24 |
Mar 19 04:00:46 PM PDT 24 |
8360816008 ps |
| T376 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.441718252 |
|
|
Mar 19 03:52:49 PM PDT 24 |
Mar 19 04:25:59 PM PDT 24 |
9703511364 ps |
| T377 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.2716095026 |
|
|
Mar 19 04:08:15 PM PDT 24 |
Mar 19 04:28:59 PM PDT 24 |
13243550278 ps |
| T309 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.2275353934 |
|
|
Mar 19 03:51:29 PM PDT 24 |
Mar 19 04:04:17 PM PDT 24 |
5173756750 ps |
| T378 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2846596139 |
|
|
Mar 19 04:05:03 PM PDT 24 |
Mar 19 04:09:59 PM PDT 24 |
2810672706 ps |
| T290 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2243694576 |
|
|
Mar 19 03:51:10 PM PDT 24 |
Mar 19 04:01:59 PM PDT 24 |
5052106472 ps |
| T379 |
/workspace/coverage/default/1.chip_sw_example_rom.3703177623 |
|
|
Mar 19 03:48:31 PM PDT 24 |
Mar 19 03:50:19 PM PDT 24 |
2273806382 ps |
| T380 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.246319756 |
|
|
Mar 19 03:47:36 PM PDT 24 |
Mar 19 04:05:48 PM PDT 24 |
7196897170 ps |
| T381 |
/workspace/coverage/default/70.chip_sw_alert_handler_lpg_sleep_mode_alerts.2627167044 |
|
|
Mar 19 04:11:35 PM PDT 24 |
Mar 19 04:17:04 PM PDT 24 |
3735854958 ps |
| T1102 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.4203406721 |
|
|
Mar 19 03:52:55 PM PDT 24 |
Mar 19 04:07:43 PM PDT 24 |
5150603821 ps |
| T793 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.2974815945 |
|
|
Mar 19 04:08:42 PM PDT 24 |
Mar 19 04:16:08 PM PDT 24 |
3622332556 ps |
| T805 |
/workspace/coverage/default/19.chip_sw_all_escalation_resets.1503945988 |
|
|
Mar 19 04:08:40 PM PDT 24 |
Mar 19 04:20:23 PM PDT 24 |
4861268424 ps |
| T1103 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.788098037 |
|
|
Mar 19 03:47:49 PM PDT 24 |
Mar 19 04:07:31 PM PDT 24 |
7358839037 ps |
| T1104 |
/workspace/coverage/default/4.chip_tap_straps_rma.3295137120 |
|
|
Mar 19 04:05:51 PM PDT 24 |
Mar 19 04:16:24 PM PDT 24 |
6093295239 ps |
| T1105 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency.1857575487 |
|
|
Mar 19 04:02:41 PM PDT 24 |
Mar 19 04:40:42 PM PDT 24 |
11051097930 ps |
| T158 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.3739521248 |
|
|
Mar 19 04:03:22 PM PDT 24 |
Mar 19 04:11:32 PM PDT 24 |
5315771528 ps |
| T1106 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.790753698 |
|
|
Mar 19 04:02:41 PM PDT 24 |
Mar 19 04:15:17 PM PDT 24 |
4233226588 ps |
| T1107 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.3748598787 |
|
|
Mar 19 03:51:35 PM PDT 24 |
Mar 19 07:07:17 PM PDT 24 |
58321954968 ps |
| T711 |
/workspace/coverage/default/33.chip_sw_all_escalation_resets.2336867618 |
|
|
Mar 19 04:10:15 PM PDT 24 |
Mar 19 04:20:35 PM PDT 24 |
5181917870 ps |
| T1108 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.109075877 |
|
|
Mar 19 04:08:36 PM PDT 24 |
Mar 19 04:40:37 PM PDT 24 |
8968290473 ps |
| T1109 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac.2689456037 |
|
|
Mar 19 04:01:22 PM PDT 24 |
Mar 19 04:06:28 PM PDT 24 |
2566734486 ps |
| T118 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_vendor_test_csr_access.3763158385 |
|
|
Mar 19 03:55:40 PM PDT 24 |
Mar 19 03:57:07 PM PDT 24 |
2509656002 ps |
| T1110 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.2499068546 |
|
|
Mar 19 03:49:53 PM PDT 24 |
Mar 19 04:44:03 PM PDT 24 |
20745193658 ps |
| T1111 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2519832840 |
|
|
Mar 19 03:49:32 PM PDT 24 |
Mar 19 04:28:30 PM PDT 24 |
9226176912 ps |
| T1112 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2639403121 |
|
|
Mar 19 03:59:31 PM PDT 24 |
Mar 19 04:08:59 PM PDT 24 |
5704335500 ps |
| T1113 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1229949468 |
|
|
Mar 19 03:55:14 PM PDT 24 |
Mar 19 04:03:26 PM PDT 24 |
5383261416 ps |
| T723 |
/workspace/coverage/default/68.chip_sw_all_escalation_resets.2723928350 |
|
|
Mar 19 04:11:32 PM PDT 24 |
Mar 19 04:20:44 PM PDT 24 |
4458441000 ps |
| T366 |
/workspace/coverage/default/1.chip_rv_dm_ndm_reset_req.837622291 |
|
|
Mar 19 03:49:48 PM PDT 24 |
Mar 19 03:57:20 PM PDT 24 |
5026606246 ps |
| T1114 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.92154400 |
|
|
Mar 19 04:00:15 PM PDT 24 |
Mar 19 04:19:04 PM PDT 24 |
9677892300 ps |
| T1115 |
/workspace/coverage/default/2.chip_sival_flash_info_access.2282724666 |
|
|
Mar 19 03:52:53 PM PDT 24 |
Mar 19 03:57:59 PM PDT 24 |
3562274600 ps |
| T1116 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_por_reset.492424450 |
|
|
Mar 19 03:50:18 PM PDT 24 |
Mar 19 03:59:56 PM PDT 24 |
6617342492 ps |
| T1117 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.2334890531 |
|
|
Mar 19 03:52:11 PM PDT 24 |
Mar 19 04:08:01 PM PDT 24 |
7808124120 ps |
| T1118 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prodend.3148994838 |
|
|
Mar 19 03:57:05 PM PDT 24 |
Mar 19 04:13:23 PM PDT 24 |
10773658675 ps |
| T1119 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2027834369 |
|
|
Mar 19 03:56:06 PM PDT 24 |
Mar 19 04:07:31 PM PDT 24 |
4457751640 ps |
| T1120 |
/workspace/coverage/default/3.chip_tap_straps_dev.3596427456 |
|
|
Mar 19 04:05:23 PM PDT 24 |
Mar 19 04:32:02 PM PDT 24 |
15631688533 ps |
| T1121 |
/workspace/coverage/default/0.chip_sw_hmac_enc_idle.4240613268 |
|
|
Mar 19 03:47:44 PM PDT 24 |
Mar 19 03:53:00 PM PDT 24 |
3429943450 ps |
| T794 |
/workspace/coverage/default/34.chip_sw_all_escalation_resets.1420457343 |
|
|
Mar 19 04:10:29 PM PDT 24 |
Mar 19 04:21:13 PM PDT 24 |
4795258304 ps |
| T1122 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter.1779350287 |
|
|
Mar 19 04:03:29 PM PDT 24 |
Mar 19 04:07:08 PM PDT 24 |
2811297018 ps |
| T1123 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq.296956036 |
|
|
Mar 19 03:50:10 PM PDT 24 |
Mar 19 04:49:43 PM PDT 24 |
17795843680 ps |
| T84 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.360921551 |
|
|
Mar 19 04:11:42 PM PDT 24 |
Mar 19 04:18:41 PM PDT 24 |
3128675716 ps |
| T111 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.120717095 |
|
|
Mar 19 03:58:08 PM PDT 24 |
Mar 19 04:06:52 PM PDT 24 |
3638855556 ps |
| T783 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.4143984489 |
|
|
Mar 19 04:08:17 PM PDT 24 |
Mar 19 04:14:46 PM PDT 24 |
3606190700 ps |
| T1124 |
/workspace/coverage/default/47.chip_sw_alert_handler_lpg_sleep_mode_alerts.2762696558 |
|
|
Mar 19 04:10:09 PM PDT 24 |
Mar 19 04:18:12 PM PDT 24 |
3861694840 ps |
| T1125 |
/workspace/coverage/default/2.chip_tap_straps_prod.1069246809 |
|
|
Mar 19 04:02:53 PM PDT 24 |
Mar 19 04:28:21 PM PDT 24 |
13056808354 ps |
| T758 |
/workspace/coverage/default/25.chip_sw_alert_handler_lpg_sleep_mode_alerts.2955847469 |
|
|
Mar 19 04:07:12 PM PDT 24 |
Mar 19 04:13:31 PM PDT 24 |
3867150596 ps |
| T1126 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_otp_hw_cfg0.4072751761 |
|
|
Mar 19 03:57:40 PM PDT 24 |
Mar 19 04:03:01 PM PDT 24 |
2627735352 ps |
| T773 |
/workspace/coverage/default/95.chip_sw_all_escalation_resets.612250661 |
|
|
Mar 19 04:14:08 PM PDT 24 |
Mar 19 04:29:11 PM PDT 24 |
5965881310 ps |
| T163 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_alert.3848658780 |
|
|
Mar 19 04:02:20 PM PDT 24 |
Mar 19 04:20:28 PM PDT 24 |
7198082318 ps |
| T345 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.1774863664 |
|
|
Mar 19 03:45:59 PM PDT 24 |
Mar 19 03:54:31 PM PDT 24 |
3266492090 ps |
| T737 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.3905642210 |
|
|
Mar 19 04:10:29 PM PDT 24 |
Mar 19 04:17:01 PM PDT 24 |
3826441972 ps |
| T1127 |
/workspace/coverage/default/0.chip_sw_sleep_sram_ret_contents_no_scramble.594380205 |
|
|
Mar 19 03:46:46 PM PDT 24 |
Mar 19 03:55:54 PM PDT 24 |
5356556312 ps |
| T236 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2618990229 |
|
|
Mar 19 04:07:26 PM PDT 24 |
Mar 19 04:18:05 PM PDT 24 |
5761908364 ps |
| T1128 |
/workspace/coverage/default/13.chip_sw_lc_ctrl_transition.1237654763 |
|
|
Mar 19 04:09:36 PM PDT 24 |
Mar 19 04:19:34 PM PDT 24 |
5652520141 ps |
| T340 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.10861513 |
|
|
Mar 19 04:06:09 PM PDT 24 |
Mar 19 04:18:21 PM PDT 24 |
6198502480 ps |
| T1129 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.1022842105 |
|
|
Mar 19 03:53:07 PM PDT 24 |
Mar 19 04:45:19 PM PDT 24 |
21233997509 ps |
| T1130 |
/workspace/coverage/default/0.chip_sw_aon_timer_smoketest.3486261768 |
|
|
Mar 19 03:46:48 PM PDT 24 |
Mar 19 03:53:12 PM PDT 24 |
3093203788 ps |
| T1131 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.192559417 |
|
|
Mar 19 03:56:30 PM PDT 24 |
Mar 19 04:16:13 PM PDT 24 |
14362480118 ps |
| T1132 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3672112690 |
|
|
Mar 19 03:46:41 PM PDT 24 |
Mar 19 03:50:07 PM PDT 24 |
2513242780 ps |
| T701 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_reset.2612806405 |
|
|
Mar 19 03:58:51 PM PDT 24 |
Mar 19 04:28:36 PM PDT 24 |
21870068342 ps |
| T1133 |
/workspace/coverage/default/1.chip_tap_straps_testunlock0.405909091 |
|
|
Mar 19 03:46:28 PM PDT 24 |
Mar 19 03:49:12 PM PDT 24 |
2644493337 ps |
| T1134 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_dev.1795893751 |
|
|
Mar 19 03:47:58 PM PDT 24 |
Mar 19 05:22:24 PM PDT 24 |
45552318422 ps |
| T1135 |
/workspace/coverage/default/0.chip_sw_aes_entropy.4050416487 |
|
|
Mar 19 03:49:28 PM PDT 24 |
Mar 19 03:53:41 PM PDT 24 |
2401762960 ps |
| T1136 |
/workspace/coverage/default/1.chip_sw_pwrmgr_usbdev_smoketest.649910067 |
|
|
Mar 19 03:52:24 PM PDT 24 |
Mar 19 03:59:06 PM PDT 24 |
5730969988 ps |
| T223 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.3227793390 |
|
|
Mar 19 04:08:24 PM PDT 24 |
Mar 19 04:17:37 PM PDT 24 |
5030614620 ps |
| T809 |
/workspace/coverage/default/94.chip_sw_all_escalation_resets.2104496743 |
|
|
Mar 19 04:13:46 PM PDT 24 |
Mar 19 04:23:52 PM PDT 24 |
5392332188 ps |
| T275 |
/workspace/coverage/default/86.chip_sw_all_escalation_resets.984846024 |
|
|
Mar 19 04:12:35 PM PDT 24 |
Mar 19 04:26:12 PM PDT 24 |
4847604060 ps |
| T1137 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.3993787519 |
|
|
Mar 19 04:03:42 PM PDT 24 |
Mar 19 05:20:52 PM PDT 24 |
24339423407 ps |
| T1138 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops.1074114539 |
|
|
Mar 19 03:47:12 PM PDT 24 |
Mar 19 03:56:19 PM PDT 24 |
3669938466 ps |
| T1139 |
/workspace/coverage/default/2.chip_sw_rstmgr_smoketest.3105552249 |
|
|
Mar 19 04:05:03 PM PDT 24 |
Mar 19 04:09:47 PM PDT 24 |
2752365096 ps |
| T747 |
/workspace/coverage/default/54.chip_sw_alert_handler_lpg_sleep_mode_alerts.416826754 |
|
|
Mar 19 04:14:49 PM PDT 24 |
Mar 19 04:22:35 PM PDT 24 |
4380277880 ps |
| T1140 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.2141437863 |
|
|
Mar 19 04:02:07 PM PDT 24 |
Mar 19 04:18:04 PM PDT 24 |
10983487513 ps |
| T1141 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.106066339 |
|
|
Mar 19 03:50:15 PM PDT 24 |
Mar 19 04:49:17 PM PDT 24 |
15864158570 ps |
| T1142 |
/workspace/coverage/default/2.chip_sw_kmac_app_rom.158870861 |
|
|
Mar 19 04:03:20 PM PDT 24 |
Mar 19 04:07:43 PM PDT 24 |
3073348858 ps |
| T1143 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2341217476 |
|
|
Mar 19 03:46:02 PM PDT 24 |
Mar 19 03:52:19 PM PDT 24 |
6758867530 ps |
| T1144 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.3298569490 |
|
|
Mar 19 04:00:03 PM PDT 24 |
Mar 19 04:22:24 PM PDT 24 |
7767036534 ps |
| T1145 |
/workspace/coverage/default/1.chip_sw_pwrmgr_wdog_reset.2946059391 |
|
|
Mar 19 03:50:12 PM PDT 24 |
Mar 19 04:01:29 PM PDT 24 |
5514027488 ps |
| T181 |
/workspace/coverage/default/2.chip_sw_rv_dm_ndm_reset_req_when_cpu_halted.824634172 |
|
|
Mar 19 04:03:54 PM PDT 24 |
Mar 19 04:11:52 PM PDT 24 |
3849389980 ps |
| T1146 |
/workspace/coverage/default/0.chip_sw_alert_handler_entropy.604237952 |
|
|
Mar 19 03:48:14 PM PDT 24 |
Mar 19 03:52:50 PM PDT 24 |
2923204830 ps |
| T1147 |
/workspace/coverage/default/1.chip_sw_aon_timer_sleep_wdog_sleep_pause.2735286678 |
|
|
Mar 19 03:50:43 PM PDT 24 |
Mar 19 03:57:49 PM PDT 24 |
7144215590 ps |
| T740 |
/workspace/coverage/default/25.chip_sw_all_escalation_resets.2716758976 |
|
|
Mar 19 04:09:31 PM PDT 24 |
Mar 19 04:20:15 PM PDT 24 |
4938304250 ps |
| T788 |
/workspace/coverage/default/5.chip_sw_alert_handler_lpg_sleep_mode_alerts.27243636 |
|
|
Mar 19 04:09:20 PM PDT 24 |
Mar 19 04:18:31 PM PDT 24 |
3614133548 ps |
| T50 |
/workspace/coverage/default/0.chip_sw_sleep_pin_wake.2415755706 |
|
|
Mar 19 03:49:08 PM PDT 24 |
Mar 19 03:59:22 PM PDT 24 |
5313043872 ps |
| T1148 |
/workspace/coverage/default/2.rom_keymgr_functest.965772392 |
|
|
Mar 19 04:04:43 PM PDT 24 |
Mar 19 04:11:43 PM PDT 24 |
3347589828 ps |
| T1149 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_idle_low_power.3362942718 |
|
|
Mar 19 03:49:37 PM PDT 24 |
Mar 19 03:56:56 PM PDT 24 |
2885874700 ps |
| T1150 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_transition.3737759243 |
|
|
Mar 19 03:45:06 PM PDT 24 |
Mar 19 04:02:57 PM PDT 24 |
11119570340 ps |
| T767 |
/workspace/coverage/default/12.chip_sw_alert_handler_lpg_sleep_mode_alerts.484412483 |
|
|
Mar 19 04:09:25 PM PDT 24 |
Mar 19 04:16:51 PM PDT 24 |
3289079000 ps |
| T1151 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.2162027830 |
|
|
Mar 19 03:47:30 PM PDT 24 |
Mar 19 03:57:09 PM PDT 24 |
4242344240 ps |
| T1152 |
/workspace/coverage/default/0.chip_sw_hmac_enc.2906313735 |
|
|
Mar 19 03:48:26 PM PDT 24 |
Mar 19 03:52:06 PM PDT 24 |
2761246140 ps |
| T734 |
/workspace/coverage/default/10.chip_sw_all_escalation_resets.1133829034 |
|
|
Mar 19 04:05:46 PM PDT 24 |
Mar 19 04:15:49 PM PDT 24 |
4753560834 ps |
| T284 |
/workspace/coverage/default/2.chip_sw_rstmgr_alert_info.2675944154 |
|
|
Mar 19 03:57:48 PM PDT 24 |
Mar 19 04:19:31 PM PDT 24 |
12129910702 ps |
| T310 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx.3228963066 |
|
|
Mar 19 03:47:03 PM PDT 24 |
Mar 19 04:02:49 PM PDT 24 |
5853143316 ps |
| T724 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.1301751206 |
|
|
Mar 19 04:12:59 PM PDT 24 |
Mar 19 04:24:30 PM PDT 24 |
5308067944 ps |
| T1153 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.869704237 |
|
|
Mar 19 03:57:40 PM PDT 24 |
Mar 19 05:33:01 PM PDT 24 |
45613001630 ps |
| T670 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.357624332 |
|
|
Mar 19 04:11:31 PM PDT 24 |
Mar 19 04:20:56 PM PDT 24 |
5593524624 ps |
| T795 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.2103650857 |
|
|
Mar 19 04:13:29 PM PDT 24 |
Mar 19 04:20:01 PM PDT 24 |
3874218604 ps |
| T712 |
/workspace/coverage/default/98.chip_sw_all_escalation_resets.17065291 |
|
|
Mar 19 04:15:04 PM PDT 24 |
Mar 19 04:24:50 PM PDT 24 |
4802095876 ps |
| T1154 |
/workspace/coverage/default/59.chip_sw_all_escalation_resets.56504443 |
|
|
Mar 19 04:10:38 PM PDT 24 |
Mar 19 04:23:02 PM PDT 24 |
4531194240 ps |
| T1155 |
/workspace/coverage/default/3.chip_tap_straps_prod.3829442165 |
|
|
Mar 19 04:05:39 PM PDT 24 |
Mar 19 04:24:16 PM PDT 24 |
11083987348 ps |
| T1156 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx3.1494272804 |
|
|
Mar 19 03:53:37 PM PDT 24 |
Mar 19 04:06:48 PM PDT 24 |
4817259098 ps |
| T170 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3676832628 |
|
|
Mar 19 04:01:56 PM PDT 24 |
Mar 19 04:06:00 PM PDT 24 |
2734957162 ps |
| T1157 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.1145144935 |
|
|
Mar 19 03:46:47 PM PDT 24 |
Mar 19 03:53:51 PM PDT 24 |
4793567876 ps |
| T1158 |
/workspace/coverage/default/9.chip_sw_all_escalation_resets.2720753956 |
|
|
Mar 19 04:07:27 PM PDT 24 |
Mar 19 04:22:38 PM PDT 24 |
5379990680 ps |
| T1159 |
/workspace/coverage/default/1.chip_sw_example_concurrency.1540008086 |
|
|
Mar 19 03:48:49 PM PDT 24 |
Mar 19 03:53:10 PM PDT 24 |
2851029960 ps |
| T762 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.2708843850 |
|
|
Mar 19 04:13:28 PM PDT 24 |
Mar 19 04:20:09 PM PDT 24 |
4243273060 ps |
| T1160 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_power_glitch_reset.1767745059 |
|
|
Mar 19 03:49:57 PM PDT 24 |
Mar 19 03:59:57 PM PDT 24 |
5113448806 ps |
| T1161 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.318056549 |
|
|
Mar 19 03:46:58 PM PDT 24 |
Mar 19 03:57:48 PM PDT 24 |
4217077748 ps |
| T1162 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_prod.3204309190 |
|
|
Mar 19 03:48:04 PM PDT 24 |
Mar 19 04:07:14 PM PDT 24 |
8435174488 ps |
| T1163 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.1350328988 |
|
|
Mar 19 04:08:51 PM PDT 24 |
Mar 19 04:17:10 PM PDT 24 |
5164177016 ps |
| T1164 |
/workspace/coverage/default/17.chip_sw_uart_rand_baudrate.3747934257 |
|
|
Mar 19 04:08:41 PM PDT 24 |
Mar 19 04:19:28 PM PDT 24 |
4912957535 ps |
| T1165 |
/workspace/coverage/default/2.chip_tap_straps_rma.2177280273 |
|
|
Mar 19 04:02:02 PM PDT 24 |
Mar 19 04:09:00 PM PDT 24 |
5043939003 ps |
| T1166 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.3593761547 |
|
|
Mar 19 04:02:13 PM PDT 24 |
Mar 19 04:33:24 PM PDT 24 |
8376974808 ps |
| T1167 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.1546532797 |
|
|
Mar 19 04:10:25 PM PDT 24 |
Mar 19 04:23:13 PM PDT 24 |
5181805496 ps |
| T1168 |
/workspace/coverage/default/15.chip_sw_alert_handler_lpg_sleep_mode_alerts.2896496048 |
|
|
Mar 19 04:08:49 PM PDT 24 |
Mar 19 04:15:00 PM PDT 24 |
3566003490 ps |
| T1169 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx.3976663059 |
|
|
Mar 19 04:05:27 PM PDT 24 |
Mar 19 04:19:12 PM PDT 24 |
5729169018 ps |
| T1170 |
/workspace/coverage/default/2.chip_sw_kmac_idle.1220140174 |
|
|
Mar 19 04:01:45 PM PDT 24 |
Mar 19 04:05:26 PM PDT 24 |
2381860324 ps |
| T686 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_disabled.3132651792 |
|
|
Mar 19 03:50:00 PM PDT 24 |
Mar 19 03:55:30 PM PDT 24 |
2767347856 ps |
| T1171 |
/workspace/coverage/default/2.chip_sw_pwrmgr_smoketest.1527122521 |
|
|
Mar 19 04:06:08 PM PDT 24 |
Mar 19 04:13:44 PM PDT 24 |
4673215590 ps |
| T730 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.674280362 |
|
|
Mar 19 04:09:57 PM PDT 24 |
Mar 19 04:19:36 PM PDT 24 |
4083850240 ps |
| T1172 |
/workspace/coverage/default/3.chip_tap_straps_testunlock0.687080852 |
|
|
Mar 19 04:05:22 PM PDT 24 |
Mar 19 04:07:51 PM PDT 24 |
3043598966 ps |
| T1173 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2813331958 |
|
|
Mar 19 04:07:20 PM PDT 24 |
Mar 19 04:13:02 PM PDT 24 |
4403916528 ps |
| T1174 |
/workspace/coverage/default/2.chip_sw_rv_timer_irq.1690150407 |
|
|
Mar 19 04:00:20 PM PDT 24 |
Mar 19 04:03:45 PM PDT 24 |
3009413580 ps |
| T320 |
/workspace/coverage/default/0.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.2456545295 |
|
|
Mar 19 03:47:41 PM PDT 24 |
Mar 19 03:57:15 PM PDT 24 |
19227941026 ps |
| T1175 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.498336995 |
|
|
Mar 19 03:47:30 PM PDT 24 |
Mar 19 04:16:00 PM PDT 24 |
9457149502 ps |