| T561 |
/workspace/coverage/default/0.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.2504526402 |
|
|
Mar 24 03:21:59 PM PDT 24 |
Mar 24 03:30:23 PM PDT 24 |
7029426660 ps |
| T562 |
/workspace/coverage/default/2.chip_sw_sleep_sram_ret_contents_no_scramble.790718002 |
|
|
Mar 24 03:44:55 PM PDT 24 |
Mar 24 03:56:01 PM PDT 24 |
8183291442 ps |
| T563 |
/workspace/coverage/default/2.chip_sw_uart_smoketest.3457723453 |
|
|
Mar 24 03:47:15 PM PDT 24 |
Mar 24 03:51:03 PM PDT 24 |
2567358280 ps |
| T223 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_dev.3696354056 |
|
|
Mar 24 03:29:39 PM PDT 24 |
Mar 24 04:46:50 PM PDT 24 |
51093708199 ps |
| T254 |
/workspace/coverage/default/37.chip_sw_all_escalation_resets.209240679 |
|
|
Mar 24 03:54:25 PM PDT 24 |
Mar 24 04:02:02 PM PDT 24 |
4471519080 ps |
| T321 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en.61992062 |
|
|
Mar 24 03:22:03 PM PDT 24 |
Mar 24 03:32:27 PM PDT 24 |
4691589445 ps |
| T564 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac_jitter_en.1491958916 |
|
|
Mar 24 03:33:38 PM PDT 24 |
Mar 24 03:37:43 PM PDT 24 |
2241818471 ps |
| T565 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_test_unlocked0.3609526504 |
|
|
Mar 24 03:40:43 PM PDT 24 |
Mar 24 03:49:14 PM PDT 24 |
4517589340 ps |
| T255 |
/workspace/coverage/default/40.chip_sw_all_escalation_resets.1120228145 |
|
|
Mar 24 03:52:36 PM PDT 24 |
Mar 24 04:00:21 PM PDT 24 |
4768675150 ps |
| T343 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx_idx3.2572520840 |
|
|
Mar 24 03:27:12 PM PDT 24 |
Mar 24 03:41:46 PM PDT 24 |
5506986321 ps |
| T242 |
/workspace/coverage/default/2.chip_sw_sysrst_ctrl_in_irq.607181365 |
|
|
Mar 24 03:41:35 PM PDT 24 |
Mar 24 03:51:48 PM PDT 24 |
3970082894 ps |
| T566 |
/workspace/coverage/default/2.chip_sw_clkmgr_sleep_frequency.1566984731 |
|
|
Mar 24 03:46:27 PM PDT 24 |
Mar 24 03:57:32 PM PDT 24 |
4496562804 ps |
| T164 |
/workspace/coverage/default/17.chip_sw_all_escalation_resets.4157104570 |
|
|
Mar 24 03:51:11 PM PDT 24 |
Mar 24 03:59:09 PM PDT 24 |
5784909350 ps |
| T382 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_lockstep_glitch.2913710822 |
|
|
Mar 24 03:47:01 PM PDT 24 |
Mar 24 03:50:23 PM PDT 24 |
2473484112 ps |
| T567 |
/workspace/coverage/default/0.rom_e2e_static_critical.3279814922 |
|
|
Mar 24 03:31:10 PM PDT 24 |
Mar 24 04:13:49 PM PDT 24 |
10261421256 ps |
| T397 |
/workspace/coverage/default/72.chip_sw_alert_handler_lpg_sleep_mode_alerts.1277978776 |
|
|
Mar 24 03:56:28 PM PDT 24 |
Mar 24 04:03:52 PM PDT 24 |
3773663984 ps |
| T324 |
/workspace/coverage/default/79.chip_sw_alert_handler_lpg_sleep_mode_alerts.2783276926 |
|
|
Mar 24 03:55:30 PM PDT 24 |
Mar 24 04:03:18 PM PDT 24 |
3337728028 ps |
| T568 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_prod.3002271166 |
|
|
Mar 24 03:20:21 PM PDT 24 |
Mar 24 03:40:51 PM PDT 24 |
7213762122 ps |
| T515 |
/workspace/coverage/default/88.chip_sw_alert_handler_lpg_sleep_mode_alerts.4002534396 |
|
|
Mar 24 03:56:17 PM PDT 24 |
Mar 24 04:02:51 PM PDT 24 |
3629994600 ps |
| T569 |
/workspace/coverage/default/4.chip_sw_lc_ctrl_transition.154534998 |
|
|
Mar 24 03:48:48 PM PDT 24 |
Mar 24 04:03:55 PM PDT 24 |
12708250819 ps |
| T432 |
/workspace/coverage/default/18.chip_sw_all_escalation_resets.3377729971 |
|
|
Mar 24 03:51:14 PM PDT 24 |
Mar 24 04:00:51 PM PDT 24 |
4116112148 ps |
| T139 |
/workspace/coverage/default/0.chip_sw_pwrmgr_full_aon_reset.3261157912 |
|
|
Mar 24 03:19:54 PM PDT 24 |
Mar 24 03:27:38 PM PDT 24 |
7267364840 ps |
| T570 |
/workspace/coverage/default/1.chip_sw_uart_tx_rx.33866871 |
|
|
Mar 24 03:27:52 PM PDT 24 |
Mar 24 03:44:23 PM PDT 24 |
5530089805 ps |
| T571 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_hmac_trans.41562980 |
|
|
Mar 24 03:22:20 PM PDT 24 |
Mar 24 03:31:09 PM PDT 24 |
5669246784 ps |
| T572 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_otp_hw_cfg0.926890904 |
|
|
Mar 24 03:29:01 PM PDT 24 |
Mar 24 03:34:49 PM PDT 24 |
3616421760 ps |
| T243 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_in_irq.779203321 |
|
|
Mar 24 03:25:59 PM PDT 24 |
Mar 24 03:36:25 PM PDT 24 |
4673525773 ps |
| T573 |
/workspace/coverage/default/1.chip_sw_clkmgr_sleep_frequency.2748001867 |
|
|
Mar 24 03:35:17 PM PDT 24 |
Mar 24 03:46:15 PM PDT 24 |
4703340982 ps |
| T350 |
/workspace/coverage/default/82.chip_sw_alert_handler_lpg_sleep_mode_alerts.755829238 |
|
|
Mar 24 04:02:08 PM PDT 24 |
Mar 24 04:07:23 PM PDT 24 |
4226699146 ps |
| T268 |
/workspace/coverage/default/2.chip_sw_edn_auto_mode.1235791725 |
|
|
Mar 24 03:46:54 PM PDT 24 |
Mar 24 04:08:09 PM PDT 24 |
6656317170 ps |
| T574 |
/workspace/coverage/default/0.chip_sw_flash_scrambling_smoketest.4216241537 |
|
|
Mar 24 03:27:54 PM PDT 24 |
Mar 24 03:31:45 PM PDT 24 |
3368080752 ps |
| T19 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ec_rst_l.254800649 |
|
|
Mar 24 03:21:02 PM PDT 24 |
Mar 24 04:17:01 PM PDT 24 |
20117371212 ps |
| T575 |
/workspace/coverage/default/14.chip_sw_lc_ctrl_transition.567520198 |
|
|
Mar 24 03:50:41 PM PDT 24 |
Mar 24 04:09:20 PM PDT 24 |
11730703875 ps |
| T267 |
/workspace/coverage/default/1.chip_sw_rv_timer_irq.829028681 |
|
|
Mar 24 03:32:57 PM PDT 24 |
Mar 24 03:36:42 PM PDT 24 |
3170106728 ps |
| T576 |
/workspace/coverage/default/60.chip_sw_alert_handler_lpg_sleep_mode_alerts.439895999 |
|
|
Mar 24 03:54:46 PM PDT 24 |
Mar 24 03:59:37 PM PDT 24 |
3311037570 ps |
| T169 |
/workspace/coverage/default/2.chip_sw_edn_boot_mode.3651242001 |
|
|
Mar 24 03:43:09 PM PDT 24 |
Mar 24 03:51:24 PM PDT 24 |
3435664040 ps |
| T11 |
/workspace/coverage/default/0.chip_sw_spi_device_pass_through_collision.14533228 |
|
|
Mar 24 03:20:33 PM PDT 24 |
Mar 24 03:32:23 PM PDT 24 |
4772712478 ps |
| T577 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_smoketest.3821988292 |
|
|
Mar 24 03:26:50 PM PDT 24 |
Mar 24 03:30:55 PM PDT 24 |
2986353644 ps |
| T317 |
/workspace/coverage/default/0.chip_sw_power_sleep_load.51897782 |
|
|
Mar 24 03:24:53 PM PDT 24 |
Mar 24 03:35:51 PM PDT 24 |
10413672660 ps |
| T578 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_reduced_freq.3567077552 |
|
|
Mar 24 03:26:13 PM PDT 24 |
Mar 24 03:28:45 PM PDT 24 |
1992109723 ps |
| T370 |
/workspace/coverage/default/21.chip_sw_all_escalation_resets.2480166511 |
|
|
Mar 24 03:51:51 PM PDT 24 |
Mar 24 04:01:22 PM PDT 24 |
4565693930 ps |
| T159 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_alert.3086489570 |
|
|
Mar 24 03:35:31 PM PDT 24 |
Mar 24 03:52:14 PM PDT 24 |
6891883500 ps |
| T211 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx.638225525 |
|
|
Mar 24 03:28:02 PM PDT 24 |
Mar 24 03:47:03 PM PDT 24 |
5867757750 ps |
| T579 |
/workspace/coverage/default/11.chip_sw_uart_rand_baudrate.775485675 |
|
|
Mar 24 03:50:38 PM PDT 24 |
Mar 24 04:20:22 PM PDT 24 |
13894814872 ps |
| T580 |
/workspace/coverage/default/0.chip_sw_kmac_idle.1966225834 |
|
|
Mar 24 03:21:32 PM PDT 24 |
Mar 24 03:26:55 PM PDT 24 |
2790650120 ps |
| T154 |
/workspace/coverage/default/0.chip_sw_sensor_ctrl_alert.4060158725 |
|
|
Mar 24 03:21:14 PM PDT 24 |
Mar 24 03:34:17 PM PDT 24 |
6102121012 ps |
| T581 |
/workspace/coverage/default/2.chip_sw_hmac_smoketest.598430188 |
|
|
Mar 24 03:47:22 PM PDT 24 |
Mar 24 03:53:53 PM PDT 24 |
2753449390 ps |
| T473 |
/workspace/coverage/default/32.chip_sw_alert_handler_lpg_sleep_mode_alerts.1784027897 |
|
|
Mar 24 03:51:45 PM PDT 24 |
Mar 24 03:58:09 PM PDT 24 |
3456013832 ps |
| T582 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_test_unlocked0.1665564760 |
|
|
Mar 24 03:29:50 PM PDT 24 |
Mar 24 03:57:26 PM PDT 24 |
7146079320 ps |
| T250 |
/workspace/coverage/default/2.chip_sw_gpio_smoketest.2202874896 |
|
|
Mar 24 03:47:47 PM PDT 24 |
Mar 24 03:51:47 PM PDT 24 |
2703238531 ps |
| T583 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq_low_speed.259488423 |
|
|
Mar 24 03:49:20 PM PDT 24 |
Mar 24 04:26:44 PM PDT 24 |
22731183235 ps |
| T439 |
/workspace/coverage/default/1.chip_sw_ast_clk_outputs.1587760212 |
|
|
Mar 24 03:35:00 PM PDT 24 |
Mar 24 03:56:36 PM PDT 24 |
7053937040 ps |
| T584 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_req.4066250534 |
|
|
Mar 24 03:20:44 PM PDT 24 |
Mar 24 03:26:54 PM PDT 24 |
3525826344 ps |
| T203 |
/workspace/coverage/default/0.chip_sw_flash_rma_unlocked.44611486 |
|
|
Mar 24 03:20:28 PM PDT 24 |
Mar 24 04:43:25 PM PDT 24 |
43840704559 ps |
| T585 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_mem_protection.3222953733 |
|
|
Mar 24 03:38:11 PM PDT 24 |
Mar 24 03:58:53 PM PDT 24 |
5274558240 ps |
| T117 |
/workspace/coverage/default/4.chip_tap_straps_testunlock0.2630629425 |
|
|
Mar 24 03:49:20 PM PDT 24 |
Mar 24 03:59:24 PM PDT 24 |
6422831752 ps |
| T586 |
/workspace/coverage/default/0.chip_sw_pwrmgr_main_power_glitch_reset.3208361814 |
|
|
Mar 24 03:20:27 PM PDT 24 |
Mar 24 03:27:03 PM PDT 24 |
3801477834 ps |
| T587 |
/workspace/coverage/default/1.chip_sw_entropy_src_kat_test.3268057111 |
|
|
Mar 24 03:35:07 PM PDT 24 |
Mar 24 03:40:01 PM PDT 24 |
3008533712 ps |
| T184 |
/workspace/coverage/default/2.chip_sw_alert_handler_reverse_ping_in_deep_sleep.2945949364 |
|
|
Mar 24 03:45:59 PM PDT 24 |
Mar 24 06:50:13 PM PDT 24 |
254485545360 ps |
| T416 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_volatile_raw_unlock.3161212311 |
|
|
Mar 24 03:29:30 PM PDT 24 |
Mar 24 03:31:31 PM PDT 24 |
2987749743 ps |
| T344 |
/workspace/coverage/default/2.rom_raw_unlock.4076314419 |
|
|
Mar 24 03:47:50 PM PDT 24 |
Mar 24 04:18:44 PM PDT 24 |
16438242639 ps |
| T222 |
/workspace/coverage/default/2.chip_sw_flash_init.3547893438 |
|
|
Mar 24 03:39:29 PM PDT 24 |
Mar 24 04:11:28 PM PDT 24 |
16984609350 ps |
| T588 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usb_clk_disabled_when_active.766989332 |
|
|
Mar 24 03:40:08 PM PDT 24 |
Mar 24 03:46:12 PM PDT 24 |
4707351894 ps |
| T589 |
/workspace/coverage/default/2.chip_sw_hmac_enc_jitter_en_reduced_freq.1858107758 |
|
|
Mar 24 03:48:56 PM PDT 24 |
Mar 24 03:53:43 PM PDT 24 |
3635635400 ps |
| T590 |
/workspace/coverage/default/1.rom_e2e_asm_init_prod_end.3900205277 |
|
|
Mar 24 03:41:00 PM PDT 24 |
Mar 24 04:13:39 PM PDT 24 |
9192006851 ps |
| T591 |
/workspace/coverage/default/0.chip_sw_entropy_src_ast_rng_req.780460500 |
|
|
Mar 24 03:20:55 PM PDT 24 |
Mar 24 03:26:04 PM PDT 24 |
2615009374 ps |
| T315 |
/workspace/coverage/default/80.chip_sw_all_escalation_resets.2549310185 |
|
|
Mar 24 03:55:20 PM PDT 24 |
Mar 24 04:04:03 PM PDT 24 |
5544797952 ps |
| T151 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en.4259359402 |
|
|
Mar 24 03:26:43 PM PDT 24 |
Mar 24 04:19:05 PM PDT 24 |
18495904512 ps |
| T398 |
/workspace/coverage/default/81.chip_sw_all_escalation_resets.3927807345 |
|
|
Mar 24 03:54:28 PM PDT 24 |
Mar 24 04:02:04 PM PDT 24 |
5150170920 ps |
| T288 |
/workspace/coverage/default/1.chip_sw_sram_ctrl_scrambled_access_jitter_en.2219810388 |
|
|
Mar 24 03:34:35 PM PDT 24 |
Mar 24 03:43:01 PM PDT 24 |
4391245455 ps |
| T364 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en.3684613437 |
|
|
Mar 24 03:19:42 PM PDT 24 |
Mar 24 03:30:32 PM PDT 24 |
4380237322 ps |
| T25 |
/workspace/coverage/default/0.chip_sw_gpio.1757833386 |
|
|
Mar 24 03:20:03 PM PDT 24 |
Mar 24 03:28:44 PM PDT 24 |
3812727899 ps |
| T56 |
/workspace/coverage/default/1.chip_sw_alert_handler_reverse_ping_in_deep_sleep.744258872 |
|
|
Mar 24 03:32:16 PM PDT 24 |
Mar 24 06:48:11 PM PDT 24 |
255277656230 ps |
| T248 |
/workspace/coverage/default/0.chip_sw_inject_scramble_seed.2530735689 |
|
|
Mar 24 03:21:00 PM PDT 24 |
Mar 24 06:30:14 PM PDT 24 |
64399790486 ps |
| T592 |
/workspace/coverage/default/2.chip_sw_csrng_fuse_en_sw_app_read_test.3122132792 |
|
|
Mar 24 03:43:15 PM PDT 24 |
Mar 24 03:51:19 PM PDT 24 |
4055406032 ps |
| T593 |
/workspace/coverage/default/4.chip_sw_uart_tx_rx_alt_clk_freq.1088244475 |
|
|
Mar 24 03:49:00 PM PDT 24 |
Mar 24 04:19:27 PM PDT 24 |
13351326052 ps |
| T594 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency.529412464 |
|
|
Mar 24 03:32:38 PM PDT 24 |
Mar 24 04:05:33 PM PDT 24 |
7926634070 ps |
| T595 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_lc.852093010 |
|
|
Mar 24 03:45:57 PM PDT 24 |
Mar 24 04:02:35 PM PDT 24 |
13225708711 ps |
| T412 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_ulp_z3_wakeup.4042586448 |
|
|
Mar 24 03:21:19 PM PDT 24 |
Mar 24 03:31:00 PM PDT 24 |
4790811680 ps |
| T506 |
/workspace/coverage/default/63.chip_sw_all_escalation_resets.1457364958 |
|
|
Mar 24 03:57:16 PM PDT 24 |
Mar 24 04:06:07 PM PDT 24 |
5053406048 ps |
| T225 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_rma.2597117385 |
|
|
Mar 24 03:30:33 PM PDT 24 |
Mar 24 05:02:25 PM PDT 24 |
45635133330 ps |
| T596 |
/workspace/coverage/default/2.chip_sw_aes_enc_jitter_en.1250096535 |
|
|
Mar 24 03:43:01 PM PDT 24 |
Mar 24 03:47:03 PM PDT 24 |
2564681309 ps |
| T232 |
/workspace/coverage/default/22.chip_sw_alert_handler_lpg_sleep_mode_alerts.1619791346 |
|
|
Mar 24 03:52:50 PM PDT 24 |
Mar 24 03:59:34 PM PDT 24 |
4091049190 ps |
| T340 |
/workspace/coverage/default/0.chip_sw_rstmgr_alert_info.2452841612 |
|
|
Mar 24 03:24:22 PM PDT 24 |
Mar 24 03:53:55 PM PDT 24 |
13518014584 ps |
| T597 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_hmac_trans.1106744970 |
|
|
Mar 24 03:38:42 PM PDT 24 |
Mar 24 03:48:56 PM PDT 24 |
5723114500 ps |
| T445 |
/workspace/coverage/default/10.chip_sw_alert_handler_lpg_sleep_mode_alerts.564156283 |
|
|
Mar 24 03:49:59 PM PDT 24 |
Mar 24 03:56:08 PM PDT 24 |
3871903562 ps |
| T444 |
/workspace/coverage/default/2.chip_sw_aes_masking_off.2663038787 |
|
|
Mar 24 03:43:22 PM PDT 24 |
Mar 24 03:47:51 PM PDT 24 |
2092416947 ps |
| T598 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.1986859343 |
|
|
Mar 24 03:22:44 PM PDT 24 |
Mar 24 03:28:30 PM PDT 24 |
3671782089 ps |
| T599 |
/workspace/coverage/default/2.chip_tap_straps_prod.918808215 |
|
|
Mar 24 03:45:01 PM PDT 24 |
Mar 24 03:47:18 PM PDT 24 |
2714852603 ps |
| T600 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.345127977 |
|
|
Mar 24 03:25:32 PM PDT 24 |
Mar 24 03:37:01 PM PDT 24 |
4283623596 ps |
| T8 |
/workspace/coverage/default/1.chip_sw_sleep_pin_mio_dio_val.470953587 |
|
|
Mar 24 03:29:25 PM PDT 24 |
Mar 24 03:35:33 PM PDT 24 |
2958303154 ps |
| T601 |
/workspace/coverage/default/0.rom_e2e_asm_init_rma.80477277 |
|
|
Mar 24 03:33:59 PM PDT 24 |
Mar 24 04:04:03 PM PDT 24 |
8482651190 ps |
| T360 |
/workspace/coverage/default/65.chip_sw_alert_handler_lpg_sleep_mode_alerts.2936172292 |
|
|
Mar 24 03:57:54 PM PDT 24 |
Mar 24 04:03:54 PM PDT 24 |
3636128572 ps |
| T374 |
/workspace/coverage/default/2.chip_sw_adc_ctrl_sleep_debug_cable_wakeup.1366402648 |
|
|
Mar 24 03:44:43 PM PDT 24 |
Mar 24 03:56:43 PM PDT 24 |
18732765778 ps |
| T602 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_dev.3601545484 |
|
|
Mar 24 03:30:50 PM PDT 24 |
Mar 24 04:01:49 PM PDT 24 |
9026798796 ps |
| T603 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_reduced_freq.3630245063 |
|
|
Mar 24 03:45:02 PM PDT 24 |
Mar 24 03:49:09 PM PDT 24 |
2886183161 ps |
| T604 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.2160502421 |
|
|
Mar 24 03:38:27 PM PDT 24 |
Mar 24 03:52:53 PM PDT 24 |
5186826464 ps |
| T605 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_power_glitch_reset.1364842538 |
|
|
Mar 24 03:40:16 PM PDT 24 |
Mar 24 03:45:42 PM PDT 24 |
6629378356 ps |
| T606 |
/workspace/coverage/default/2.chip_sw_hmac_enc_idle.719134503 |
|
|
Mar 24 03:43:52 PM PDT 24 |
Mar 24 03:49:38 PM PDT 24 |
3078691400 ps |
| T415 |
/workspace/coverage/default/1.chip_tap_straps_dev.1492762117 |
|
|
Mar 24 03:36:54 PM PDT 24 |
Mar 24 04:00:24 PM PDT 24 |
13469149582 ps |
| T200 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_icache_invalidate.144329222 |
|
|
Mar 24 03:36:48 PM PDT 24 |
Mar 24 03:40:43 PM PDT 24 |
3179433074 ps |
| T481 |
/workspace/coverage/default/17.chip_sw_alert_handler_lpg_sleep_mode_alerts.2128689384 |
|
|
Mar 24 03:52:06 PM PDT 24 |
Mar 24 03:59:05 PM PDT 24 |
3301124580 ps |
| T607 |
/workspace/coverage/default/2.chip_sw_otbn_randomness.1518332095 |
|
|
Mar 24 03:42:15 PM PDT 24 |
Mar 24 03:55:46 PM PDT 24 |
6280333032 ps |
| T608 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_test_unlocked0.3824181702 |
|
|
Mar 24 03:30:31 PM PDT 24 |
Mar 24 04:00:49 PM PDT 24 |
6430849752 ps |
| T469 |
/workspace/coverage/default/85.chip_sw_all_escalation_resets.585412894 |
|
|
Mar 24 03:56:40 PM PDT 24 |
Mar 24 04:04:11 PM PDT 24 |
5461594224 ps |
| T158 |
/workspace/coverage/default/3.chip_sw_sensor_ctrl_alert.1557549506 |
|
|
Mar 24 03:50:04 PM PDT 24 |
Mar 24 03:56:46 PM PDT 24 |
4280417336 ps |
| T462 |
/workspace/coverage/default/15.chip_sw_all_escalation_resets.4043475053 |
|
|
Mar 24 03:50:24 PM PDT 24 |
Mar 24 04:00:02 PM PDT 24 |
4727300536 ps |
| T333 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs_jitter.3529112431 |
|
|
Mar 24 03:32:58 PM PDT 24 |
Mar 24 03:46:49 PM PDT 24 |
4808664334 ps |
| T609 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_prodend.201858494 |
|
|
Mar 24 03:24:55 PM PDT 24 |
Mar 24 03:43:34 PM PDT 24 |
7806511620 ps |
| T610 |
/workspace/coverage/default/7.chip_sw_uart_rand_baudrate.3254916715 |
|
|
Mar 24 03:48:45 PM PDT 24 |
Mar 24 04:21:02 PM PDT 24 |
12737962083 ps |
| T430 |
/workspace/coverage/default/80.chip_sw_alert_handler_lpg_sleep_mode_alerts.230246362 |
|
|
Mar 24 03:55:38 PM PDT 24 |
Mar 24 04:02:27 PM PDT 24 |
4045463166 ps |
| T611 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.58896555 |
|
|
Mar 24 03:20:27 PM PDT 24 |
Mar 24 03:29:22 PM PDT 24 |
4987774736 ps |
| T612 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_idle_low_power.1656243233 |
|
|
Mar 24 03:39:44 PM PDT 24 |
Mar 24 03:45:26 PM PDT 24 |
3716063928 ps |
| T613 |
/workspace/coverage/default/2.chip_sw_clkmgr_smoketest.3051979734 |
|
|
Mar 24 03:47:52 PM PDT 24 |
Mar 24 03:53:10 PM PDT 24 |
2438876760 ps |
| T614 |
/workspace/coverage/default/2.chip_sw_example_flash.1453275741 |
|
|
Mar 24 03:38:33 PM PDT 24 |
Mar 24 03:41:49 PM PDT 24 |
2804985340 ps |
| T615 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_access_jitter_en.1437163315 |
|
|
Mar 24 03:42:38 PM PDT 24 |
Mar 24 04:02:11 PM PDT 24 |
6345577204 ps |
| T616 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_test_unlocked0.2640024237 |
|
|
Mar 24 03:19:52 PM PDT 24 |
Mar 24 03:29:50 PM PDT 24 |
4143961966 ps |
| T617 |
/workspace/coverage/default/1.chip_sw_uart_smoketest_signed.2469762814 |
|
|
Mar 24 03:42:43 PM PDT 24 |
Mar 24 04:12:34 PM PDT 24 |
8925968868 ps |
| T618 |
/workspace/coverage/default/2.rom_e2e_asm_init_rma.1976080251 |
|
|
Mar 24 03:51:47 PM PDT 24 |
Mar 24 04:21:42 PM PDT 24 |
9291890785 ps |
| T619 |
/workspace/coverage/default/2.chip_sw_kmac_smoketest.4094039225 |
|
|
Mar 24 03:47:15 PM PDT 24 |
Mar 24 03:53:35 PM PDT 24 |
3440642544 ps |
| T620 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_fast_rma.884877326 |
|
|
Mar 24 03:44:44 PM PDT 24 |
Mar 24 03:55:13 PM PDT 24 |
3928123184 ps |
| T289 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access_jitter_en_reduced_freq.2166838140 |
|
|
Mar 24 03:46:47 PM PDT 24 |
Mar 24 03:55:19 PM PDT 24 |
4095101305 ps |
| T621 |
/workspace/coverage/default/0.chip_sw_aes_idle.4153123520 |
|
|
Mar 24 03:21:22 PM PDT 24 |
Mar 24 03:25:05 PM PDT 24 |
2537946150 ps |
| T446 |
/workspace/coverage/default/61.chip_sw_all_escalation_resets.4067779976 |
|
|
Mar 24 03:54:35 PM PDT 24 |
Mar 24 04:03:46 PM PDT 24 |
6150245168 ps |
| T123 |
/workspace/coverage/default/0.chip_sw_usbdev_pullup.119243437 |
|
|
Mar 24 03:19:38 PM PDT 24 |
Mar 24 03:24:08 PM PDT 24 |
3245649532 ps |
| T622 |
/workspace/coverage/default/2.chip_sw_pwrmgr_random_sleep_all_reset_reqs.658515640 |
|
|
Mar 24 03:41:03 PM PDT 24 |
Mar 24 04:10:26 PM PDT 24 |
24994167781 ps |
| T224 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_prod.2948647524 |
|
|
Mar 24 03:41:52 PM PDT 24 |
Mar 24 05:17:45 PM PDT 24 |
49257838410 ps |
| T623 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod_end.202374110 |
|
|
Mar 24 03:28:35 PM PDT 24 |
Mar 24 03:59:29 PM PDT 24 |
8306061256 ps |
| T624 |
/workspace/coverage/default/0.chip_sw_rv_timer_irq.1462597197 |
|
|
Mar 24 03:24:17 PM PDT 24 |
Mar 24 03:28:11 PM PDT 24 |
2363214120 ps |
| T625 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_lc_signals_rma.4050842682 |
|
|
Mar 24 03:21:12 PM PDT 24 |
Mar 24 03:39:58 PM PDT 24 |
8260240080 ps |
| T447 |
/workspace/coverage/default/90.chip_sw_all_escalation_resets.2664604194 |
|
|
Mar 24 03:58:01 PM PDT 24 |
Mar 24 04:08:14 PM PDT 24 |
6164274696 ps |
| T626 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq.3937628822 |
|
|
Mar 24 03:42:02 PM PDT 24 |
Mar 24 04:37:32 PM PDT 24 |
17138992600 ps |
| T627 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_smoketest.2485269902 |
|
|
Mar 24 03:47:22 PM PDT 24 |
Mar 24 03:51:04 PM PDT 24 |
3003594778 ps |
| T441 |
/workspace/coverage/default/46.chip_sw_alert_handler_lpg_sleep_mode_alerts.543322551 |
|
|
Mar 24 03:52:19 PM PDT 24 |
Mar 24 03:58:33 PM PDT 24 |
3933113396 ps |
| T448 |
/workspace/coverage/default/86.chip_sw_alert_handler_lpg_sleep_mode_alerts.1526809033 |
|
|
Mar 24 03:55:29 PM PDT 24 |
Mar 24 04:03:05 PM PDT 24 |
3969192130 ps |
| T628 |
/workspace/coverage/default/1.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.2715231554 |
|
|
Mar 24 03:31:36 PM PDT 24 |
Mar 24 03:54:57 PM PDT 24 |
15623145556 ps |
| T435 |
/workspace/coverage/default/13.chip_sw_all_escalation_resets.3458625853 |
|
|
Mar 24 03:50:42 PM PDT 24 |
Mar 24 03:59:27 PM PDT 24 |
6044062038 ps |
| T629 |
/workspace/coverage/default/0.chip_sw_clkmgr_jitter_frequency.3184617079 |
|
|
Mar 24 03:21:22 PM PDT 24 |
Mar 24 03:27:46 PM PDT 24 |
3313193288 ps |
| T519 |
/workspace/coverage/default/46.chip_sw_all_escalation_resets.1072297290 |
|
|
Mar 24 03:53:04 PM PDT 24 |
Mar 24 04:05:12 PM PDT 24 |
6447513804 ps |
| T504 |
/workspace/coverage/default/4.chip_sw_all_escalation_resets.2356610270 |
|
|
Mar 24 03:49:38 PM PDT 24 |
Mar 24 03:57:50 PM PDT 24 |
4546523496 ps |
| T498 |
/workspace/coverage/default/30.chip_sw_alert_handler_lpg_sleep_mode_alerts.564572310 |
|
|
Mar 24 03:52:43 PM PDT 24 |
Mar 24 03:58:56 PM PDT 24 |
3481711762 ps |
| T630 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.342399728 |
|
|
Mar 24 03:20:19 PM PDT 24 |
Mar 24 03:30:23 PM PDT 24 |
3708844950 ps |
| T631 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_dev.281777777 |
|
|
Mar 24 03:30:19 PM PDT 24 |
Mar 24 04:26:35 PM PDT 24 |
11420311141 ps |
| T257 |
/workspace/coverage/default/14.chip_sw_alert_handler_lpg_sleep_mode_alerts.4239137083 |
|
|
Mar 24 03:51:27 PM PDT 24 |
Mar 24 04:00:22 PM PDT 24 |
3828872722 ps |
| T165 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_sleep_mode_pings.3886044855 |
|
|
Mar 24 03:46:22 PM PDT 24 |
Mar 24 04:06:56 PM PDT 24 |
12765073556 ps |
| T303 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en.2148978288 |
|
|
Mar 24 03:43:05 PM PDT 24 |
Mar 24 03:50:36 PM PDT 24 |
2773198399 ps |
| T81 |
/workspace/coverage/default/1.chip_sw_kmac_app_rom.1089634549 |
|
|
Mar 24 03:33:47 PM PDT 24 |
Mar 24 03:38:28 PM PDT 24 |
2665739400 ps |
| T304 |
/workspace/coverage/default/1.rom_keymgr_functest.3274345572 |
|
|
Mar 24 03:39:07 PM PDT 24 |
Mar 24 03:48:14 PM PDT 24 |
4123169374 ps |
| T305 |
/workspace/coverage/default/0.chip_sw_sleep_pwm_pulses.3653192035 |
|
|
Mar 24 03:23:15 PM PDT 24 |
Mar 24 03:45:22 PM PDT 24 |
8288527300 ps |
| T306 |
/workspace/coverage/default/1.chip_sw_kmac_idle.1669619087 |
|
|
Mar 24 03:33:58 PM PDT 24 |
Mar 24 03:37:56 PM PDT 24 |
2626563898 ps |
| T307 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops.180549778 |
|
|
Mar 24 03:25:33 PM PDT 24 |
Mar 24 03:38:11 PM PDT 24 |
3946387104 ps |
| T308 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_smoketest.3818371381 |
|
|
Mar 24 03:47:27 PM PDT 24 |
Mar 24 03:50:50 PM PDT 24 |
2829907870 ps |
| T309 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock_ext_clk_48mhz.2131520649 |
|
|
Mar 24 03:20:22 PM PDT 24 |
Mar 24 03:22:12 PM PDT 24 |
2124587149 ps |
| T632 |
/workspace/coverage/default/1.chip_sw_uart_rand_baudrate.1436826647 |
|
|
Mar 24 03:28:00 PM PDT 24 |
Mar 24 04:07:14 PM PDT 24 |
14064665407 ps |
| T89 |
/workspace/coverage/default/2.chip_plic_all_irqs_10.337948571 |
|
|
Mar 24 03:44:09 PM PDT 24 |
Mar 24 03:55:11 PM PDT 24 |
4492967702 ps |
| T140 |
/workspace/coverage/default/2.chip_sw_sensor_ctrl_status.3967649145 |
|
|
Mar 24 03:44:23 PM PDT 24 |
Mar 24 03:48:43 PM PDT 24 |
2485536031 ps |
| T633 |
/workspace/coverage/default/1.chip_sw_aes_enc_jitter_en_reduced_freq.539849343 |
|
|
Mar 24 03:37:45 PM PDT 24 |
Mar 24 03:41:44 PM PDT 24 |
3005838694 ps |
| T634 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_reset_toggle.88878994 |
|
|
Mar 24 03:23:50 PM PDT 24 |
Mar 24 03:48:26 PM PDT 24 |
6414547070 ps |
| T216 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx2.289486592 |
|
|
Mar 24 03:27:39 PM PDT 24 |
Mar 24 03:40:27 PM PDT 24 |
4421845940 ps |
| T20 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_ec_rst_l.377903164 |
|
|
Mar 24 03:31:00 PM PDT 24 |
Mar 24 04:28:15 PM PDT 24 |
20872961661 ps |
| T635 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_rma.2771190107 |
|
|
Mar 24 03:20:21 PM PDT 24 |
Mar 24 04:58:11 PM PDT 24 |
45781044228 ps |
| T175 |
/workspace/coverage/default/1.chip_plic_all_irqs_20.2806547947 |
|
|
Mar 24 03:35:55 PM PDT 24 |
Mar 24 03:49:20 PM PDT 24 |
5008143100 ps |
| T113 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_execution_main.1322576153 |
|
|
Mar 24 03:44:25 PM PDT 24 |
Mar 24 04:00:13 PM PDT 24 |
10186046090 ps |
| T636 |
/workspace/coverage/default/1.chip_sw_aes_enc.102067192 |
|
|
Mar 24 03:33:16 PM PDT 24 |
Mar 24 03:37:35 PM PDT 24 |
2398910046 ps |
| T637 |
/workspace/coverage/default/1.chip_sw_kmac_mode_kmac.1674924706 |
|
|
Mar 24 03:36:12 PM PDT 24 |
Mar 24 03:41:10 PM PDT 24 |
2465569716 ps |
| T322 |
/workspace/coverage/default/2.chip_sw_alert_handler_escalation.2420247237 |
|
|
Mar 24 03:43:03 PM PDT 24 |
Mar 24 03:51:25 PM PDT 24 |
3955080064 ps |
| T389 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2296026290 |
|
|
Mar 24 03:22:59 PM PDT 24 |
Mar 24 04:21:15 PM PDT 24 |
24061377450 ps |
| T433 |
/workspace/coverage/default/35.chip_sw_alert_handler_lpg_sleep_mode_alerts.2278611887 |
|
|
Mar 24 03:51:13 PM PDT 24 |
Mar 24 03:58:02 PM PDT 24 |
3318324428 ps |
| T638 |
/workspace/coverage/default/1.rom_e2e_static_critical.1643878735 |
|
|
Mar 24 03:40:28 PM PDT 24 |
Mar 24 04:16:58 PM PDT 24 |
10850266060 ps |
| T639 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx1.2440717704 |
|
|
Mar 24 03:38:08 PM PDT 24 |
Mar 24 03:53:30 PM PDT 24 |
5756504387 ps |
| T640 |
/workspace/coverage/default/2.rom_e2e_static_critical.1650764168 |
|
|
Mar 24 03:52:40 PM PDT 24 |
Mar 24 04:29:11 PM PDT 24 |
10979632900 ps |
| T323 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en.2663522336 |
|
|
Mar 24 03:32:45 PM PDT 24 |
Mar 24 03:42:25 PM PDT 24 |
5484060176 ps |
| T641 |
/workspace/coverage/default/2.chip_sw_aes_entropy.46850416 |
|
|
Mar 24 03:47:15 PM PDT 24 |
Mar 24 03:52:38 PM PDT 24 |
2884309122 ps |
| T330 |
/workspace/coverage/default/69.chip_sw_all_escalation_resets.2333551830 |
|
|
Mar 24 03:54:30 PM PDT 24 |
Mar 24 04:03:52 PM PDT 24 |
4540870934 ps |
| T167 |
/workspace/coverage/default/1.chip_plic_all_irqs_10.547159296 |
|
|
Mar 24 03:34:54 PM PDT 24 |
Mar 24 03:46:48 PM PDT 24 |
4136475744 ps |
| T475 |
/workspace/coverage/default/58.chip_sw_alert_handler_lpg_sleep_mode_alerts.1644380853 |
|
|
Mar 24 03:54:25 PM PDT 24 |
Mar 24 04:00:44 PM PDT 24 |
3379467828 ps |
| T345 |
/workspace/coverage/default/0.rom_raw_unlock.243777712 |
|
|
Mar 24 03:26:41 PM PDT 24 |
Mar 24 04:00:01 PM PDT 24 |
15997748962 ps |
| T642 |
/workspace/coverage/default/1.chip_sw_entropy_src_ast_rng_req.888903554 |
|
|
Mar 24 03:35:23 PM PDT 24 |
Mar 24 03:41:09 PM PDT 24 |
3168325718 ps |
| T325 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_kmac.3372253705 |
|
|
Mar 24 03:34:04 PM PDT 24 |
Mar 24 03:41:15 PM PDT 24 |
4747429928 ps |
| T386 |
/workspace/coverage/default/1.chip_sw_kmac_entropy.1082745374 |
|
|
Mar 24 03:28:21 PM PDT 24 |
Mar 24 03:32:34 PM PDT 24 |
2933321774 ps |
| T643 |
/workspace/coverage/default/6.chip_sw_uart_rand_baudrate.3016936737 |
|
|
Mar 24 03:49:30 PM PDT 24 |
Mar 24 04:01:31 PM PDT 24 |
5087053033 ps |
| T644 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_kmac_trans.3150510090 |
|
|
Mar 24 03:33:47 PM PDT 24 |
Mar 24 03:42:50 PM PDT 24 |
5309114730 ps |
| T354 |
/workspace/coverage/default/2.chip_sw_pattgen_ios.808882681 |
|
|
Mar 24 03:38:31 PM PDT 24 |
Mar 24 03:42:29 PM PDT 24 |
3128018620 ps |
| T645 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_lc_escalate.3893215764 |
|
|
Mar 24 03:32:40 PM PDT 24 |
Mar 24 03:42:23 PM PDT 24 |
5334673230 ps |
| T646 |
/workspace/coverage/default/0.chip_sw_aes_enc.3327973422 |
|
|
Mar 24 03:19:04 PM PDT 24 |
Mar 24 03:23:42 PM PDT 24 |
2605990450 ps |
| T647 |
/workspace/coverage/default/2.chip_sw_pwrmgr_b2b_sleep_reset_req.919288378 |
|
|
Mar 24 03:45:03 PM PDT 24 |
Mar 24 04:19:02 PM PDT 24 |
23219619288 ps |
| T648 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_rma.1477270387 |
|
|
Mar 24 03:29:09 PM PDT 24 |
Mar 24 03:55:37 PM PDT 24 |
8089889626 ps |
| T201 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_icache_invalidate.258562563 |
|
|
Mar 24 03:23:58 PM PDT 24 |
Mar 24 03:28:33 PM PDT 24 |
2555910404 ps |
| T649 |
/workspace/coverage/default/2.chip_sw_rv_plic_smoketest.3762085284 |
|
|
Mar 24 03:48:27 PM PDT 24 |
Mar 24 03:53:23 PM PDT 24 |
2690390080 ps |
| T650 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_power_glitch_reset.3729349850 |
|
|
Mar 24 03:40:12 PM PDT 24 |
Mar 24 03:48:35 PM PDT 24 |
3987926614 ps |
| T422 |
/workspace/coverage/default/88.chip_sw_all_escalation_resets.2377672740 |
|
|
Mar 24 03:56:13 PM PDT 24 |
Mar 24 04:06:04 PM PDT 24 |
5585818628 ps |
| T651 |
/workspace/coverage/default/1.chip_sw_pwrmgr_random_sleep_all_reset_reqs.2491758232 |
|
|
Mar 24 03:30:38 PM PDT 24 |
Mar 24 04:15:44 PM PDT 24 |
19846853268 ps |
| T652 |
/workspace/coverage/default/2.chip_sw_flash_init_reduced_freq.3325689402 |
|
|
Mar 24 03:45:31 PM PDT 24 |
Mar 24 04:14:32 PM PDT 24 |
23677937291 ps |
| T434 |
/workspace/coverage/default/24.chip_sw_all_escalation_resets.3232562571 |
|
|
Mar 24 03:50:35 PM PDT 24 |
Mar 24 04:01:40 PM PDT 24 |
5768047998 ps |
| T76 |
/workspace/coverage/default/2.chip_sw_alert_test.3816684808 |
|
|
Mar 24 03:41:04 PM PDT 24 |
Mar 24 03:47:37 PM PDT 24 |
3105987464 ps |
| T455 |
/workspace/coverage/default/41.chip_sw_all_escalation_resets.2039914591 |
|
|
Mar 24 03:53:20 PM PDT 24 |
Mar 24 04:04:00 PM PDT 24 |
5440303000 ps |
| T653 |
/workspace/coverage/default/1.chip_sw_edn_sw_mode.2823403414 |
|
|
Mar 24 03:34:37 PM PDT 24 |
Mar 24 03:57:07 PM PDT 24 |
6785417060 ps |
| T654 |
/workspace/coverage/default/1.chip_sw_inject_scramble_seed.1459949697 |
|
|
Mar 24 03:26:44 PM PDT 24 |
Mar 24 06:25:31 PM PDT 24 |
64130366120 ps |
| T655 |
/workspace/coverage/default/1.chip_sw_csrng_smoketest.3654822243 |
|
|
Mar 24 03:38:50 PM PDT 24 |
Mar 24 03:42:44 PM PDT 24 |
2377700200 ps |
| T656 |
/workspace/coverage/default/1.chip_sw_aes_entropy.3732714196 |
|
|
Mar 24 03:33:09 PM PDT 24 |
Mar 24 03:37:25 PM PDT 24 |
2161102614 ps |
| T657 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_dev.2322132790 |
|
|
Mar 24 03:39:04 PM PDT 24 |
Mar 24 03:52:20 PM PDT 24 |
4264751336 ps |
| T197 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_test_locked0_to_scrap.1492945823 |
|
|
Mar 24 03:23:22 PM PDT 24 |
Mar 24 03:25:44 PM PDT 24 |
3072217495 ps |
| T658 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_test_unlocked0.3115371350 |
|
|
Mar 24 03:30:41 PM PDT 24 |
Mar 24 03:57:58 PM PDT 24 |
6806847576 ps |
| T659 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.4197081922 |
|
|
Mar 24 03:45:54 PM PDT 24 |
Mar 24 04:00:17 PM PDT 24 |
4789772922 ps |
| T660 |
/workspace/coverage/default/1.chip_sw_aon_timer_smoketest.1292744299 |
|
|
Mar 24 03:38:05 PM PDT 24 |
Mar 24 03:42:41 PM PDT 24 |
2411409764 ps |
| T290 |
/workspace/coverage/default/2.chip_sw_sram_ctrl_scrambled_access.4125763673 |
|
|
Mar 24 03:44:27 PM PDT 24 |
Mar 24 03:54:43 PM PDT 24 |
4251433896 ps |
| T661 |
/workspace/coverage/default/0.chip_sw_example_manufacturer.1591774544 |
|
|
Mar 24 03:19:45 PM PDT 24 |
Mar 24 03:23:29 PM PDT 24 |
2787251812 ps |
| T662 |
/workspace/coverage/default/0.chip_sw_coremark.1738742199 |
|
|
Mar 24 03:19:52 PM PDT 24 |
Mar 24 06:10:32 PM PDT 24 |
51178589256 ps |
| T663 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.967990546 |
|
|
Mar 24 03:35:41 PM PDT 24 |
Mar 24 03:49:25 PM PDT 24 |
5174002152 ps |
| T664 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_bite_reset.4153200898 |
|
|
Mar 24 03:42:18 PM PDT 24 |
Mar 24 03:56:41 PM PDT 24 |
9615810282 ps |
| T291 |
/workspace/coverage/default/1.chip_sw_otbn_mem_scramble.964052095 |
|
|
Mar 24 03:33:42 PM PDT 24 |
Mar 24 03:42:44 PM PDT 24 |
2934206732 ps |
| T326 |
/workspace/coverage/default/1.chip_sw_keymgr_sideload_otbn.2707327372 |
|
|
Mar 24 03:34:36 PM PDT 24 |
Mar 24 04:34:05 PM PDT 24 |
10957818994 ps |
| T665 |
/workspace/coverage/default/2.chip_sw_csrng_kat_test.741895657 |
|
|
Mar 24 03:42:08 PM PDT 24 |
Mar 24 03:47:47 PM PDT 24 |
2912142676 ps |
| T666 |
/workspace/coverage/default/4.chip_sw_aon_timer_sleep_wdog_sleep_pause.1018959935 |
|
|
Mar 24 03:51:31 PM PDT 24 |
Mar 24 03:57:27 PM PDT 24 |
7742973150 ps |
| T667 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_dev.355306456 |
|
|
Mar 24 03:28:17 PM PDT 24 |
Mar 24 04:01:43 PM PDT 24 |
8602624852 ps |
| T668 |
/workspace/coverage/default/2.chip_sw_pwrmgr_normal_sleep_por_reset.1447748295 |
|
|
Mar 24 03:41:27 PM PDT 24 |
Mar 24 03:56:23 PM PDT 24 |
5687331564 ps |
| T669 |
/workspace/coverage/default/1.rom_raw_unlock.584397233 |
|
|
Mar 24 03:39:10 PM PDT 24 |
Mar 24 04:15:03 PM PDT 24 |
14419512720 ps |
| T118 |
/workspace/coverage/default/2.chip_tap_straps_testunlock0.3771241453 |
|
|
Mar 24 03:46:54 PM PDT 24 |
Mar 24 03:50:48 PM PDT 24 |
3257757173 ps |
| T262 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_dev.4223769764 |
|
|
Mar 24 03:31:04 PM PDT 24 |
Mar 24 04:19:39 PM PDT 24 |
12008442580 ps |
| T670 |
/workspace/coverage/default/2.rom_e2e_shutdown_exception_c.4263178199 |
|
|
Mar 24 03:51:18 PM PDT 24 |
Mar 24 04:19:01 PM PDT 24 |
8317579989 ps |
| T671 |
/workspace/coverage/default/0.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.3720915285 |
|
|
Mar 24 03:23:41 PM PDT 24 |
Mar 24 03:30:16 PM PDT 24 |
4372546082 ps |
| T672 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_nothing_prod.3012812300 |
|
|
Mar 24 03:28:19 PM PDT 24 |
Mar 24 04:00:04 PM PDT 24 |
8371048214 ps |
| T673 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_test_unlocked0.2609685960 |
|
|
Mar 24 03:45:40 PM PDT 24 |
Mar 24 03:55:43 PM PDT 24 |
4063639100 ps |
| T502 |
/workspace/coverage/default/48.chip_sw_all_escalation_resets.844769526 |
|
|
Mar 24 03:53:00 PM PDT 24 |
Mar 24 04:01:39 PM PDT 24 |
5272554608 ps |
| T135 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_wake_ups.4265118410 |
|
|
Mar 24 03:25:27 PM PDT 24 |
Mar 24 03:33:42 PM PDT 24 |
7646742612 ps |
| T357 |
/workspace/coverage/default/0.chip_sw_sysrst_ctrl_reset.1108288569 |
|
|
Mar 24 03:20:14 PM PDT 24 |
Mar 24 03:52:05 PM PDT 24 |
20990281616 ps |
| T674 |
/workspace/coverage/default/11.chip_sw_lc_ctrl_transition.1857173670 |
|
|
Mar 24 03:50:39 PM PDT 24 |
Mar 24 03:58:44 PM PDT 24 |
5423637456 ps |
| T269 |
/workspace/coverage/default/0.chip_sw_rstmgr_cpu_info.1803192589 |
|
|
Mar 24 03:21:08 PM PDT 24 |
Mar 24 03:31:28 PM PDT 24 |
5230850184 ps |
| T12 |
/workspace/coverage/default/2.chip_sw_spi_host_tx_rx.132934956 |
|
|
Mar 24 03:39:18 PM PDT 24 |
Mar 24 03:44:37 PM PDT 24 |
2840928446 ps |
| T675 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_alt_clk_freq.2768935571 |
|
|
Mar 24 03:38:21 PM PDT 24 |
Mar 24 04:35:00 PM PDT 24 |
22946522973 ps |
| T421 |
/workspace/coverage/default/0.chip_sw_all_escalation_resets.715150638 |
|
|
Mar 24 03:20:02 PM PDT 24 |
Mar 24 03:28:20 PM PDT 24 |
4746264504 ps |
| T312 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_nmi_irq.2874006127 |
|
|
Mar 24 03:26:44 PM PDT 24 |
Mar 24 03:40:06 PM PDT 24 |
4022466340 ps |
| T676 |
/workspace/coverage/default/2.chip_sw_aon_timer_wdog_lc_escalate.4255304900 |
|
|
Mar 24 03:42:10 PM PDT 24 |
Mar 24 03:55:01 PM PDT 24 |
4837668402 ps |
| T677 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_all_reset_reqs.740840812 |
|
|
Mar 24 03:22:19 PM PDT 24 |
Mar 24 03:50:54 PM PDT 24 |
10720078017 ps |
| T678 |
/workspace/coverage/default/0.chip_sw_flash_init_reduced_freq.2596217957 |
|
|
Mar 24 03:22:48 PM PDT 24 |
Mar 24 03:58:01 PM PDT 24 |
22892043347 ps |
| T679 |
/workspace/coverage/default/1.chip_sw_example_rom.3002137611 |
|
|
Mar 24 03:26:32 PM PDT 24 |
Mar 24 03:28:23 PM PDT 24 |
2164987248 ps |
| T680 |
/workspace/coverage/default/0.chip_sw_kmac_mode_cshake.880056848 |
|
|
Mar 24 03:22:49 PM PDT 24 |
Mar 24 03:27:07 PM PDT 24 |
2981549004 ps |
| T499 |
/workspace/coverage/default/69.chip_sw_alert_handler_lpg_sleep_mode_alerts.1465663304 |
|
|
Mar 24 03:54:34 PM PDT 24 |
Mar 24 04:00:41 PM PDT 24 |
3492112412 ps |
| T681 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_rst.3150649183 |
|
|
Mar 24 03:29:36 PM PDT 24 |
Mar 24 03:33:59 PM PDT 24 |
2308175192 ps |
| T452 |
/workspace/coverage/default/22.chip_sw_all_escalation_resets.806948203 |
|
|
Mar 24 03:50:39 PM PDT 24 |
Mar 24 04:01:13 PM PDT 24 |
5399152240 ps |
| T682 |
/workspace/coverage/default/0.rom_e2e_shutdown_output.3798832932 |
|
|
Mar 24 03:30:30 PM PDT 24 |
Mar 24 04:18:37 PM PDT 24 |
25809755729 ps |
| T683 |
/workspace/coverage/default/82.chip_sw_all_escalation_resets.2524446516 |
|
|
Mar 24 03:55:29 PM PDT 24 |
Mar 24 04:03:39 PM PDT 24 |
4614238500 ps |
| T684 |
/workspace/coverage/default/2.chip_sw_alert_handler_ping_timeout.2671925650 |
|
|
Mar 24 03:44:03 PM PDT 24 |
Mar 24 03:53:17 PM PDT 24 |
5056415736 ps |
| T327 |
/workspace/coverage/default/0.chip_sw_keymgr_sideload_aes.3881714208 |
|
|
Mar 24 03:21:19 PM PDT 24 |
Mar 24 03:32:39 PM PDT 24 |
5461998968 ps |
| T685 |
/workspace/coverage/default/0.rom_e2e_smoke.3053805794 |
|
|
Mar 24 03:25:39 PM PDT 24 |
Mar 24 03:59:48 PM PDT 24 |
8851455718 ps |
| T372 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_ops_jitter_en.491002891 |
|
|
Mar 24 03:41:56 PM PDT 24 |
Mar 24 03:55:24 PM PDT 24 |
4591917001 ps |
| T263 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_address_translation.3572389000 |
|
|
Mar 24 03:45:36 PM PDT 24 |
Mar 24 03:50:03 PM PDT 24 |
2472355316 ps |
| T686 |
/workspace/coverage/default/0.chip_sw_rstmgr_sw_rst.2587854125 |
|
|
Mar 24 03:21:51 PM PDT 24 |
Mar 24 03:26:04 PM PDT 24 |
2973652606 ps |
| T687 |
/workspace/coverage/default/7.chip_sw_lc_ctrl_transition.2280706052 |
|
|
Mar 24 03:49:08 PM PDT 24 |
Mar 24 03:59:34 PM PDT 24 |
7115141715 ps |
| T688 |
/workspace/coverage/default/1.chip_sw_rstmgr_sw_req.2395548914 |
|
|
Mar 24 03:29:50 PM PDT 24 |
Mar 24 03:39:19 PM PDT 24 |
4823222832 ps |
| T451 |
/workspace/coverage/default/3.chip_sw_all_escalation_resets.3686677858 |
|
|
Mar 24 03:47:29 PM PDT 24 |
Mar 24 03:57:33 PM PDT 24 |
5359912416 ps |