| T425 |
/workspace/coverage/default/78.chip_sw_all_escalation_resets.2278982972 |
|
|
Mar 24 04:01:13 PM PDT 24 |
Mar 24 04:09:52 PM PDT 24 |
5512940594 ps |
| T689 |
/workspace/coverage/default/0.chip_sw_flash_crash_alert.2501315738 |
|
|
Mar 24 03:23:10 PM PDT 24 |
Mar 24 03:34:17 PM PDT 24 |
4558225030 ps |
| T690 |
/workspace/coverage/default/1.chip_sw_csrng_edn_concurrency_reduced_freq.2203525946 |
|
|
Mar 24 03:37:16 PM PDT 24 |
Mar 24 04:25:34 PM PDT 24 |
17001593551 ps |
| T82 |
/workspace/coverage/default/0.chip_sw_rom_ctrl_integrity_check.1952296333 |
|
|
Mar 24 03:19:56 PM PDT 24 |
Mar 24 03:28:51 PM PDT 24 |
8263862887 ps |
| T691 |
/workspace/coverage/default/2.rom_keymgr_functest.4237606466 |
|
|
Mar 24 03:47:29 PM PDT 24 |
Mar 24 03:56:04 PM PDT 24 |
5104572580 ps |
| T187 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_vendor_test_csr_access.1529964244 |
|
|
Mar 24 03:28:34 PM PDT 24 |
Mar 24 03:32:28 PM PDT 24 |
2386735170 ps |
| T500 |
/workspace/coverage/default/89.chip_sw_alert_handler_lpg_sleep_mode_alerts.1931864184 |
|
|
Mar 24 03:56:41 PM PDT 24 |
Mar 24 04:02:41 PM PDT 24 |
4392056840 ps |
| T692 |
/workspace/coverage/default/2.chip_sw_clkmgr_reset_frequency.1210495281 |
|
|
Mar 24 03:44:12 PM PDT 24 |
Mar 24 03:49:18 PM PDT 24 |
3259277860 ps |
| T693 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en.2482637709 |
|
|
Mar 24 03:30:22 PM PDT 24 |
Mar 24 03:46:11 PM PDT 24 |
5200344025 ps |
| T694 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_lc_signals_test_unlocked0.1267678427 |
|
|
Mar 24 03:30:02 PM PDT 24 |
Mar 24 03:41:33 PM PDT 24 |
3896726120 ps |
| T695 |
/workspace/coverage/default/0.chip_sw_pwrmgr_sleep_wake_5_bug.1901942176 |
|
|
Mar 24 03:23:48 PM PDT 24 |
Mar 24 03:29:10 PM PDT 24 |
5156865530 ps |
| T126 |
/workspace/coverage/default/29.chip_sw_alert_handler_lpg_sleep_mode_alerts.167460345 |
|
|
Mar 24 03:51:36 PM PDT 24 |
Mar 24 03:58:10 PM PDT 24 |
3717007080 ps |
| T426 |
/workspace/coverage/default/67.chip_sw_alert_handler_lpg_sleep_mode_alerts.3227074138 |
|
|
Mar 24 03:54:22 PM PDT 24 |
Mar 24 04:02:02 PM PDT 24 |
4147413892 ps |
| T377 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2742377110 |
|
|
Mar 24 03:22:57 PM PDT 24 |
Mar 24 03:32:16 PM PDT 24 |
4361095981 ps |
| T696 |
/workspace/coverage/default/0.chip_sw_kmac_mode_kmac_jitter_en.4227875636 |
|
|
Mar 24 03:19:22 PM PDT 24 |
Mar 24 03:22:59 PM PDT 24 |
2633329392 ps |
| T697 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_transition.3978359634 |
|
|
Mar 24 03:28:32 PM PDT 24 |
Mar 24 03:46:04 PM PDT 24 |
10920554475 ps |
| T698 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_reset_reqs.1586503452 |
|
|
Mar 24 03:39:52 PM PDT 24 |
Mar 24 04:01:47 PM PDT 24 |
17244749688 ps |
| T699 |
/workspace/coverage/default/2.chip_sw_kmac_mode_kmac_jitter_en_reduced_freq.3431852788 |
|
|
Mar 24 03:48:52 PM PDT 24 |
Mar 24 03:53:47 PM PDT 24 |
3167604717 ps |
| T700 |
/workspace/coverage/default/2.chip_sw_edn_sw_mode.2015246224 |
|
|
Mar 24 03:42:13 PM PDT 24 |
Mar 24 04:12:44 PM PDT 24 |
9318449616 ps |
| T701 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_clkoff.2303979968 |
|
|
Mar 24 03:21:45 PM PDT 24 |
Mar 24 03:51:35 PM PDT 24 |
7488515788 ps |
| T270 |
/workspace/coverage/default/23.chip_sw_all_escalation_resets.2835672725 |
|
|
Mar 24 03:52:30 PM PDT 24 |
Mar 24 04:01:25 PM PDT 24 |
5952085064 ps |
| T35 |
/workspace/coverage/default/0.chip_sw_spi_device_tpm.3505900696 |
|
|
Mar 24 03:21:18 PM PDT 24 |
Mar 24 03:28:22 PM PDT 24 |
3377623826 ps |
| T702 |
/workspace/coverage/default/1.chip_sw_pwrmgr_all_reset_reqs.3749431393 |
|
|
Mar 24 03:30:22 PM PDT 24 |
Mar 24 03:54:16 PM PDT 24 |
12221508795 ps |
| T505 |
/workspace/coverage/default/78.chip_sw_alert_handler_lpg_sleep_mode_alerts.3534763769 |
|
|
Mar 24 03:55:43 PM PDT 24 |
Mar 24 04:00:55 PM PDT 24 |
4226684160 ps |
| T703 |
/workspace/coverage/default/1.chip_sw_pwrmgr_main_power_glitch_reset.4285320310 |
|
|
Mar 24 03:30:15 PM PDT 24 |
Mar 24 03:35:33 PM PDT 24 |
4809962616 ps |
| T704 |
/workspace/coverage/default/0.rom_keymgr_functest.49221270 |
|
|
Mar 24 03:26:29 PM PDT 24 |
Mar 24 03:37:39 PM PDT 24 |
5040336768 ps |
| T483 |
/workspace/coverage/default/38.chip_sw_all_escalation_resets.1237995029 |
|
|
Mar 24 03:51:58 PM PDT 24 |
Mar 24 04:02:57 PM PDT 24 |
5162991216 ps |
| T393 |
/workspace/coverage/default/0.chip_sw_edn_boot_mode.2462185775 |
|
|
Mar 24 03:19:37 PM PDT 24 |
Mar 24 03:29:36 PM PDT 24 |
3337226178 ps |
| T174 |
/workspace/coverage/default/0.chip_sw_usbdev_vbus.1955677101 |
|
|
Mar 24 03:20:16 PM PDT 24 |
Mar 24 03:24:40 PM PDT 24 |
3207245090 ps |
| T21 |
/workspace/coverage/default/0.chip_sw_usbdev_setuprx.2286361381 |
|
|
Mar 24 03:21:08 PM PDT 24 |
Mar 24 03:30:22 PM PDT 24 |
3921468892 ps |
| T213 |
/workspace/coverage/default/0.chip_sw_i2c_host_tx_rx_idx1.4156492256 |
|
|
Mar 24 03:22:02 PM PDT 24 |
Mar 24 03:32:37 PM PDT 24 |
5283708200 ps |
| T155 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.2585358740 |
|
|
Mar 24 03:34:11 PM PDT 24 |
Mar 24 03:42:12 PM PDT 24 |
4768272388 ps |
| T705 |
/workspace/coverage/default/10.chip_sw_uart_rand_baudrate.1992775563 |
|
|
Mar 24 03:48:42 PM PDT 24 |
Mar 24 04:01:08 PM PDT 24 |
4874310068 ps |
| T477 |
/workspace/coverage/default/19.chip_sw_alert_handler_lpg_sleep_mode_alerts.1715266075 |
|
|
Mar 24 03:50:00 PM PDT 24 |
Mar 24 03:55:45 PM PDT 24 |
3751115270 ps |
| T472 |
/workspace/coverage/default/27.chip_sw_all_escalation_resets.661819136 |
|
|
Mar 24 03:52:33 PM PDT 24 |
Mar 24 04:02:29 PM PDT 24 |
6192581464 ps |
| T706 |
/workspace/coverage/default/1.chip_sw_lc_walkthrough_testunlocks.1704999789 |
|
|
Mar 24 03:30:02 PM PDT 24 |
Mar 24 04:03:53 PM PDT 24 |
26765535192 ps |
| T87 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through_collision.1551994264 |
|
|
Mar 24 03:27:47 PM PDT 24 |
Mar 24 03:36:21 PM PDT 24 |
4947363001 ps |
| T707 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_rma.4286951536 |
|
|
Mar 24 03:45:23 PM PDT 24 |
Mar 24 03:56:40 PM PDT 24 |
4367006316 ps |
| T331 |
/workspace/coverage/default/2.chip_sw_keymgr_sideload_otbn.798883058 |
|
|
Mar 24 03:42:35 PM PDT 24 |
Mar 24 04:48:57 PM PDT 24 |
16996333240 ps |
| T708 |
/workspace/coverage/default/0.chip_sw_edn_sw_mode.1444299578 |
|
|
Mar 24 03:19:55 PM PDT 24 |
Mar 24 04:01:19 PM PDT 24 |
11219517200 ps |
| T387 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs.1642733142 |
|
|
Mar 24 03:43:53 PM PDT 24 |
Mar 24 04:03:07 PM PDT 24 |
5609646960 ps |
| T709 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access.1226687959 |
|
|
Mar 24 03:22:04 PM PDT 24 |
Mar 24 03:42:20 PM PDT 24 |
5678120288 ps |
| T436 |
/workspace/coverage/default/77.chip_sw_all_escalation_resets.4271839426 |
|
|
Mar 24 03:56:26 PM PDT 24 |
Mar 24 04:04:37 PM PDT 24 |
5458200680 ps |
| T461 |
/workspace/coverage/default/7.chip_sw_alert_handler_lpg_sleep_mode_alerts.2748661804 |
|
|
Mar 24 03:49:39 PM PDT 24 |
Mar 24 03:56:52 PM PDT 24 |
3400549700 ps |
| T710 |
/workspace/coverage/default/0.chip_sw_aes_masking_off.4076749603 |
|
|
Mar 24 03:22:35 PM PDT 24 |
Mar 24 03:27:17 PM PDT 24 |
2351481927 ps |
| T711 |
/workspace/coverage/default/0.chip_sw_lc_walkthrough_testunlocks.2308770628 |
|
|
Mar 24 03:24:57 PM PDT 24 |
Mar 24 04:00:03 PM PDT 24 |
27446152355 ps |
| T712 |
/workspace/coverage/default/0.chip_sw_rstmgr_smoketest.971181461 |
|
|
Mar 24 03:28:10 PM PDT 24 |
Mar 24 03:32:00 PM PDT 24 |
2382341624 ps |
| T511 |
/workspace/coverage/default/54.chip_sw_all_escalation_resets.1882260089 |
|
|
Mar 24 03:53:11 PM PDT 24 |
Mar 24 04:02:06 PM PDT 24 |
4426397944 ps |
| T713 |
/workspace/coverage/default/1.chip_sw_otbn_smoketest.2254332626 |
|
|
Mar 24 03:38:42 PM PDT 24 |
Mar 24 03:56:12 PM PDT 24 |
5566133976 ps |
| T714 |
/workspace/coverage/default/2.chip_sw_lc_walkthrough_rma.3909789942 |
|
|
Mar 24 03:40:30 PM PDT 24 |
Mar 24 05:02:19 PM PDT 24 |
48646780676 ps |
| T494 |
/workspace/coverage/default/26.chip_sw_alert_handler_lpg_sleep_mode_alerts.2126053359 |
|
|
Mar 24 03:51:05 PM PDT 24 |
Mar 24 03:56:33 PM PDT 24 |
4003135072 ps |
| T715 |
/workspace/coverage/default/4.chip_tap_straps_prod.2152742008 |
|
|
Mar 24 03:47:25 PM PDT 24 |
Mar 24 03:51:14 PM PDT 24 |
2772504838 ps |
| T716 |
/workspace/coverage/default/1.chip_tap_straps_prod.1910715707 |
|
|
Mar 24 03:36:03 PM PDT 24 |
Mar 24 03:46:51 PM PDT 24 |
5569172342 ps |
| T478 |
/workspace/coverage/default/12.chip_sw_all_escalation_resets.356698347 |
|
|
Mar 24 03:50:42 PM PDT 24 |
Mar 24 04:00:04 PM PDT 24 |
5612986248 ps |
| T717 |
/workspace/coverage/default/0.chip_tap_straps_prod.747821281 |
|
|
Mar 24 03:24:23 PM PDT 24 |
Mar 24 03:27:05 PM PDT 24 |
2894398164 ps |
| T718 |
/workspace/coverage/default/0.chip_sw_csrng_edn_concurrency.3846697158 |
|
|
Mar 24 03:21:35 PM PDT 24 |
Mar 24 04:40:18 PM PDT 24 |
20747777496 ps |
| T719 |
/workspace/coverage/default/0.chip_sw_otbn_mem_scramble.963686498 |
|
|
Mar 24 03:24:26 PM PDT 24 |
Mar 24 03:31:37 PM PDT 24 |
3437731198 ps |
| T720 |
/workspace/coverage/default/0.chip_sw_aon_timer_wdog_bite_reset.2693393403 |
|
|
Mar 24 03:22:19 PM PDT 24 |
Mar 24 03:37:47 PM PDT 24 |
10140747960 ps |
| T491 |
/workspace/coverage/default/56.chip_sw_all_escalation_resets.2353607544 |
|
|
Mar 24 03:56:37 PM PDT 24 |
Mar 24 04:06:47 PM PDT 24 |
5858393608 ps |
| T721 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_nothing_b_bad_prod_end.3750633681 |
|
|
Mar 24 03:29:55 PM PDT 24 |
Mar 24 04:05:36 PM PDT 24 |
8769562616 ps |
| T514 |
/workspace/coverage/default/45.chip_sw_alert_handler_lpg_sleep_mode_alerts.1171776605 |
|
|
Mar 24 03:54:25 PM PDT 24 |
Mar 24 03:58:44 PM PDT 24 |
3730256688 ps |
| T722 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_prod_end.1525898606 |
|
|
Mar 24 03:28:37 PM PDT 24 |
Mar 24 04:04:09 PM PDT 24 |
9079127286 ps |
| T60 |
/workspace/coverage/default/2.chip_sw_sleep_pin_wake.4122055265 |
|
|
Mar 24 03:39:36 PM PDT 24 |
Mar 24 03:45:32 PM PDT 24 |
5348953000 ps |
| T401 |
/workspace/coverage/default/0.chip_sw_otbn_ecdsa_op_irq.3375934619 |
|
|
Mar 24 03:23:28 PM PDT 24 |
Mar 24 04:26:05 PM PDT 24 |
17173816180 ps |
| T311 |
/workspace/coverage/default/50.chip_sw_all_escalation_resets.4100678219 |
|
|
Mar 24 03:53:53 PM PDT 24 |
Mar 24 04:01:55 PM PDT 24 |
4829372248 ps |
| T355 |
/workspace/coverage/default/1.chip_sw_pattgen_ios.2933818596 |
|
|
Mar 24 03:27:29 PM PDT 24 |
Mar 24 03:31:50 PM PDT 24 |
3120226712 ps |
| T402 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_rnd.720777650 |
|
|
Mar 24 03:32:46 PM PDT 24 |
Mar 24 03:47:42 PM PDT 24 |
5493268350 ps |
| T403 |
/workspace/coverage/default/4.chip_sw_alert_handler_lpg_sleep_mode_alerts.2153488298 |
|
|
Mar 24 03:48:14 PM PDT 24 |
Mar 24 03:55:12 PM PDT 24 |
3528869700 ps |
| T404 |
/workspace/coverage/default/16.chip_sw_uart_rand_baudrate.4055850210 |
|
|
Mar 24 03:49:44 PM PDT 24 |
Mar 24 03:58:50 PM PDT 24 |
4727587960 ps |
| T405 |
/workspace/coverage/default/2.chip_sw_entropy_src_smoketest.1565139824 |
|
|
Mar 24 03:47:20 PM PDT 24 |
Mar 24 03:55:07 PM PDT 24 |
3396720728 ps |
| T406 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_smoketest.2735210674 |
|
|
Mar 24 03:26:53 PM PDT 24 |
Mar 24 03:32:38 PM PDT 24 |
3738887734 ps |
| T407 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en_reduced_freq.2940770081 |
|
|
Mar 24 03:37:06 PM PDT 24 |
Mar 24 03:40:51 PM PDT 24 |
3081637008 ps |
| T723 |
/workspace/coverage/default/0.chip_sw_csrng_kat_test.3433646039 |
|
|
Mar 24 03:24:09 PM PDT 24 |
Mar 24 03:28:08 PM PDT 24 |
2652880410 ps |
| T724 |
/workspace/coverage/default/1.chip_sw_example_flash.2348729495 |
|
|
Mar 24 03:27:17 PM PDT 24 |
Mar 24 03:31:38 PM PDT 24 |
2901575908 ps |
| T725 |
/workspace/coverage/default/3.chip_sw_uart_tx_rx_idx2.2287091036 |
|
|
Mar 24 03:48:25 PM PDT 24 |
Mar 24 04:00:43 PM PDT 24 |
5291253764 ps |
| T726 |
/workspace/coverage/default/2.chip_sw_flash_crash_alert.1982176204 |
|
|
Mar 24 03:46:02 PM PDT 24 |
Mar 24 03:54:18 PM PDT 24 |
4208988208 ps |
| T727 |
/workspace/coverage/default/1.chip_sw_rv_plic_smoketest.2290074511 |
|
|
Mar 24 03:38:49 PM PDT 24 |
Mar 24 03:43:37 PM PDT 24 |
3143895200 ps |
| T271 |
/workspace/coverage/default/1.chip_sw_rstmgr_cpu_info.1594304267 |
|
|
Mar 24 03:29:51 PM PDT 24 |
Mar 24 03:38:20 PM PDT 24 |
5191985610 ps |
| T728 |
/workspace/coverage/default/60.chip_sw_all_escalation_resets.88976671 |
|
|
Mar 24 03:53:55 PM PDT 24 |
Mar 24 04:03:27 PM PDT 24 |
5995886898 ps |
| T729 |
/workspace/coverage/default/0.chip_sw_pwrmgr_usb_clk_disabled_when_active.3983043571 |
|
|
Mar 24 03:25:25 PM PDT 24 |
Mar 24 03:35:05 PM PDT 24 |
4893106564 ps |
| T730 |
/workspace/coverage/default/52.chip_sw_all_escalation_resets.2617965449 |
|
|
Mar 24 03:52:05 PM PDT 24 |
Mar 24 04:00:41 PM PDT 24 |
4650610980 ps |
| T731 |
/workspace/coverage/default/0.chip_sw_kmac_smoketest.739599399 |
|
|
Mar 24 03:25:43 PM PDT 24 |
Mar 24 03:30:52 PM PDT 24 |
2948169896 ps |
| T732 |
/workspace/coverage/default/2.rom_e2e_smoke.3770430326 |
|
|
Mar 24 03:47:32 PM PDT 24 |
Mar 24 04:20:07 PM PDT 24 |
8572378946 ps |
| T383 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_lockstep_glitch.553380133 |
|
|
Mar 24 03:36:59 PM PDT 24 |
Mar 24 03:40:15 PM PDT 24 |
2687762400 ps |
| T733 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access_jitter_en.3183762380 |
|
|
Mar 24 03:21:59 PM PDT 24 |
Mar 24 03:31:43 PM PDT 24 |
4365528372 ps |
| T734 |
/workspace/coverage/default/0.chip_sw_rv_plic_smoketest.3801328588 |
|
|
Mar 24 03:26:22 PM PDT 24 |
Mar 24 03:30:24 PM PDT 24 |
2557621550 ps |
| T735 |
/workspace/coverage/default/0.chip_sw_aes_smoketest.2750092638 |
|
|
Mar 24 03:26:28 PM PDT 24 |
Mar 24 03:30:06 PM PDT 24 |
2422150740 ps |
| T736 |
/workspace/coverage/default/96.chip_sw_all_escalation_resets.1162816563 |
|
|
Mar 24 03:57:02 PM PDT 24 |
Mar 24 04:05:13 PM PDT 24 |
5563926768 ps |
| T476 |
/workspace/coverage/default/31.chip_sw_alert_handler_lpg_sleep_mode_alerts.758268898 |
|
|
Mar 24 03:51:37 PM PDT 24 |
Mar 24 03:58:03 PM PDT 24 |
4192393988 ps |
| T737 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_prod_end.2600599637 |
|
|
Mar 24 03:31:08 PM PDT 24 |
Mar 24 04:21:17 PM PDT 24 |
11151140415 ps |
| T738 |
/workspace/coverage/default/1.chip_sw_keymgr_key_derivation_jitter_en_reduced_freq.2849582700 |
|
|
Mar 24 03:37:57 PM PDT 24 |
Mar 24 03:45:41 PM PDT 24 |
3701164913 ps |
| T739 |
/workspace/coverage/default/1.chip_sw_csrng_fuse_en_sw_app_read_test.1891738196 |
|
|
Mar 24 03:33:59 PM PDT 24 |
Mar 24 03:41:04 PM PDT 24 |
3240741830 ps |
| T740 |
/workspace/coverage/default/1.chip_sw_pwrmgr_smoketest.1296776997 |
|
|
Mar 24 03:40:01 PM PDT 24 |
Mar 24 03:46:59 PM PDT 24 |
4861354158 ps |
| T741 |
/workspace/coverage/default/0.chip_sw_pwrmgr_b2b_sleep_reset_req.2072235475 |
|
|
Mar 24 03:22:26 PM PDT 24 |
Mar 24 04:11:47 PM PDT 24 |
29095345831 ps |
| T742 |
/workspace/coverage/default/1.chip_sw_aon_timer_wdog_bite_reset.1470561860 |
|
|
Mar 24 03:33:22 PM PDT 24 |
Mar 24 03:49:51 PM PDT 24 |
9471012146 ps |
| T743 |
/workspace/coverage/default/2.chip_sw_alert_handler_lpg_reset_toggle.1372352142 |
|
|
Mar 24 03:44:19 PM PDT 24 |
Mar 24 04:08:56 PM PDT 24 |
7652623208 ps |
| T744 |
/workspace/coverage/default/0.chip_sw_edn_kat.309054274 |
|
|
Mar 24 03:21:45 PM PDT 24 |
Mar 24 03:33:27 PM PDT 24 |
3252460572 ps |
| T745 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_prod.2473550547 |
|
|
Mar 24 03:31:01 PM PDT 24 |
Mar 24 04:05:39 PM PDT 24 |
9398215808 ps |
| T149 |
/workspace/coverage/default/2.chip_sw_csrng_edn_concurrency_reduced_freq.326634083 |
|
|
Mar 24 03:47:34 PM PDT 24 |
Mar 24 04:32:58 PM PDT 24 |
16500787459 ps |
| T746 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_lc_rw_en.776019710 |
|
|
Mar 24 03:29:27 PM PDT 24 |
Mar 24 03:37:22 PM PDT 24 |
4846034099 ps |
| T431 |
/workspace/coverage/default/59.chip_sw_alert_handler_lpg_sleep_mode_alerts.1082056598 |
|
|
Mar 24 03:54:04 PM PDT 24 |
Mar 24 04:00:39 PM PDT 24 |
3403177144 ps |
| T394 |
/workspace/coverage/default/1.chip_sw_edn_boot_mode.2850607638 |
|
|
Mar 24 03:32:45 PM PDT 24 |
Mar 24 03:39:54 PM PDT 24 |
2897138160 ps |
| T191 |
/workspace/coverage/default/67.chip_sw_all_escalation_resets.3445164491 |
|
|
Mar 24 03:53:49 PM PDT 24 |
Mar 24 04:01:40 PM PDT 24 |
4558427260 ps |
| T747 |
/workspace/coverage/default/2.chip_sw_pwrmgr_full_aon_reset.46941510 |
|
|
Mar 24 03:44:51 PM PDT 24 |
Mar 24 03:52:16 PM PDT 24 |
8033157064 ps |
| T748 |
/workspace/coverage/default/39.chip_sw_all_escalation_resets.1495437546 |
|
|
Mar 24 03:50:59 PM PDT 24 |
Mar 24 04:00:54 PM PDT 24 |
5336525916 ps |
| T417 |
/workspace/coverage/default/2.rom_volatile_raw_unlock.816814722 |
|
|
Mar 24 03:48:42 PM PDT 24 |
Mar 24 03:50:29 PM PDT 24 |
2613287502 ps |
| T749 |
/workspace/coverage/default/1.chip_sw_data_integrity_escalation.4090039229 |
|
|
Mar 24 03:28:50 PM PDT 24 |
Mar 24 03:38:11 PM PDT 24 |
5240802360 ps |
| T390 |
/workspace/coverage/default/1.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.2531864066 |
|
|
Mar 24 03:39:34 PM PDT 24 |
Mar 24 04:49:54 PM PDT 24 |
24767376760 ps |
| T750 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod_end.518026688 |
|
|
Mar 24 03:50:09 PM PDT 24 |
Mar 24 04:17:39 PM PDT 24 |
8494916396 ps |
| T258 |
/workspace/coverage/default/16.chip_sw_all_escalation_resets.295766277 |
|
|
Mar 24 03:53:14 PM PDT 24 |
Mar 24 04:01:46 PM PDT 24 |
4753062650 ps |
| T22 |
/workspace/coverage/default/0.chip_sw_usbdev_config_host.2590744865 |
|
|
Mar 24 03:18:46 PM PDT 24 |
Mar 24 03:51:36 PM PDT 24 |
8000986742 ps |
| T751 |
/workspace/coverage/default/2.chip_sw_clkmgr_external_clk_src_for_sw_slow_dev.2707333564 |
|
|
Mar 24 03:45:02 PM PDT 24 |
Mar 24 03:57:24 PM PDT 24 |
4888084980 ps |
| T409 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_nmi_irq.2583399637 |
|
|
Mar 24 03:42:54 PM PDT 24 |
Mar 24 03:59:24 PM PDT 24 |
4667253120 ps |
| T464 |
/workspace/coverage/default/43.chip_sw_all_escalation_resets.3097593596 |
|
|
Mar 24 03:53:19 PM PDT 24 |
Mar 24 03:59:37 PM PDT 24 |
5162211996 ps |
| T259 |
/workspace/coverage/default/99.chip_sw_all_escalation_resets.3179799400 |
|
|
Mar 24 03:57:01 PM PDT 24 |
Mar 24 04:10:49 PM PDT 24 |
6357001792 ps |
| T182 |
/workspace/coverage/default/1.chip_sw_alert_handler_entropy.3754517890 |
|
|
Mar 24 03:33:53 PM PDT 24 |
Mar 24 03:39:15 PM PDT 24 |
3333041521 ps |
| T202 |
/workspace/coverage/default/2.chip_sw_flash_rma_unlocked.2376652828 |
|
|
Mar 24 03:42:19 PM PDT 24 |
Mar 24 05:06:42 PM PDT 24 |
43204411198 ps |
| T176 |
/workspace/coverage/default/0.chip_plic_all_irqs_20.3023212853 |
|
|
Mar 24 03:20:22 PM PDT 24 |
Mar 24 03:33:44 PM PDT 24 |
4758009578 ps |
| T168 |
/workspace/coverage/default/0.chip_plic_all_irqs_10.2128135008 |
|
|
Mar 24 03:21:08 PM PDT 24 |
Mar 24 03:30:13 PM PDT 24 |
4270081982 ps |
| T752 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_dev.3263069022 |
|
|
Mar 24 03:29:07 PM PDT 24 |
Mar 24 04:06:19 PM PDT 24 |
8821402740 ps |
| T753 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_good_dev.2423715367 |
|
|
Mar 24 03:28:45 PM PDT 24 |
Mar 24 04:00:05 PM PDT 24 |
8702117648 ps |
| T754 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_access_jitter_en_reduced_freq.3053885294 |
|
|
Mar 24 03:37:40 PM PDT 24 |
Mar 24 03:55:18 PM PDT 24 |
7108293025 ps |
| T391 |
/workspace/coverage/default/2.chip_sw_otbn_ecdsa_op_irq_jitter_en_reduced_freq.845453124 |
|
|
Mar 24 03:46:15 PM PDT 24 |
Mar 24 04:38:00 PM PDT 24 |
24760367632 ps |
| T442 |
/workspace/coverage/default/0.chip_sw_alert_handler_lpg_sleep_mode_pings.2618380509 |
|
|
Mar 24 03:20:14 PM PDT 24 |
Mar 24 03:40:09 PM PDT 24 |
10249367790 ps |
| T755 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sysrst_ctrl_reset.1628993700 |
|
|
Mar 24 03:31:23 PM PDT 24 |
Mar 24 03:54:26 PM PDT 24 |
6938506776 ps |
| T465 |
/workspace/coverage/default/44.chip_sw_all_escalation_resets.1832246680 |
|
|
Mar 24 03:53:19 PM PDT 24 |
Mar 24 04:01:41 PM PDT 24 |
4804178664 ps |
| T9 |
/workspace/coverage/default/0.chip_sw_sleep_pin_mio_dio_val.3422554305 |
|
|
Mar 24 03:21:36 PM PDT 24 |
Mar 24 03:25:28 PM PDT 24 |
2479431044 ps |
| T166 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through.1886572291 |
|
|
Mar 24 03:40:41 PM PDT 24 |
Mar 24 03:55:20 PM PDT 24 |
7432443902 ps |
| T59 |
/workspace/coverage/default/0.chip_sw_pwrmgr_random_sleep_all_wake_ups.3822224828 |
|
|
Mar 24 03:21:23 PM PDT 24 |
Mar 24 03:54:23 PM PDT 24 |
18933657432 ps |
| T62 |
/workspace/coverage/default/2.chip_sw_sleep_pin_retention.3323417437 |
|
|
Mar 24 03:39:32 PM PDT 24 |
Mar 24 03:43:55 PM PDT 24 |
3412461360 ps |
| T756 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_aes_trans.2516668734 |
|
|
Mar 24 03:44:28 PM PDT 24 |
Mar 24 03:51:42 PM PDT 24 |
4914600108 ps |
| T757 |
/workspace/coverage/default/1.chip_sw_clkmgr_reset_frequency.2763156340 |
|
|
Mar 24 03:34:19 PM PDT 24 |
Mar 24 03:42:02 PM PDT 24 |
3549231044 ps |
| T521 |
/workspace/coverage/default/57.chip_sw_all_escalation_resets.2447486974 |
|
|
Mar 24 03:53:37 PM PDT 24 |
Mar 24 04:01:35 PM PDT 24 |
4032970846 ps |
| T418 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_volatile_raw_unlock.856701208 |
|
|
Mar 24 03:19:22 PM PDT 24 |
Mar 24 03:21:08 PM PDT 24 |
1829390161 ps |
| T758 |
/workspace/coverage/default/2.chip_sw_rstmgr_rst_cnsty_escalation.492716964 |
|
|
Mar 24 03:39:47 PM PDT 24 |
Mar 24 03:51:53 PM PDT 24 |
6123704952 ps |
| T423 |
/workspace/coverage/default/52.chip_sw_alert_handler_lpg_sleep_mode_alerts.2016138985 |
|
|
Mar 24 03:53:00 PM PDT 24 |
Mar 24 03:59:59 PM PDT 24 |
4340921704 ps |
| T26 |
/workspace/coverage/default/1.chip_sw_gpio.3617400727 |
|
|
Mar 24 03:30:03 PM PDT 24 |
Mar 24 03:41:02 PM PDT 24 |
4123563312 ps |
| T759 |
/workspace/coverage/default/2.chip_sw_ast_clk_outputs.3205975386 |
|
|
Mar 24 03:44:32 PM PDT 24 |
Mar 24 04:00:27 PM PDT 24 |
6955031400 ps |
| T160 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sleep_sensor_ctrl_alert_wakeup.593584734 |
|
|
Mar 24 03:43:45 PM PDT 24 |
Mar 24 03:52:18 PM PDT 24 |
5368408700 ps |
| T413 |
/workspace/coverage/default/0.chip_sw_rv_dm_access_after_escalation_reset.225517238 |
|
|
Mar 24 03:22:57 PM PDT 24 |
Mar 24 03:31:54 PM PDT 24 |
5345609588 ps |
| T272 |
/workspace/coverage/default/0.chip_sw_rv_core_ibex_lockstep_glitch.657831497 |
|
|
Mar 24 03:22:15 PM PDT 24 |
Mar 24 03:24:41 PM PDT 24 |
2721527300 ps |
| T214 |
/workspace/coverage/default/1.chip_sw_i2c_host_tx_rx_idx1.2484596118 |
|
|
Mar 24 03:28:19 PM PDT 24 |
Mar 24 03:40:57 PM PDT 24 |
5705382656 ps |
| T295 |
/workspace/coverage/default/55.chip_sw_all_escalation_resets.552616659 |
|
|
Mar 24 03:55:09 PM PDT 24 |
Mar 24 04:05:00 PM PDT 24 |
4993594710 ps |
| T296 |
/workspace/coverage/default/2.chip_sw_clkmgr_off_peri.908721659 |
|
|
Mar 24 03:44:33 PM PDT 24 |
Mar 24 04:10:14 PM PDT 24 |
10247079736 ps |
| T297 |
/workspace/coverage/default/2.rom_e2e_shutdown_output.1029459875 |
|
|
Mar 24 03:53:33 PM PDT 24 |
Mar 24 04:40:06 PM PDT 24 |
27171110439 ps |
| T298 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_volatile_raw_unlock.3365622434 |
|
|
Mar 24 03:41:02 PM PDT 24 |
Mar 24 03:42:53 PM PDT 24 |
2217667785 ps |
| T299 |
/workspace/coverage/default/41.chip_sw_alert_handler_lpg_sleep_mode_alerts.1978599617 |
|
|
Mar 24 03:52:57 PM PDT 24 |
Mar 24 03:57:51 PM PDT 24 |
3504052000 ps |
| T300 |
/workspace/coverage/default/2.chip_sw_lc_ctrl_transition.2234240875 |
|
|
Mar 24 03:39:16 PM PDT 24 |
Mar 24 03:49:28 PM PDT 24 |
5477023219 ps |
| T301 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_idle_low_power.3342030244 |
|
|
Mar 24 03:20:18 PM PDT 24 |
Mar 24 03:24:24 PM PDT 24 |
3029610072 ps |
| T61 |
/workspace/coverage/default/1.chip_sw_sleep_pin_wake.823420266 |
|
|
Mar 24 03:27:44 PM PDT 24 |
Mar 24 03:33:49 PM PDT 24 |
5480967818 ps |
| T760 |
/workspace/coverage/default/0.chip_sw_uart_rand_baudrate.1921101106 |
|
|
Mar 24 03:25:21 PM PDT 24 |
Mar 24 03:38:14 PM PDT 24 |
4974916225 ps |
| T761 |
/workspace/coverage/default/1.chip_sw_example_concurrency.1136117170 |
|
|
Mar 24 03:28:15 PM PDT 24 |
Mar 24 03:32:04 PM PDT 24 |
2953338800 ps |
| T762 |
/workspace/coverage/default/1.chip_sw_sysrst_ctrl_inputs.2163501826 |
|
|
Mar 24 03:31:23 PM PDT 24 |
Mar 24 03:35:44 PM PDT 24 |
2749388735 ps |
| T238 |
/workspace/coverage/default/1.chip_sw_power_sleep_load.1707558977 |
|
|
Mar 24 03:36:23 PM PDT 24 |
Mar 24 03:42:21 PM PDT 24 |
4033505120 ps |
| T763 |
/workspace/coverage/default/1.chip_sw_exit_test_unlocked_bootstrap.2082197692 |
|
|
Mar 24 03:27:51 PM PDT 24 |
Mar 24 06:25:26 PM PDT 24 |
59573697001 ps |
| T83 |
/workspace/coverage/default/3.chip_sw_data_integrity_escalation.3080004790 |
|
|
Mar 24 03:48:07 PM PDT 24 |
Mar 24 04:00:41 PM PDT 24 |
5575558360 ps |
| T410 |
/workspace/coverage/default/1.chip_sw_rv_core_ibex_nmi_irq.906007935 |
|
|
Mar 24 03:33:02 PM PDT 24 |
Mar 24 03:46:21 PM PDT 24 |
5223061560 ps |
| T764 |
/workspace/coverage/default/2.chip_sw_entropy_src_ast_rng_req.3793726865 |
|
|
Mar 24 03:42:29 PM PDT 24 |
Mar 24 03:47:41 PM PDT 24 |
2242996530 ps |
| T177 |
/workspace/coverage/default/2.chip_plic_all_irqs_20.4001389589 |
|
|
Mar 24 03:44:40 PM PDT 24 |
Mar 24 03:59:25 PM PDT 24 |
4961195192 ps |
| T765 |
/workspace/coverage/default/1.chip_sw_otp_ctrl_smoketest.3090289639 |
|
|
Mar 24 03:38:31 PM PDT 24 |
Mar 24 03:43:34 PM PDT 24 |
3444316556 ps |
| T77 |
/workspace/coverage/default/0.chip_sw_alert_test.323962221 |
|
|
Mar 24 03:22:40 PM PDT 24 |
Mar 24 03:28:35 PM PDT 24 |
3515164392 ps |
| T508 |
/workspace/coverage/default/63.chip_sw_alert_handler_lpg_sleep_mode_alerts.1909689702 |
|
|
Mar 24 03:53:57 PM PDT 24 |
Mar 24 04:00:01 PM PDT 24 |
3031347688 ps |
| T766 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_otp_hw_cfg0.3881409078 |
|
|
Mar 24 03:20:18 PM PDT 24 |
Mar 24 03:24:36 PM PDT 24 |
3497132482 ps |
| T427 |
/workspace/coverage/default/38.chip_sw_alert_handler_lpg_sleep_mode_alerts.2703351525 |
|
|
Mar 24 03:51:41 PM PDT 24 |
Mar 24 03:59:18 PM PDT 24 |
4126476894 ps |
| T57 |
/workspace/coverage/default/2.chip_rv_dm_ndm_reset_req.1138473572 |
|
|
Mar 24 03:45:37 PM PDT 24 |
Mar 24 03:53:52 PM PDT 24 |
4945848506 ps |
| T32 |
/workspace/coverage/default/0.chip_sw_spi_host_tx_rx.1666541070 |
|
|
Mar 24 03:19:58 PM PDT 24 |
Mar 24 03:26:04 PM PDT 24 |
3105414980 ps |
| T767 |
/workspace/coverage/default/0.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.3216307822 |
|
|
Mar 24 03:26:03 PM PDT 24 |
Mar 24 03:35:46 PM PDT 24 |
3520119700 ps |
| T768 |
/workspace/coverage/default/4.chip_tap_straps_dev.88347935 |
|
|
Mar 24 03:47:39 PM PDT 24 |
Mar 24 04:03:55 PM PDT 24 |
10818205775 ps |
| T492 |
/workspace/coverage/default/61.chip_sw_alert_handler_lpg_sleep_mode_alerts.3466036698 |
|
|
Mar 24 03:54:01 PM PDT 24 |
Mar 24 03:59:29 PM PDT 24 |
4049976338 ps |
| T769 |
/workspace/coverage/default/2.chip_sw_otp_ctrl_lc_signals_dev.1552245997 |
|
|
Mar 24 03:41:59 PM PDT 24 |
Mar 24 04:03:08 PM PDT 24 |
7524664008 ps |
| T770 |
/workspace/coverage/default/0.rom_e2e_sigverify_always_a_bad_b_bad_test_unlocked0.3244143721 |
|
|
Mar 24 03:28:51 PM PDT 24 |
Mar 24 04:14:52 PM PDT 24 |
10003420400 ps |
| T771 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_ops_jitter_en_reduced_freq.2862022718 |
|
|
Mar 24 03:39:34 PM PDT 24 |
Mar 24 03:51:14 PM PDT 24 |
5333305985 ps |
| T512 |
/workspace/coverage/default/18.chip_sw_alert_handler_lpg_sleep_mode_alerts.3373807856 |
|
|
Mar 24 03:52:33 PM PDT 24 |
Mar 24 03:59:46 PM PDT 24 |
3568867526 ps |
| T63 |
/workspace/coverage/default/1.chip_sw_sleep_pin_retention.486619814 |
|
|
Mar 24 03:28:05 PM PDT 24 |
Mar 24 03:33:23 PM PDT 24 |
4073802476 ps |
| T507 |
/workspace/coverage/default/84.chip_sw_alert_handler_lpg_sleep_mode_alerts.2601339788 |
|
|
Mar 24 03:56:00 PM PDT 24 |
Mar 24 04:03:04 PM PDT 24 |
3455465842 ps |
| T399 |
/workspace/coverage/default/2.chip_sw_pwrmgr_deep_sleep_all_wake_ups.3928282904 |
|
|
Mar 24 03:45:18 PM PDT 24 |
Mar 24 04:12:37 PM PDT 24 |
21267113514 ps |
| T772 |
/workspace/coverage/default/39.chip_sw_alert_handler_lpg_sleep_mode_alerts.2339653335 |
|
|
Mar 24 03:51:56 PM PDT 24 |
Mar 24 04:00:10 PM PDT 24 |
3633161164 ps |
| T479 |
/workspace/coverage/default/76.chip_sw_all_escalation_resets.2994869821 |
|
|
Mar 24 03:56:40 PM PDT 24 |
Mar 24 04:05:09 PM PDT 24 |
5069547476 ps |
| T501 |
/workspace/coverage/default/43.chip_sw_alert_handler_lpg_sleep_mode_alerts.2519648438 |
|
|
Mar 24 03:54:19 PM PDT 24 |
Mar 24 04:00:33 PM PDT 24 |
3186720704 ps |
| T466 |
/workspace/coverage/default/29.chip_sw_all_escalation_resets.765030416 |
|
|
Mar 24 03:51:24 PM PDT 24 |
Mar 24 04:00:13 PM PDT 24 |
4183925176 ps |
| T773 |
/workspace/coverage/default/0.chip_sw_ast_clk_outputs.3786182556 |
|
|
Mar 24 03:21:40 PM PDT 24 |
Mar 24 03:38:12 PM PDT 24 |
6365036614 ps |
| T88 |
/workspace/coverage/default/2.chip_sw_spi_device_pass_through_collision.2830248555 |
|
|
Mar 24 03:40:19 PM PDT 24 |
Mar 24 03:50:05 PM PDT 24 |
4871995742 ps |
| T388 |
/workspace/coverage/default/0.chip_sw_edn_entropy_reqs_jitter.2540911467 |
|
|
Mar 24 03:22:02 PM PDT 24 |
Mar 24 03:37:11 PM PDT 24 |
5161433604 ps |
| T302 |
/workspace/coverage/default/28.chip_sw_all_escalation_resets.2471816811 |
|
|
Mar 24 03:52:19 PM PDT 24 |
Mar 24 04:00:40 PM PDT 24 |
4760715280 ps |
| T774 |
/workspace/coverage/default/1.chip_sw_clkmgr_external_clk_src_for_sw_fast_test_unlocked0.2710042442 |
|
|
Mar 24 03:39:15 PM PDT 24 |
Mar 24 03:49:56 PM PDT 24 |
3915747850 ps |
| T775 |
/workspace/coverage/default/0.chip_sw_exit_test_unlocked_bootstrap.2211098272 |
|
|
Mar 24 03:21:20 PM PDT 24 |
Mar 24 06:16:45 PM PDT 24 |
57956544113 ps |
| T346 |
/workspace/coverage/default/2.chip_jtag_mem_access.2371541403 |
|
|
Mar 24 03:37:39 PM PDT 24 |
Mar 24 04:05:51 PM PDT 24 |
13403211580 ps |
| T776 |
/workspace/coverage/default/0.chip_sw_lc_ctrl_rma_to_scrap.1830000441 |
|
|
Mar 24 03:21:21 PM PDT 24 |
Mar 24 03:23:50 PM PDT 24 |
2482347344 ps |
| T777 |
/workspace/coverage/default/0.chip_sw_pwrmgr_normal_sleep_por_reset.1276060531 |
|
|
Mar 24 03:20:29 PM PDT 24 |
Mar 24 03:32:51 PM PDT 24 |
5988527076 ps |
| T778 |
/workspace/coverage/default/68.chip_sw_alert_handler_lpg_sleep_mode_alerts.2891109239 |
|
|
Mar 24 04:00:14 PM PDT 24 |
Mar 24 04:07:17 PM PDT 24 |
3866634908 ps |
| T779 |
/workspace/coverage/default/0.chip_sw_clkmgr_off_kmac_trans.376249975 |
|
|
Mar 24 03:21:18 PM PDT 24 |
Mar 24 03:30:09 PM PDT 24 |
5689429184 ps |
| T780 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_no_scramble.1315692482 |
|
|
Mar 24 03:33:50 PM PDT 24 |
Mar 24 03:42:22 PM PDT 24 |
5213986136 ps |
| T781 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_scrambled_access.621153127 |
|
|
Mar 24 03:20:51 PM PDT 24 |
Mar 24 03:31:12 PM PDT 24 |
5559848140 ps |
| T371 |
/workspace/coverage/default/1.chip_sw_sensor_ctrl_status.920231103 |
|
|
Mar 24 03:34:51 PM PDT 24 |
Mar 24 03:39:26 PM PDT 24 |
2810630911 ps |
| T782 |
/workspace/coverage/default/1.chip_sw_flash_ctrl_clock_freqs.2477164194 |
|
|
Mar 24 03:28:35 PM PDT 24 |
Mar 24 03:45:09 PM PDT 24 |
5358452798 ps |
| T783 |
/workspace/coverage/default/1.chip_sw_hmac_enc.4013816830 |
|
|
Mar 24 03:33:29 PM PDT 24 |
Mar 24 03:39:03 PM PDT 24 |
2930640744 ps |
| T114 |
/workspace/coverage/default/0.chip_sw_sram_ctrl_execution_main.1848816295 |
|
|
Mar 24 03:21:49 PM PDT 24 |
Mar 24 03:33:41 PM PDT 24 |
6672984081 ps |
| T456 |
/workspace/coverage/default/53.chip_sw_alert_handler_lpg_sleep_mode_alerts.1927655267 |
|
|
Mar 24 03:54:18 PM PDT 24 |
Mar 24 03:59:51 PM PDT 24 |
4072299416 ps |
| T513 |
/workspace/coverage/default/53.chip_sw_all_escalation_resets.3734110361 |
|
|
Mar 24 03:53:21 PM PDT 24 |
Mar 24 04:03:41 PM PDT 24 |
5162655072 ps |
| T784 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_bad_b_good_prod_end.3210544415 |
|
|
Mar 24 03:31:06 PM PDT 24 |
Mar 24 04:23:41 PM PDT 24 |
11822558296 ps |
| T785 |
/workspace/coverage/default/0.chip_sw_uart_smoketest_signed.2550443647 |
|
|
Mar 24 03:32:02 PM PDT 24 |
Mar 24 04:10:00 PM PDT 24 |
8587942534 ps |
| T458 |
/workspace/coverage/default/6.chip_sw_all_escalation_resets.1645594752 |
|
|
Mar 24 03:50:00 PM PDT 24 |
Mar 24 04:03:58 PM PDT 24 |
6073195770 ps |
| T786 |
/workspace/coverage/default/1.rom_e2e_shutdown_exception_c.2731259479 |
|
|
Mar 24 03:43:45 PM PDT 24 |
Mar 24 04:18:21 PM PDT 24 |
9357108139 ps |
| T192 |
/workspace/coverage/default/0.chip_sw_otp_ctrl_escalation.3254499934 |
|
|
Mar 24 03:23:41 PM PDT 24 |
Mar 24 03:34:31 PM PDT 24 |
6035931560 ps |
| T787 |
/workspace/coverage/default/2.chip_sw_uart_tx_rx_idx2.566934029 |
|
|
Mar 24 03:39:02 PM PDT 24 |
Mar 24 03:53:09 PM PDT 24 |
5548673541 ps |
| T788 |
/workspace/coverage/default/1.chip_sw_hmac_enc_jitter_en.813039518 |
|
|
Mar 24 03:34:16 PM PDT 24 |
Mar 24 03:39:43 PM PDT 24 |
3159716609 ps |
| T789 |
/workspace/coverage/default/23.chip_sw_alert_handler_lpg_sleep_mode_alerts.3332145607 |
|
|
Mar 24 03:51:05 PM PDT 24 |
Mar 24 03:58:16 PM PDT 24 |
3941171658 ps |
| T790 |
/workspace/coverage/default/0.chip_sw_flash_ctrl_access_jitter_en.3174605925 |
|
|
Mar 24 03:21:02 PM PDT 24 |
Mar 24 03:37:51 PM PDT 24 |
5597732858 ps |
| T791 |
/workspace/coverage/default/1.chip_sival_flash_info_access.2701679720 |
|
|
Mar 24 03:27:25 PM PDT 24 |
Mar 24 03:32:05 PM PDT 24 |
2578452728 ps |
| T454 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_sleep_mode_alerts.1332247950 |
|
|
Mar 24 03:33:11 PM PDT 24 |
Mar 24 03:39:54 PM PDT 24 |
3424395576 ps |
| T792 |
/workspace/coverage/default/2.chip_sw_pwrmgr_sysrst_ctrl_reset.934547586 |
|
|
Mar 24 03:40:00 PM PDT 24 |
Mar 24 03:57:12 PM PDT 24 |
6328623420 ps |
| T793 |
/workspace/coverage/default/2.chip_sw_entropy_src_kat_test.1816484149 |
|
|
Mar 24 03:43:38 PM PDT 24 |
Mar 24 03:48:29 PM PDT 24 |
2712388716 ps |
| T794 |
/workspace/coverage/default/31.chip_sw_all_escalation_resets.2879011663 |
|
|
Mar 24 03:51:52 PM PDT 24 |
Mar 24 04:02:34 PM PDT 24 |
6094388588 ps |
| T795 |
/workspace/coverage/default/2.chip_sw_sleep_pwm_pulses.159424545 |
|
|
Mar 24 03:38:18 PM PDT 24 |
Mar 24 04:02:50 PM PDT 24 |
8425527064 ps |
| T376 |
/workspace/coverage/default/2.chip_sw_aon_timer_irq.2497663351 |
|
|
Mar 24 03:44:39 PM PDT 24 |
Mar 24 03:52:29 PM PDT 24 |
4185887180 ps |
| T503 |
/workspace/coverage/default/45.chip_sw_all_escalation_resets.376111847 |
|
|
Mar 24 03:53:59 PM PDT 24 |
Mar 24 04:05:06 PM PDT 24 |
4650939680 ps |
| T796 |
/workspace/coverage/default/1.chip_sw_spi_device_pass_through.1910770945 |
|
|
Mar 24 03:28:12 PM PDT 24 |
Mar 24 03:41:04 PM PDT 24 |
6969948567 ps |
| T797 |
/workspace/coverage/default/1.chip_sw_sleep_sram_ret_contents_scramble.3695329774 |
|
|
Mar 24 03:33:58 PM PDT 24 |
Mar 24 03:45:45 PM PDT 24 |
8712350816 ps |
| T798 |
/workspace/coverage/default/0.chip_sw_csrng_smoketest.3294886183 |
|
|
Mar 24 03:28:16 PM PDT 24 |
Mar 24 03:31:53 PM PDT 24 |
2298952624 ps |
| T23 |
/workspace/coverage/default/0.chip_sw_usbdev_dpi.3277215359 |
|
|
Mar 24 03:21:04 PM PDT 24 |
Mar 24 04:09:30 PM PDT 24 |
12331458288 ps |
| T799 |
/workspace/coverage/default/2.chip_sival_flash_info_access.3841038862 |
|
|
Mar 24 03:39:14 PM PDT 24 |
Mar 24 03:44:11 PM PDT 24 |
3325218864 ps |
| T800 |
/workspace/coverage/default/1.chip_sw_clkmgr_off_aes_trans.1024154566 |
|
|
Mar 24 03:35:03 PM PDT 24 |
Mar 24 03:42:53 PM PDT 24 |
5041138572 ps |
| T801 |
/workspace/coverage/default/2.chip_sw_flash_ctrl_clock_freqs.4057455318 |
|
|
Mar 24 03:38:45 PM PDT 24 |
Mar 24 03:57:03 PM PDT 24 |
5757306218 ps |
| T802 |
/workspace/coverage/default/1.chip_sw_edn_entropy_reqs.3409134389 |
|
|
Mar 24 03:33:38 PM PDT 24 |
Mar 24 03:53:22 PM PDT 24 |
4862966520 ps |
| T803 |
/workspace/coverage/default/74.chip_sw_all_escalation_resets.2201703078 |
|
|
Mar 24 03:54:23 PM PDT 24 |
Mar 24 04:05:43 PM PDT 24 |
5025245548 ps |
| T804 |
/workspace/coverage/default/1.chip_sw_pwrmgr_sleep_wake_5_bug.2879877603 |
|
|
Mar 24 03:36:04 PM PDT 24 |
Mar 24 03:43:30 PM PDT 24 |
6240328940 ps |
| T805 |
/workspace/coverage/default/0.rom_e2e_boot_policy_valid_a_good_b_bad_rma.3057380538 |
|
|
Mar 24 03:29:35 PM PDT 24 |
Mar 24 04:03:45 PM PDT 24 |
8454592334 ps |
| T806 |
/workspace/coverage/default/2.chip_sw_pwrmgr_usbdev_smoketest.442838265 |
|
|
Mar 24 03:49:15 PM PDT 24 |
Mar 24 03:54:06 PM PDT 24 |
5362969280 ps |
| T807 |
/workspace/coverage/default/2.chip_sw_clkmgr_jitter_frequency.714064206 |
|
|
Mar 24 03:46:09 PM PDT 24 |
Mar 24 03:53:09 PM PDT 24 |
3561533620 ps |
| T808 |
/workspace/coverage/default/1.chip_sw_example_manufacturer.2134795690 |
|
|
Mar 24 03:27:04 PM PDT 24 |
Mar 24 03:30:07 PM PDT 24 |
2472745500 ps |
| T809 |
/workspace/coverage/default/2.rom_e2e_asm_init_test_unlocked0.3734564227 |
|
|
Mar 24 03:53:56 PM PDT 24 |
Mar 24 04:15:10 PM PDT 24 |
6853268540 ps |
| T127 |
/workspace/coverage/default/62.chip_sw_alert_handler_lpg_sleep_mode_alerts.3040808323 |
|
|
Mar 24 03:54:30 PM PDT 24 |
Mar 24 04:00:56 PM PDT 24 |
4213655024 ps |
| T810 |
/workspace/coverage/default/3.chip_tap_straps_prod.2163637343 |
|
|
Mar 24 03:47:48 PM PDT 24 |
Mar 24 04:06:15 PM PDT 24 |
12991414057 ps |
| T811 |
/workspace/coverage/default/2.chip_sw_pwrmgr_all_reset_reqs.90504766 |
|
|
Mar 24 03:40:56 PM PDT 24 |
Mar 24 04:04:40 PM PDT 24 |
11074026429 ps |
| T812 |
/workspace/coverage/default/5.chip_sw_lc_ctrl_transition.2576330691 |
|
|
Mar 24 03:49:02 PM PDT 24 |
Mar 24 04:05:54 PM PDT 24 |
9471437412 ps |
| T813 |
/workspace/coverage/default/2.chip_sw_all_escalation_resets.688636758 |
|
|
Mar 24 03:39:26 PM PDT 24 |
Mar 24 03:47:58 PM PDT 24 |
4734745960 ps |
| T471 |
/workspace/coverage/default/73.chip_sw_alert_handler_lpg_sleep_mode_alerts.328635338 |
|
|
Mar 24 03:57:26 PM PDT 24 |
Mar 24 04:02:43 PM PDT 24 |
3960091428 ps |
| T814 |
/workspace/coverage/default/2.rom_e2e_asm_init_prod.3500707236 |
|
|
Mar 24 03:53:56 PM PDT 24 |
Mar 24 04:21:00 PM PDT 24 |
8507188581 ps |
| T496 |
/workspace/coverage/default/21.chip_sw_alert_handler_lpg_sleep_mode_alerts.3679624986 |
|
|
Mar 24 03:50:30 PM PDT 24 |
Mar 24 03:56:24 PM PDT 24 |
3062757980 ps |
| T815 |
/workspace/coverage/default/2.chip_tap_straps_dev.141177994 |
|
|
Mar 24 03:44:17 PM PDT 24 |
Mar 24 03:51:40 PM PDT 24 |
4260040626 ps |
| T516 |
/workspace/coverage/default/26.chip_sw_all_escalation_resets.3825738196 |
|
|
Mar 24 03:51:58 PM PDT 24 |
Mar 24 04:03:49 PM PDT 24 |
5537162398 ps |
| T816 |
/workspace/coverage/default/2.chip_sw_edn_entropy_reqs_jitter.3547629901 |
|
|
Mar 24 03:42:11 PM PDT 24 |
Mar 24 03:55:32 PM PDT 24 |
4636151915 ps |
| T463 |
/workspace/coverage/default/36.chip_sw_alert_handler_lpg_sleep_mode_alerts.201558313 |
|
|
Mar 24 03:54:21 PM PDT 24 |
Mar 24 03:59:54 PM PDT 24 |
3960440196 ps |
| T817 |
/workspace/coverage/default/1.rom_e2e_asm_init_dev.3613755167 |
|
|
Mar 24 03:45:42 PM PDT 24 |
Mar 24 04:17:33 PM PDT 24 |
9350989254 ps |
| T818 |
/workspace/coverage/default/1.chip_sw_alert_handler_lpg_clkoff.798191729 |
|
|
Mar 24 03:34:06 PM PDT 24 |
Mar 24 04:13:36 PM PDT 24 |
9659043928 ps |
| T819 |
/workspace/coverage/default/1.chip_sw_lc_ctrl_rand_to_scrap.2910630308 |
|
|
Mar 24 03:28:39 PM PDT 24 |
Mar 24 03:32:04 PM PDT 24 |
3181352783 ps |
| T470 |
/workspace/coverage/default/30.chip_sw_all_escalation_resets.2761627574 |
|
|
Mar 24 03:50:52 PM PDT 24 |
Mar 24 03:57:36 PM PDT 24 |
4813648952 ps |
| T820 |
/workspace/coverage/default/0.chip_sw_example_rom.3318804966 |
|
|
Mar 24 03:19:35 PM PDT 24 |
Mar 24 03:21:45 PM PDT 24 |
2164351656 ps |
| T821 |
/workspace/coverage/default/1.chip_sw_flash_scrambling_smoketest.3564948118 |
|
|
Mar 24 03:42:17 PM PDT 24 |
Mar 24 03:46:49 PM PDT 24 |
2926735148 ps |
| T822 |
/workspace/coverage/default/2.chip_sw_rv_core_ibex_rnd.3160805160 |
|
|
Mar 24 03:42:32 PM PDT 24 |
Mar 24 03:59:26 PM PDT 24 |
5492166878 ps |